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Remove redundant data from pci host generic

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The bus tag and handle fields are already stored in the resource. Use
this with the bus_read/bus_write helper macros.

Sponsored by:	Arm Ltd
This commit is contained in:
Andrew Turner 2023-04-24 12:11:29 +01:00
parent 078a69abcb
commit 8bc94f256e
4 changed files with 18 additions and 44 deletions
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28
sys/arm/broadcom/bcm2835/bcm2838_pci.c
View File

@ -168,16 +168,14 @@ static void
bcm_pcib_set_reg(struct bcm_pcib_softc *sc, uint32_t reg, uint32_t val) bcm_pcib_set_reg(struct bcm_pcib_softc *sc, uint32_t reg, uint32_t val)
{ {
bus_space_write_4(sc->base.base.bst, sc->base.base.bsh, reg, bus_write_4(sc->base.base.res, reg, htole32(val));
htole32(val));
} }
static uint32_t static uint32_t
bcm_pcib_read_reg(struct bcm_pcib_softc *sc, uint32_t reg) bcm_pcib_read_reg(struct bcm_pcib_softc *sc, uint32_t reg)
{ {
return (le32toh(bus_space_read_4(sc->base.base.bst, sc->base.base.bsh, return (le32toh(bus_read_4(sc->base.base.res, reg)));
reg)));
} }
static void static void
@ -318,8 +316,6 @@ bcm_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
int bytes) int bytes)
{ {
struct bcm_pcib_softc *sc; struct bcm_pcib_softc *sc;
bus_space_handle_t h;
bus_space_tag_t t;
bus_addr_t offset; bus_addr_t offset;
uint32_t data; uint32_t data;
@ -330,18 +326,15 @@ bcm_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
mtx_lock(&sc->config_mtx); mtx_lock(&sc->config_mtx);
offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg); offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg);
t = sc->base.base.bst;
h = sc->base.base.bsh;
switch (bytes) { switch (bytes) {
case 1: case 1:
data = bus_space_read_1(t, h, offset); data = bus_read_1(sc->base.base.res, offset);
break; break;
case 2: case 2:
data = le16toh(bus_space_read_2(t, h, offset)); data = le16toh(bus_read_2(sc->base.base.res, offset));
break; break;
case 4: case 4:
data = le32toh(bus_space_read_4(t, h, offset)); data = le32toh(bus_read_4(sc->base.base.res, offset));
break; break;
default: default:
data = ~0U; data = ~0U;
@ -357,8 +350,6 @@ bcm_pcib_write_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, uint32_t val, int bytes) u_int func, u_int reg, uint32_t val, int bytes)
{ {
struct bcm_pcib_softc *sc; struct bcm_pcib_softc *sc;
bus_space_handle_t h;
bus_space_tag_t t;
uint32_t offset; uint32_t offset;
sc = device_get_softc(dev); sc = device_get_softc(dev);
@ -368,18 +359,15 @@ bcm_pcib_write_config(device_t dev, u_int bus, u_int slot,
mtx_lock(&sc->config_mtx); mtx_lock(&sc->config_mtx);
offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg); offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg);
t = sc->base.base.bst;
h = sc->base.base.bsh;
switch (bytes) { switch (bytes) {
case 1: case 1:
bus_space_write_1(t, h, offset, val); bus_write_1(sc->base.base.res, offset, val);
break; break;
case 2: case 2:
bus_space_write_2(t, h, offset, htole16(val)); bus_write_2(sc->base.base.res, offset, htole16(val));
break; break;
case 4: case 4:
bus_space_write_4(t, h, offset, htole32(val)); bus_write_4(sc->base.base.res, offset, htole32(val));
break; break;
default: default:
break; break;

8
sys/dev/pci/controller/pci_n1sdp.c
View File

@ -113,8 +113,8 @@ n1sdp_init(struct generic_pcie_n1sdp_softc *sc)
shared_data = (struct pcie_discovery_data *)vaddr; shared_data = (struct pcie_discovery_data *)vaddr;
paddr_rc = (vm_offset_t)shared_data->rc_base_addr; paddr_rc = (vm_offset_t)shared_data->rc_base_addr;
error = bus_space_map(sc->acpi.base.bst, paddr_rc, PCI_CFG_SPACE_SIZE, error = bus_space_map(sc->acpi.base.res->r_bustag, paddr_rc,
0, &sc->n1_bsh); PCI_CFG_SPACE_SIZE, 0, &sc->n1_bsh);
if (error != 0) if (error != 0)
goto out_pmap; goto out_pmap;
@ -245,10 +245,10 @@ n1sdp_get_bus_space(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
return (EINVAL); return (EINVAL);
*bsh = sc->n1_bsh; *bsh = sc->n1_bsh;
} else { } else {
*bsh = sc->acpi.base.bsh; *bsh = rman_get_bushandle(sc->acpi.base.res);
} }
*bst = sc->acpi.base.bst; *bst = rman_get_bustag(sc->acpi.base.res);
*offset = PCIE_ADDR_OFFSET(bus - sc->acpi.base.bus_start, slot, func, *offset = PCIE_ADDR_OFFSET(bus - sc->acpi.base.bus_start, slot, func,
reg); reg);

24
sys/dev/pci/pci_host_generic.c
View File

@ -126,9 +126,6 @@ pci_host_generic_core_attach(device_t dev)
} }
rman_set_mapping(sc->res, &map); rman_set_mapping(sc->res, &map);
#endif #endif
sc->bst = rman_get_bustag(sc->res);
sc->bsh = rman_get_bushandle(sc->res);
} }
sc->has_pmem = false; sc->has_pmem = false;
@ -233,8 +230,6 @@ generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, int bytes) u_int func, u_int reg, int bytes)
{ {
struct generic_pcie_core_softc *sc; struct generic_pcie_core_softc *sc;
bus_space_handle_t h;
bus_space_tag_t t;
uint64_t offset; uint64_t offset;
uint32_t data; uint32_t data;
@ -248,18 +243,16 @@ generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
return (~0U); return (~0U);
offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
t = sc->bst;
h = sc->bsh;
switch (bytes) { switch (bytes) {
case 1: case 1:
data = bus_space_read_1(t, h, offset); data = bus_read_1(sc->res, offset);
break; break;
case 2: case 2:
data = le16toh(bus_space_read_2(t, h, offset)); data = le16toh(bus_read_2(sc->res, offset));
break; break;
case 4: case 4:
data = le32toh(bus_space_read_4(t, h, offset)); data = le32toh(bus_read_4(sc->res, offset));
break; break;
default: default:
return (~0U); return (~0U);
@ -273,8 +266,6 @@ generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
u_int func, u_int reg, uint32_t val, int bytes) u_int func, u_int reg, uint32_t val, int bytes)
{ {
struct generic_pcie_core_softc *sc; struct generic_pcie_core_softc *sc;
bus_space_handle_t h;
bus_space_tag_t t;
uint64_t offset; uint64_t offset;
sc = device_get_softc(dev); sc = device_get_softc(dev);
@ -286,18 +277,15 @@ generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
t = sc->bst;
h = sc->bsh;
switch (bytes) { switch (bytes) {
case 1: case 1:
bus_space_write_1(t, h, offset, val); bus_write_1(sc->res, offset, val);
break; break;
case 2: case 2:
bus_space_write_2(t, h, offset, htole16(val)); bus_write_2(sc->res, offset, htole16(val));
break; break;
case 4: case 4:
bus_space_write_4(t, h, offset, htole32(val)); bus_write_4(sc->res, offset, htole32(val));
break; break;
default: default:
return; return;

2
sys/dev/pci/pci_host_generic.h
View File

@ -80,8 +80,6 @@ struct generic_pcie_core_softc {
int bus_start; int bus_start;
int bus_end; int bus_end;
int ecam; int ecam;
bus_space_tag_t bst;
bus_space_handle_t bsh;
device_t dev; device_t dev;
bus_space_handle_t ioh; bus_space_handle_t ioh;
bus_dma_tag_t dmat; bus_dma_tag_t dmat;