- Document event numbers.
- Correct misspellings of two event names.
This commit is contained in:
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=183534
@ -121,75 +121,86 @@ qualifiers are specified, the default is to enable both.
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The event specifiers supported by Intel P6 PMCs are:
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.Bl -tag -width indent
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.It Li p6-baclears
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.Pq Event E6H
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Count the number of times a static branch prediction was made by the
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branch decoder because the BTB did not have a prediction.
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.It Li p6-br-bac-missp-exec
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.Pq Tn "Pentium M"
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.Pq Event 8AH , Tn "Pentium M"
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Count the number of branch instructions executed that where
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mispredicted at the Front End (BAC).
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.It Li p6-br-bogus
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.Pq Event E4H
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Count the number of bogus branches.
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.It Li p6-br-call-exec
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.Pq Tn "Pentium M"
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.Pq Event 92H , Tn "Pentium M"
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Count the number of call instructions executed.
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.It Li p6-br-call-missp-exec
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.Pq Tn "Pentium M"
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.Pq Event 93H , Tn "Pentium M"
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Count the number of call instructions executed that were mispredicted.
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.It Li p6-br-cnd-exec
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.Pq Tn "Pentium M"
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.Pq Event 8BH , Tn "Pentium M"
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Count the number of conditional branch instructions executed.
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.It Li p6-br-cnd-missp-exec
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.Pq Tn "Pentium M"
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.Pq Event 8CH , Tn "Pentium M"
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Count the number of conditional branch instructions executed that were
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mispredicted.
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.It Li p6-br-ind-call-exec
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.Pq Tn "Pentium M"
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.Pq Event 94H , Tn "Pentium M"
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Count the number of indirect call instructions executed.
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.It Li p6-br-ind-exec
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.Pq Tn "Pentium M"
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.Pq Event 8DH , Tn "Pentium M"
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Count the number of indirect branch instructions executed.
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.It Li p6-br-ind-missp-exec
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.Pq Tn "Pentium M"
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.Pq Event 8EH , Tn "Pentium M"
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Count the number of indirect branch instructions executed that were
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mispredicted.
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.It Li p6-br-inst-decoded
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.Pq Event E0H
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Count the number of branch instructions decoded.
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.It Li p6-br-inst-exec
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.Pq Tn "Pentium M"
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.Pq Event 88H , Tn "Pentium M"
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Count the number of branch instructions executed but necessarily retired.
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.It Li p6-br-inst-retired
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.Pq Event C4H
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Count the number of branch instructions retired.
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.It Li p6-br-miss-pred-retired
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.Pq Event C5H
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Count the number of mispredicted branch instructions retired.
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.It Li p6-br-miss-pred-taken-ret
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.Pq Event C9H
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Count the number of taken mispredicted branches retired.
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.It Li p6-br-missp-exec
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.Pq Tn "Pentium M"
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.Pq Event 89H , Tn "Pentium M"
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Count the number of branch instructions executed that were
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mispredicted at execution.
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.It Li p6-br-ret-bac-missp-exec
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.Pq Tn "Pentium M"
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.Pq Event 91H , Tn "Pentium M"
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Count the number of return instructions executed that were
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mispredicted at the Front End (BAC).
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.It Li p6-br-ret-exec
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.Pq Tn "Pentium M"
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.Pq Event 8FH , Tn "Pentium M"
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Count the number of return instructions executed.
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.It Li p6-br-ret-missp-exec
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.Pq Tn "Pentium M"
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.Pq Event 90H , Tn "Pentium M"
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Count the number of return instructions executed that were
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mispredicted at execution.
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.It Li p6-br-taken-retired
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.Pq Event C9H
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Count the number of taken branches retired.
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.It Li p6-btb-misses
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.Pq Event E2H
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Count the number of branches for which the BTB did not produce a
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prediction.
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.It Li p6-bus-bnr-drv
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.Pq Event 61H
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Count the number of bus clock cycles during which this processor is
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driving the BNR# pin.
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.It Li p6-bus-data-rcv
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.Pq Event 64H
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Count the number of bus clock cycles during which this processor is
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receiving data.
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.It Li p6-bus-drdy-clocks Op Li ,umask= Ns Ar qualifier
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.Pq Event 62H
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Count the number of clocks during which DRDY# is asserted.
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An additional qualifier may be specified, and comprises one of the
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following keywords:
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@ -203,12 +214,15 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-hit-drv
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.Pq Event 7AH
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Count the number of bus clock cycles during which this processor is
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driving the HIT# pin.
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.It Li p6-bus-hitm-drv
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.Pq Event 7BH
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Count the number of bus clock cycles during which this processor is
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driving the HITM# pin.
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.It Li p6-bus-lock-clocks Op Li ,umask= Ns Ar qualifier
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.Pq Event 63H
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Count the number of clocks during with LOCK# is asserted on the
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external system bus.
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An additional qualifier may be specified and comprises one of the following
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@ -223,10 +237,13 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-req-outstanding
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.Pq Event 60H
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Count the number of bus requests outstanding in any given cycle.
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.It Li p6-bus-snoop-stall
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.Pq Event 7EH
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Count the number of clock cycles during which the bus is snoop stalled.
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.It Li p6-bus-tran-any Op Li ,umask= Ns Ar qualifier
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.Pq Event 70H
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Count the number of completed bus transactions of any kind.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -240,6 +257,7 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-tran-brd Op Li ,umask= Ns Ar qualifier
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.Pq Event 65H
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Count the number of burst read transactions.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -253,6 +271,7 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-tran-burst Op Li ,umask= Ns Ar qualifier
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.Pq Event 6EH
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Count the number of completed burst transactions.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -266,6 +285,7 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-tran-def Op Li ,umask= Ns Ar qualifier
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.Pq Event 6DH
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Count the number of completed deferred transactions.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -279,6 +299,7 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-tran-ifetch Op Li ,umask= Ns Ar qualifier
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.Pq Event 68H
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Count the number of completed instruction fetch transactions.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -292,6 +313,7 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-tran-inval Op Li ,umask= Ns Ar qualifier
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.Pq Event 69H
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Count the number of completed invalidate transactions.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -305,6 +327,7 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-tran-mem Op Li ,umask= Ns Ar qualifier
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.Pq Event 6FH
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Count the number of completed memory transactions.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -318,6 +341,7 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-tran-pwr Op Li ,umask= Ns Ar qualifier
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.Pq Event 6AH
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Count the number of completed partial write transactions.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -331,6 +355,7 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-tran-rfo Op Li ,umask= Ns Ar qualifier
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.Pq Event 66H
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Count the number of completed read-for-ownership transactions.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -344,6 +369,7 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-trans-io Op Li ,umask= Ns Ar qualifier
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.Pq Event 6CH
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Count the number of completed I/O transactions.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -357,6 +383,7 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-trans-p Op Li ,umask= Ns Ar qualifier
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.Pq Event 6BH
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Count the number of completed partial transactions.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -370,6 +397,7 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-bus-trans-wb Op Li ,umask= Ns Ar qualifier
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.Pq Event 67H
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Count the number of completed write-back transactions.
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An additional qualifier may be specified and comprises one of the following
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keywords:
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@ -383,44 +411,54 @@ Count transactions generated by this processor.
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.Pp
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The default is to count operations generated by this processor.
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.It Li p6-cpu-clk-unhalted
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.Pq Event 79H
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Count the number of cycles during with the processor was not halted.
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.Pp
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.Pq Tn "Pentium M"
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Count the number of cycles during with the processor was not halted
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and not in a thermal trip.
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.It Li p6-cycles-div-busy
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.Pq Event 14H
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Count the number of cycles during which the divider is busy and cannot
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accept new divides.
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This event is only allocated on counter 0.
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.It Li p6-cycles-in-pending-and-masked
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.Pq Event C7H
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Count the number of processor cycles for which interrupts were
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disabled and interrupts were pending.
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.It Li p6-cycles-int-masked
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.Pq Event C6H
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Count the number of processor cycles for which interrupts were
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disabled.
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.It Li p6-data-mem-refs
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.Pq Event 43H
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Count all loads and all stores using any memory type, including
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internal retries.
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Each part of a split store is counted separately.
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.It Li p6-dcu-lines-in
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.Pq Event 45H
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Count the total lines allocated in the data cache unit.
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.It Li p6-dcu-m-lines-in
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.Pq Event 46H
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Count the number of M state lines allocated in the data cache unit.
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.It Li p6-dcu-m-lines-out
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.Pq Event 47H
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Count the number of M state lines evicted from the data cache unit.
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.It Li p6-dcu-miss-outstanding
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.Pq Event 48H
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Count the weighted number of cycles while a data cache unit miss is
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outstanding, incremented by the number of outstanding cache misses at
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any time.
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.It Li p6-div
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.Pq Event 13H
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Count the number of integer and floating-point divides including
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speculative divides.
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This event is only allocated on counter 1.
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.It Li p6-emon-esp-uops
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.Pq Tn "Pentium M"
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.Pq Event D7H , Tn "Pentium M"
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Count the total number of micro-ops.
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.It Li p6-emon-est-trans Op Li ,umask= Ns Ar qualifier
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.Pq Tn "Pentium M"
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.Pq Event 58H , Tn "Pentium M"
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Count the number of
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.Tn "Enhanced Intel SpeedStep"
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transitions.
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@ -436,7 +474,7 @@ Count only frequency transitions.
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.Pp
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The default is to count all transitions.
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.It Li p6-emon-fused-uops-ret Op Li ,umask= Ns Ar qualifier
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.Pq Tn "Pentium M"
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.Pq Event DAH , Tn "Pentium M"
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Count the number of retired fused micro-ops.
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An additional qualifier may be specified, and may be one of the
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following keywords:
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@ -452,7 +490,7 @@ Count only STD/STA micro-ops.
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.Pp
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The default is to count all fused micro-ops.
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.It Li p6-emon-kni-comp-inst-ret
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.Pq Tn "Pentium III"
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.Pq Event D9H , Tn "Pentium III"
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Count the number of SSE computational instructions retired.
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An additional qualifier may be specified, and comprises one of the
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following keywords:
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@ -466,7 +504,7 @@ Count scalar operations only.
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.Pp
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The default is to count packed and scalar operations.
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.It Li p6-emon-kni-inst-retired Op Li ,umask= Ns Ar qualifier
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.Pq Tn "Pentium III"
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.Pq Event D8H , Tn "Pentium III"
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Count the number of SSE instructions retired.
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An additional qualifier may be specified, and comprises one of the
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following keywords:
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@ -480,6 +518,7 @@ Count scalar operations only.
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.Pp
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The default is to count packed and scalar operations.
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.It Li p6-emon-kni-pref-dispatched Op Li ,umask= Ns Ar qualifier
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.Pq Event 07H
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.Pq Tn "Pentium III"
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Count the number of SSE prefetch or weakly ordered instructions
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dispatched (including speculative prefetches).
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@ -499,7 +538,7 @@ Count weakly ordered stores.
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.Pp
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The default is to count non-temporal prefetches.
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.It Li p6-emon-kni-pref-miss Op Li ,umask= Ns Ar qualifier
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.Pq Tn "Pentium III"
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.Pq Event 4BH , Tn "Pentium III"
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Count the number of prefetch or weakly ordered instructions that miss
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all caches.
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An additional qualifier may be specified, and comprises one of the
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@ -518,18 +557,18 @@ Count weakly ordered stores.
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.Pp
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The default is to count non-temporal prefetches.
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.It Li p6-emon-pref-rqsts-dn
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.Pq Tn "Pentium M"
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.Pq Event F8H , Tn "Pentium M"
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Count the number of downward prefetches issued.
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.It Li p6-emon-pref-rqsts-up
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.Pq Tn "Pentium M"
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.Pq Event F0H , Tn "Pentium M"
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Count the number of upward prefetches issued.
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.It Li p6-emon-simd-instr-retired
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.Pq Tn "Pentium M"
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.Pq Event CEH , Tn "Pentium M"
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Count the number of retired
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.Tn MMX
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instructions.
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.It Li p6-emon-sse-sse2-comp-inst-retired Op Li ,umask= Ns Ar qualifier
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.Pq Tn "Pentium M"
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.Pq Event D9H , Tn "Pentium M"
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Count the number of computational SSE instructions retired.
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An additional qualifier may be specified and can be one of the
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following keywords:
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@ -547,8 +586,7 @@ Count SSE2 scalar-double instructions.
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.Pp
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The default is to count SSE packed-single instructions.
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.It Li p6-emon-sse-sse2-inst-retired Op Li ,umask= Ns Ar qualifer
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.Pp
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.Pq Tn "Pentium M"
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.Pq Event D8H , Tn "Pentium M"
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Count the number of SSE instructions retired.
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An additional qualifier can be specified, and can be one of the
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following keywords:
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@ -566,28 +604,31 @@ Count SSE2 scalar-double instructions.
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.Pp
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The default is to count SSE packed-single instructions.
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.It Li p6-emon-synch-uops
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.Pq Tn "Pentium M"
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.Pq Event D3H , Tn "Pentium M"
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Count the number of sync micro-ops.
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.It Li p6-emon-thermal-trip
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.Pq Tn "Pentium M"
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.Pq Event 59H , Tn "Pentium M"
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Count the duration or occurrences of thermal trips.
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Use the
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.Dq Li edge
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qualifier to count occurrences of thermal trips.
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.It Li p6-emon-unfusion
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.Pq Tn "Pentium M"
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.Pq Event DBH , Tn "Pentium M"
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Count the number of unfusion events in the reorder buffer.
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.It Li p6-flops
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.Pq Event C1H
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Count the number of computational floating point operations retired.
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This event is only allocated on counter 0.
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.It Li p6-fp-assist
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.Pq Event 11H
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Count the number of floating point exceptions handled by microcode.
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This event is only allocated on counter 1.
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.It Li p6-fp-comps-ops-exe
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.Pq Event 10H
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Count the number of computation floating point operations executed.
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This event is only allocated on counter 0.
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.It Li p6-fp-mmx-trans Op Li ,umask= Ns Ar qualifier
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.Pq Tn "Pentium II" , Tn "Pentium III"
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.Pq Event CCH , Tn "Pentium II" , Tn "Pentium III"
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Count the number of transitions between MMX and floating-point
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instructions.
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An additional qualifier may be specified, and comprises one of the
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@ -602,30 +643,42 @@ Count transitions from floating-point instructions to MMX instructions.
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.Pp
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The default is to count MMX to floating-point transitions.
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.It Li p6-hw-int-rx
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.Pq Event C8H
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Count the number of hardware interrupts received.
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.It Li p6-ifu-fetch
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.It Li p6-ifu-ifetch
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.Pq Event 80H
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Count the number of instruction fetches, both cacheable and non-cacheable.
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.It Li p6-ifu-fetch-miss
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.It Li p6-ifu-ifetch-miss
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.Pq Event 81H
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Count the number of instruction fetch misses (i.e., those that produce
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memory accesses).
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.It Li p6-ifu-mem-stall
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.Pq Event 86H
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Count the number of cycles instruction fetch is stalled for any reason.
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.It Li p6-ild-stall
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.Pq Event 87H
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||||
Count the number of cycles the instruction length decoder is stalled.
|
||||
.It Li p6-inst-decoded
|
||||
.Pq Event D0H
|
||||
Count the number of instructions decoded.
|
||||
.It Li p6-inst-retired
|
||||
.Pq Event C0H
|
||||
Count the number of instructions retired.
|
||||
.It Li p6-itlb-miss
|
||||
.Pq Event 85H
|
||||
Count the number of instruction TLB misses.
|
||||
.It Li p6-l2-ads
|
||||
.Pq Event 21H
|
||||
Count the number of L2 address strobes.
|
||||
.It Li p6-l2-dbus-busy
|
||||
.Pq Event 22H
|
||||
Count the number of cycles during which the L2 cache data bus was busy.
|
||||
.It Li p6-l2-dbus-busy-rd
|
||||
.Pq Event 23H
|
||||
Count the number of cycles during which the L2 cache data bus was busy
|
||||
transferring read data from L2 to the processor.
|
||||
.It Li p6-l2-ifetch Op Li ,umask= Ns Ar qualifier
|
||||
.Pq Event 28H
|
||||
Count the number of L2 instruction fetches.
|
||||
An additional qualifier may be specified and comprises a list of the following
|
||||
keywords separated by
|
||||
@ -645,6 +698,7 @@ Count operations affecting S (shared) state lines.
|
||||
.Pp
|
||||
The default is to count operations affecting all (MESI) state lines.
|
||||
.It Li p6-l2-ld Op Li ,umask= Ns Ar qualifier
|
||||
.Pq Event 29H
|
||||
Count the number of L2 data loads.
|
||||
An additional qualifier may be specified and comprises a list of the following
|
||||
keywords separated by
|
||||
@ -681,6 +735,7 @@ non-hardware-prefetch operations on all (MESI) state lines.
|
||||
.Pq Errata
|
||||
This event is affected by processor errata E53.
|
||||
.It Li p6-l2-lines-in Op Li ,umask= Ns Ar qualifier
|
||||
.Pq Event 24H
|
||||
Count the number of L2 lines allocated.
|
||||
An additional qualifier may be specified and comprises a list of the following
|
||||
keywords separated by
|
||||
@ -717,6 +772,7 @@ non-hardware-prefetch operations on all (MESI) state lines.
|
||||
.Pq Errata
|
||||
This event is affected by processor errata E45.
|
||||
.It Li p6-l2-lines-out Op Li ,umask= Ns Ar qualifier
|
||||
.Pq Event 26H
|
||||
Count the number of L2 lines evicted.
|
||||
An additional qualifier may be specified and comprises a list of the following
|
||||
keywords separated by
|
||||
@ -753,8 +809,10 @@ non-hardware-prefetch operations on all (MESI) state lines.
|
||||
.Pq Errata
|
||||
This event is affected by processor errata E45.
|
||||
.It Li p6-l2-m-lines-inm
|
||||
.Pq Event 25H
|
||||
Count the number of modified lines allocated in L2 cache.
|
||||
.It Li p6-l2-m-lines-outm Op Li ,umask= Ns Ar qualifier
|
||||
.Pq Event 27H
|
||||
Count the number of L2 M-state lines evicted.
|
||||
.Pp
|
||||
.Pq Tn "Pentium M"
|
||||
@ -777,6 +835,7 @@ non-hardware-prefetch operations.
|
||||
.Pq Errata
|
||||
This event is affected by processor errata E53.
|
||||
.It Li p6-l2-rqsts Op Li ,umask= Ns Ar qualifier
|
||||
.Pq Event 2EH
|
||||
Count the total number of L2 requests.
|
||||
An additional qualifier may be specified and comprises a list of the following
|
||||
keywords separated by
|
||||
@ -796,6 +855,7 @@ Count operations affecting S (shared) state lines.
|
||||
.Pp
|
||||
The default is to count operations affecting all (MESI) state lines.
|
||||
.It Li p6-l2-st
|
||||
.Pq Event 2AH
|
||||
Count the number of L2 data stores.
|
||||
An additional qualifier may be specified and comprises a list of the following
|
||||
keywords separated by
|
||||
@ -815,22 +875,25 @@ Count operations affecting S (shared) state lines.
|
||||
.Pp
|
||||
The default is to count operations affecting all (MESI) state lines.
|
||||
.It Li p6-ld-blocks
|
||||
.Pq Event 03H
|
||||
Count the number of load operations delayed due to store buffer blocks.
|
||||
.It Li p6-misalign-mem-ref
|
||||
.Pq Event 05H
|
||||
Count the number of misaligned data memory references (crossing a 64
|
||||
bit boundary).
|
||||
.It Li p6-mmx-assist
|
||||
.Pq Tn "Pentium II" , Tn "Pentium III"
|
||||
.Pq Event CDH , Tn "Pentium II" , Tn "Pentium III"
|
||||
Count the number of MMX assists executed.
|
||||
.It Li p6-mmx-instr-exec
|
||||
.Pq Event B0H
|
||||
.Pq Tn Celeron , Tn "Pentium II"
|
||||
Count the number of MMX instructions executed, except MOVQ and MOVD
|
||||
stores from register to memory.
|
||||
.It Li p6-mmx-instr-ret
|
||||
.Pq Tn "Pentium II"
|
||||
.Pq Event CEH , Tn "Pentium II"
|
||||
Count the number of MMX instructions retired.
|
||||
.It Li p6-mmx-instr-type-exec Op Li ,umask= Ns Ar qualifier
|
||||
.Pq Tn "Pentium II" , Tn "Pentium III"
|
||||
.Pq Event B3H , Tn "Pentium II" , Tn "Pentium III"
|
||||
Count the number of MMX instructions executed.
|
||||
An additional qualifier may be specified and comprises a list of
|
||||
the following keywords separated by
|
||||
@ -854,26 +917,30 @@ Count MMX unpack operation instructions.
|
||||
.Pp
|
||||
The default is to count all operations.
|
||||
.It Li p6-mmx-sat-instr-exec
|
||||
.Pq Tn "Pentium II" , Tn "Pentium III"
|
||||
.Pq Event B1H , Tn "Pentium II" , Tn "Pentium III"
|
||||
Count the number of MMX saturating instructions executed.
|
||||
.It Li p6-mmx-uops-exec
|
||||
.Pq Tn "Pentium II" , Tn "Pentium III"
|
||||
.Pq Event B2H , Tn "Pentium II" , Tn "Pentium III"
|
||||
Count the number of MMX micro-ops executed.
|
||||
.It Li p6-mul
|
||||
.Pq Event 12H
|
||||
Count the number of integer and floating-point multiplies, including
|
||||
speculative multiplies.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p6-partial-rat-stalls
|
||||
.Pq Event D2H
|
||||
Count the number of cycles or events for partial stalls.
|
||||
.It Li p6-resource-stalls
|
||||
.Pq Event A2H
|
||||
Count the number of cycles there was a resource related stall of any kind.
|
||||
.It Li p6-ret-seg-renames
|
||||
.Pq Tn "Pentium II" , Tn "Pentium III"
|
||||
.Pq Event D6H , Tn "Pentium II" , Tn "Pentium III"
|
||||
Count the number of segment register rename events retired.
|
||||
.It Li p6-sb-drains
|
||||
.Pq Event 04H
|
||||
Count the number of cycles the store buffer is draining.
|
||||
.It Li p6-seg-reg-renames Op Li ,umask= Ns Ar qualifier
|
||||
.Pq Tn "Pentium II" , Tn "Pentium III"
|
||||
.Pq Event D5H , Tn "Pentium II" , Tn "Pentium III"
|
||||
Count the number of segment register renames.
|
||||
An additional qualifier may be specified, and comprises a list of the
|
||||
following keywords separated by
|
||||
@ -893,7 +960,7 @@ Count renames for segment register GS.
|
||||
.Pp
|
||||
The default is to count operations affecting all segment registers.
|
||||
.It Li p6-seg-rename-stalls
|
||||
.Pq Tn "Pentium II" , Tn "Pentium III"
|
||||
.Pq Event D4H , Tn "Pentium II" , Tn "Pentium III"
|
||||
Count the number of segment register renaming stalls.
|
||||
An additional qualifier may be specified, and comprises a list of the
|
||||
following keywords separated by
|
||||
@ -913,8 +980,10 @@ Count stalls for segment register GS.
|
||||
.Pp
|
||||
The default is to count operations affecting all the segment registers.
|
||||
.It Li p6-segment-reg-loads
|
||||
.Pq Event 06H
|
||||
Count the number of segment register loads.
|
||||
.It Li p6-uops-retired
|
||||
.Pq Event C2H
|
||||
Count the number of micro-ops retired.
|
||||
.El
|
||||
.Ss Event Name Aliases
|
||||
|
Loading…
Reference in New Issue
Block a user