mdoc improvements
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2020-12-20 02:59:44 +00:00
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@ -37,7 +37,9 @@ The special file
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.Pa /dev/devcfg
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can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
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.Pp
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On the first write to the character device at file offset 0, the devcfg driver
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On the first write to the character device at file offset 0, the
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.Nm
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driver
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asserts the top-level PL reset signals, disables the PS-PL level shifters,
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and clears the PL configuration.
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Write data is sent to the PCAP (processor configuration access port).
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@ -54,16 +56,18 @@ The file should not be confused with the .bit file output by the FPGA
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design tools.
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It is the binary form of the configuration bitstream.
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The Xilinx
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.Pa promgen
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.Ic promgen
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tool can do the conversion:
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.Bd -literal -offset indent
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promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin
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.Ed
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.Sh SYSCTL VARIABLES
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The devcfg driver provides the following
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The
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.Nm
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driver provides the following
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.Xr sysctl 8
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variables:
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.Bl -tag -width 12
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.Bl -tag -width 4n
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.It Va hw.fpga.pl_done
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.Pp
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This variable always reflects the status of the PL's DONE signal.
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@ -73,15 +77,19 @@ A 1 means the PL section has been properly programmed.
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This variable controls if the PS-PL level shifters are enabled after the
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PL section has been reconfigured.
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This variable is 1 by default but setting it to 0 allows the PL section to be
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programmed with configurations that don't interface to the PS section of the
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programmed with configurations that do not interface to the PS section of the
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part.
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Changing this value has no effect on the level shifters until the next device
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reconfiguration.
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.El
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.Sh FILES
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/dev/devcfg Character device for
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.Bl -tag -width 12n
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.It Pa /dev/devcfg
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Character device for the
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.Nm
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driver.
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.Sh AUTHORS
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Thomas Skibo
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.El
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.Sh SEE ALSO
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Zynq-7000 SoC Technical Reference Manual (Xilinx doc UG585)
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.Sh AUTHORS
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Thomas Skibo
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