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Next round of fixes to the ia64 code. This includes simulated clock and

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disk drivers along with a load of fixes to context switching, fork
handling and a load of other stuff I can't remember now. This takes us as
far as start_init() before it dies. I guess now I will have to finish off
the VM system and syscall handling :-).
This commit is contained in:
Doug Rabson 2000-10-04 17:53:03 +00:00
parent f94b5cf2c3
commit 8d9761debf
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=66633
43 changed files with 2303 additions and 427 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
sys/conf/files.ia64
View File

@ -49,6 +49,8 @@ ia64/ia64/pmap.c standard
ia64/ia64/procfs_machdep.c standard
ia64/ia64/support.s standard
ia64/ia64/ssc.c standard
ia64/ia64/sscclock.c standard
ia64/ia64/sscdisk.c standard
ia64/ia64/swtch.s standard
ia64/ia64/sys_machdep.c standard
ia64/ia64/synch_machdep.c standard
@ -92,13 +94,13 @@ libkern/ia64/htonl.S standard
libkern/ia64/htons.S standard
libkern/ia64/ntohl.S standard
libkern/ia64/ntohs.S standard
libkern/ia64/__divsi3.s standard
libkern/ia64/__modsi3.s standard
libkern/ia64/__udivsi3.s standard
libkern/ia64/__umodsi3.s standard
libkern/ia64/__divdi3.s standard
libkern/ia64/__moddi3.s standard
libkern/ia64/__udivdi3.s standard
libkern/ia64/__umoddi3.s standard
libkern/ia64/__divsi3.S standard
libkern/ia64/__modsi3.S standard
libkern/ia64/__udivsi3.S standard
libkern/ia64/__umodsi3.S standard
libkern/ia64/__divdi3.S standard
libkern/ia64/__moddi3.S standard
libkern/ia64/__udivdi3.S standard
libkern/ia64/__umoddi3.S standard
libkern/bcmp.c standard
libkern/ffs.c standard

4
sys/ia64/ia64/clock.c
View File

@ -158,10 +158,8 @@ cpu_initclocks()
{
u_int32_t freq;
#if 0
if (clockdev == NULL)
panic("cpu_initclocks: no clock attached");
#endif
/*
* We use cr.itc and cr.itm to implement a 1024hz clock.
@ -194,12 +192,10 @@ cpu_initclocks()
stathz = 128;
#if 0
/*
* Get the clock started.
*/
CLOCK_INIT(clockdev);
#endif
}
static u_int32_t

13
sys/ia64/ia64/exception.S
View File

@ -33,6 +33,7 @@
/*
* ar.k7 = curproc
* ar.k6 = ksp
* ar.k5 = globalp
*/
/*
@ -784,7 +785,7 @@ ia64_vhpt: .quad 0
* sp+16 trapframe pointer
*
*/
LEAF(exception_return, 0)
ENTRY(exception_return, 0)
rsm psr.ic|psr.dt // disable interrupt collection and vm
add r3=16,sp;
@ -792,6 +793,13 @@ LEAF(exception_return, 0)
srlz.d
dep r3=0,r3,61,3 // physical address
;;
extr.u r16=rIPSR,32,2 // extract ipsr.cpl
;;
cmp.eq p1,p2=r0,r16 // test for return to kernel mode
;;
(p1) add r16=SIZEOF_TRAPFRAME+16,sp // restore ar.k6 (kernel sp)
;;
(p1) mov ar.k6=r16
add r1=SIZEOF_TRAPFRAME-16,r3 // r1=&tf_f[FRAME_F15]
add r2=SIZEOF_TRAPFRAME-32,r3 // r2=&tf_f[FRAME_F14]
;;
@ -943,7 +951,7 @@ LEAF(exception_return, 0)
* Return:
* sp kernel stack pointer
*/
LEAF(exception_save_regs, 0)
ENTRY(exception_save_regs, 0)
rsm psr.dt // turn off data translations
;;
srlz.d // serialize
@ -1135,6 +1143,7 @@ LEAF(exception_save_regs, 0)
stf.spill [r1]=f15 //
;;
movl r1=__gp // kernel globals
mov r13=ar.k5 // processor globals
ssm psr.ic|psr.dt // enable interrupts & translation
;;
srlz.d // serialize

13
sys/ia64/ia64/exception.s
View File

@ -33,6 +33,7 @@
/*
* ar.k7 = curproc
* ar.k6 = ksp
* ar.k5 = globalp
*/
/*
@ -784,7 +785,7 @@ ia64_vhpt: .quad 0
* sp+16 trapframe pointer
*
*/
LEAF(exception_return, 0)
ENTRY(exception_return, 0)
rsm psr.ic|psr.dt // disable interrupt collection and vm
add r3=16,sp;
@ -792,6 +793,13 @@ LEAF(exception_return, 0)
srlz.d
dep r3=0,r3,61,3 // physical address
;;
extr.u r16=rIPSR,32,2 // extract ipsr.cpl
;;
cmp.eq p1,p2=r0,r16 // test for return to kernel mode
;;
(p1) add r16=SIZEOF_TRAPFRAME+16,sp // restore ar.k6 (kernel sp)
;;
(p1) mov ar.k6=r16
add r1=SIZEOF_TRAPFRAME-16,r3 // r1=&tf_f[FRAME_F15]
add r2=SIZEOF_TRAPFRAME-32,r3 // r2=&tf_f[FRAME_F14]
;;
@ -943,7 +951,7 @@ LEAF(exception_return, 0)
* Return:
* sp kernel stack pointer
*/
LEAF(exception_save_regs, 0)
ENTRY(exception_save_regs, 0)
rsm psr.dt // turn off data translations
;;
srlz.d // serialize
@ -1135,6 +1143,7 @@ LEAF(exception_save_regs, 0)
stf.spill [r1]=f15 //
;;
movl r1=__gp // kernel globals
mov r13=ar.k5 // processor globals
ssm psr.ic|psr.dt // enable interrupts & translation
;;
srlz.d // serialize

12
sys/ia64/ia64/locore.S
View File

@ -68,7 +68,7 @@
/*
* Not really a leaf but we can't return.
*/
LEAF(locorestart, 1)
ENTRY(locorestart, 1)
movl r8=ia64_vector_table // set up IVT early
movl r9=ia64_vhpt+(1<<8)+(15<<2)+1 // and VHPT
@ -122,7 +122,7 @@ LEAF(locorestart, 1)
* sp+16 pointer to sigframe
*/
LEAF(sigcode,0)
ENTRY(sigcode,0)
ld8 r8=[r17],8 // function address
;;
ld8 gp=[r17] // function's gp value
@ -172,7 +172,7 @@ LEAF(sigcode,0)
CALLSYS_NOERROR(sigreturn) // and call sigreturn() with it.
mov out0=ret0 // if that failed, get error code
CALLSYS_NOERROR(exit) // and call exit() with it.
XLEAF(esigcode)
XENTRY(esigcode)
END(sigcode)
.data
@ -189,7 +189,7 @@ XLEAF(esigcode)
* a0 'struct fpstate *' to save into
*/
LEAF(savefpstate, 1)
ENTRY(savefpstate, 1)
#if 0
LDGP(pv)
/* save all of the FP registers */
@ -246,7 +246,7 @@ LEAF(savefpstate, 1)
* a0 'struct fpstate *' to restore from
*/
LEAF(restorefpstate, 1)
ENTRY(restorefpstate, 1)
#if 0
LDGP(pv)
/*
@ -298,7 +298,7 @@ LEAF(restorefpstate, 1)
* When starting init, call this to configure the process for user
* mode. This will be inherited by other processes.
*/
LEAF_NOPROFILE(prepare_usermode, 0)
ENTRY_NOPROFILE(prepare_usermode, 0)
END(prepare_usermode)
.data

12
sys/ia64/ia64/locore.s
View File

@ -68,7 +68,7 @@
/*
* Not really a leaf but we can't return.
*/
LEAF(locorestart, 1)
ENTRY(locorestart, 1)
movl r8=ia64_vector_table // set up IVT early
movl r9=ia64_vhpt+(1<<8)+(15<<2)+1 // and VHPT
@ -122,7 +122,7 @@ LEAF(locorestart, 1)
* sp+16 pointer to sigframe
*/
LEAF(sigcode,0)
ENTRY(sigcode,0)
ld8 r8=[r17],8 // function address
;;
ld8 gp=[r17] // function's gp value
@ -172,7 +172,7 @@ LEAF(sigcode,0)
CALLSYS_NOERROR(sigreturn) // and call sigreturn() with it.
mov out0=ret0 // if that failed, get error code
CALLSYS_NOERROR(exit) // and call exit() with it.
XLEAF(esigcode)
XENTRY(esigcode)
END(sigcode)
.data
@ -189,7 +189,7 @@ XLEAF(esigcode)
* a0 'struct fpstate *' to save into
*/
LEAF(savefpstate, 1)
ENTRY(savefpstate, 1)
#if 0
LDGP(pv)
/* save all of the FP registers */
@ -246,7 +246,7 @@ LEAF(savefpstate, 1)
* a0 'struct fpstate *' to restore from
*/
LEAF(restorefpstate, 1)
ENTRY(restorefpstate, 1)
#if 0
LDGP(pv)
/*
@ -298,7 +298,7 @@ LEAF(restorefpstate, 1)
* When starting init, call this to configure the process for user
* mode. This will be inherited by other processes.
*/
LEAF_NOPROFILE(prepare_usermode, 0)
ENTRY_NOPROFILE(prepare_usermode, 0)
END(prepare_usermode)
.data

22
sys/ia64/ia64/machdep.c
View File

@ -581,6 +581,7 @@ ia64_init()
size_t sz = round_page(UPAGES * PAGE_SIZE);
globalp = (struct globaldata *) pmap_steal_memory(sz);
globaldata_init(globalp, 0, sz);
ia64_set_k5((u_int64_t) globalp);
PCPU_GET(next_asn) = 1; /* 0 used for proc0 pmap */
}
@ -1022,7 +1023,26 @@ cpu_halt(void)
void
setregs(struct proc *p, u_long entry, u_long stack, u_long ps_strings)
{
/* TODO setup trapframe to enter CSU code at the right place */
struct trapframe *frame;
frame = p->p_md.md_tf;
bzero(frame->tf_r, sizeof(frame->tf_r));
bzero(frame->tf_f, sizeof(frame->tf_f));
frame->tf_cr_iip = entry;
frame->tf_r[FRAME_SP] = stack;
frame->tf_r[FRAME_R14] = ps_strings;
/*
* Setup the new backing store and make sure the new image
* starts executing with an empty register stack frame.
*/
frame->tf_ar_bspstore = p->p_md.md_bspstore;
frame->tf_ar_bsp = p->p_md.md_bspstore;
frame->tf_cr_ifs = (1L<<63); /* ifm=0, v=1 */
p->p_md.md_flags &= ~MDP_FPUSED;
ia64_fpstate_drop(p);
}
int

8
sys/ia64/ia64/pal.S
View File

@ -31,10 +31,10 @@
BSS(ia64_pal_entry, 8)
/*
* struct ia64_pal_result ia64_call_pal_static(u_int64_t proc,
u_int64_t arg1, u_int64_t arg2, u_int64_t arg3)
* struct ia64_pal_result ia64_call_pal(u_int64_t proc,
* u_int64_t arg1, u_int64_t arg2, u_int64_t arg3)
*/
NESTED(ia64_call_pal_static, 4)
ENTRY(ia64_call_pal, 4)
.regstk 4,5,0,0
palret = loc0
@ -72,4 +72,4 @@ psrsave = loc4
srlz.d
br.ret.sptk rp
END(ia64_call_pal_static)
END(ia64_call_pal)

8
sys/ia64/ia64/pal.s
View File

@ -31,10 +31,10 @@
BSS(ia64_pal_entry, 8)
/*
* struct ia64_pal_result ia64_call_pal_static(u_int64_t proc,
u_int64_t arg1, u_int64_t arg2, u_int64_t arg3)
* struct ia64_pal_result ia64_call_pal(u_int64_t proc,
* u_int64_t arg1, u_int64_t arg2, u_int64_t arg3)
*/
NESTED(ia64_call_pal_static, 4)
ENTRY(ia64_call_pal, 4)
.regstk 4,5,0,0
palret = loc0
@ -72,4 +72,4 @@ psrsave = loc4
srlz.d
br.ret.sptk rp
END(ia64_call_pal_static)
END(ia64_call_pal)

2
sys/ia64/ia64/pmap.c
View File

@ -308,7 +308,7 @@ pmap_bootstrap()
* handlers. Here we just make sure that they have the largest
* possible page size to minimise TLB usage.
*/
#if 0
#if 1
ia64_set_rr(IA64_RR_BASE(6), (6 << 8) | (28 << 2));
ia64_set_rr(IA64_RR_BASE(7), (7 << 8) | (28 << 2));
#endif

1
sys/ia64/ia64/ssc.c
View File

@ -269,4 +269,3 @@ ssccnattach(void)
ssc_consdev.cn_dev = makedev(CDEV_MAJOR, 0);
make_dev(&ssc_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "ssccons");
}

127
sys/ia64/ia64/sscclock.c Normal file
View File

@ -0,0 +1,127 @@
/*-
* Copyright (c) 2000 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/malloc.h>
#include <machine/clockvar.h>
struct ssc_time {
u_int16_t year;
u_int8_t month;
u_int8_t day;
u_int8_t hour;
u_int8_t minute;
u_int8_t second;
u_int8_t pad1;
u_int32_t nanosecond;
int16_t timezone;
u_int8_t daylight;
u_int8_t pad2;
};
#define SSC_GET_RTC 65
static u_int64_t
ssc(u_int64_t in0, u_int64_t in1, u_int64_t in2, u_int64_t in3, int which)
{
register u_int64_t ret0 __asm("r8");
__asm __volatile("mov r15=%1\n\t"
"break 0x80001"
: "=r"(ret0)
: "r"(which), "r"(in0), "r"(in1), "r"(in2), "r"(in3));
return ret0;
}
static void
sscclock_init(device_t dev)
{
}
/*
* Get the time of day, based on the clock's value and/or the base value.
*/
static void
sscclock_get(device_t dev, time_t base, struct clocktime *ct)
{
#if 0
struct ssc_time time;
ssc(ia64_tpa((vm_offset_t) &time), 0, 0, 0, SSC_GET_RTC);
ct->sec = time.second;
ct->min = time.minute;
ct->hour = time.hour;
ct->dow = 0; /* XXX */
ct->day = time.day;
ct->mon = time.month;
ct->year = time.year;
#else
bzero(ct, sizeof(struct clocktime));
#endif
}
/*
* Reset the TODR based on the time value.
*/
static void
sscclock_set(device_t dev, struct clocktime *ct)
{
}
static int
sscclock_getsecs(device_t dev, int *secp)
{
return ETIMEDOUT;
}
static device_method_t sscclock_methods[] = {
/* clock interface */
DEVMETHOD(clock_init, sscclock_init),
DEVMETHOD(clock_get, sscclock_get),
DEVMETHOD(clock_set, sscclock_set),
DEVMETHOD(clock_getsecs, sscclock_getsecs),
{ 0, 0 }
};
DEFINE_CLASS(sscclock, sscclock_methods, sizeof(struct kobj));
static void
sscclock_create(void *arg)
{
device_t clock = (device_t)
kobj_create(&sscclock_class, M_TEMP, M_NOWAIT);
clockattach(clock);
}
SYSINIT(sscdev, SI_SUB_DRIVERS,SI_ORDER_MIDDLE, sscclock_create, NULL);

285
sys/ia64/ia64/sscdisk.c Normal file
View File

@ -0,0 +1,285 @@
/*
* ----------------------------------------------------------------------------
* "THE BEER-WARE LICENSE" (Revision 42):
* <phk@FreeBSD.ORG> wrote this file. As long as you retain this notice you
* can do whatever you want with this stuff. If we meet some day, and you think
* this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
* ----------------------------------------------------------------------------
*
* $FreeBSD$
*
*/
#include "opt_mfs.h" /* We have adopted some tasks from MFS */
#include "opt_md.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bio.h>
#include <sys/conf.h>
#include <sys/devicestat.h>
#include <sys/disk.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/sysctl.h>
#include <sys/linker.h>
#include <sys/queue.h>
#include <sys/lock.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
#include <vm/vm_extern.h>
#include <vm/vm_object.h>
#include <vm/vm_pager.h>
#define SSC_OPEN 50
#define SSC_CLOSE 51
#define SSC_READ 52
#define SSC_WRITE 53
#define SSC_GET_COMPLETION 54
#define SSC_WAIT_COMPLETION 55
struct disk_req {
unsigned long addr;
unsigned len;
};
struct disk_stat {
int fd;
unsigned count;
};
static u_int64_t
ssc(u_int64_t in0, u_int64_t in1, u_int64_t in2, u_int64_t in3, int which)
{
register u_int64_t ret0 __asm("r8");
__asm __volatile("mov r15=%1\n\t"
"break 0x80001"
: "=r"(ret0)
: "r"(which), "r"(in0), "r"(in1), "r"(in2), "r"(in3));
return ret0;
}
#ifndef SSC_NSECT
#define SSC_NSECT 196608
#endif
MALLOC_DEFINE(M_SSC, "SSC disk", "Memory Disk");
MALLOC_DEFINE(M_SSCSECT, "SSC sectors", "Memory Disk Sectors");
static int ssc_debug;
SYSCTL_INT(_debug, OID_AUTO, mddebug, CTLFLAG_RW, &ssc_debug, 0, "");
static int sscrootready;
#define CDEV_MAJOR 157
#define BDEV_MAJOR 157
static d_strategy_t sscstrategy;
static d_open_t sscopen;
static d_ioctl_t sscioctl;
static struct cdevsw ssc_cdevsw = {
/* open */ sscopen,
/* close */ nullclose,
/* read */ physread,
/* write */ physwrite,
/* ioctl */ sscioctl,
/* poll */ nopoll,
/* mmap */ nommap,
/* strategy */ sscstrategy,
/* name */ "ssc",
/* maj */ CDEV_MAJOR,
/* dump */ nodump,
/* psize */ nopsize,
/* flags */ D_DISK | D_CANFREE,
/* bmaj */ BDEV_MAJOR
};
static struct cdevsw sscdisk_cdevsw;
static LIST_HEAD(, ssc_s) ssc_softc_list = LIST_HEAD_INITIALIZER(&ssc_softc_list);
struct ssc_s {
int unit;
LIST_ENTRY(ssc_s) list;
struct devstat stats;
struct bio_queue_head bio_queue;
struct disk disk;
dev_t dev;
int busy;
unsigned nsect;
int fd;
};
static int sscunits;
static int
sscopen(dev_t dev, int flag, int fmt, struct proc *p)
{
struct ssc_s *sc;
struct disklabel *dl;
if (ssc_debug)
printf("sscopen(%s %x %x %p)\n",
devtoname(dev), flag, fmt, p);
sc = dev->si_drv1;
dl = &sc->disk.d_label;
bzero(dl, sizeof(*dl));
dl->d_secsize = DEV_BSIZE;
dl->d_nsectors = 1024;
dl->d_ntracks = 1;
dl->d_secpercyl = dl->d_nsectors * dl->d_ntracks;
dl->d_secperunit = sc->nsect;
dl->d_ncylinders = dl->d_secperunit / dl->d_secpercyl;
return (0);
}
static int
sscioctl(dev_t dev, u_long cmd, caddr_t addr, int flags, struct proc *p)
{
if (ssc_debug)
printf("sscioctl(%s %lx %p %x %p)\n",
devtoname(dev), cmd, addr, flags, p);
return (ENOIOCTL);
}
static void
sscstrategy(struct bio *bp)
{
struct ssc_s *sc;
int s;
devstat_trans_flags dop;
unsigned sscop = 0;
struct disk_req req;
struct disk_stat stat;
if (ssc_debug > 1)
printf("sscstrategy(%p) %s %x, %d, %ld, %p)\n",
bp, devtoname(bp->bio_dev), bp->bio_flags, bp->bio_blkno,
bp->bio_bcount / DEV_BSIZE, bp->bio_data);
sc = bp->bio_dev->si_drv1;
s = splbio();
bioqdisksort(&sc->bio_queue, bp);
if (sc->busy) {
splx(s);
return;
}
sc->busy++;
while (1) {
bp = bioq_first(&sc->bio_queue);
if (bp)
bioq_remove(&sc->bio_queue, bp);
splx(s);
if (!bp)
break;
devstat_start_transaction(&sc->stats);
if (bp->bio_cmd == BIO_DELETE) {
dop = DEVSTAT_NO_DATA;
} else if (bp->bio_cmd == BIO_READ) {
dop = DEVSTAT_READ;
sscop = SSC_READ;
} else {
dop = DEVSTAT_WRITE;
sscop = SSC_WRITE;
}
req.len = bp->bio_bcount;
req.addr = (long) vtophys(bp->bio_data);
ssc(sc->fd, 1, ia64_tpa((long) &req),
(bp->bio_pblkno << DEV_BSHIFT), sscop);
stat.fd = sc->fd;
ssc(ia64_tpa((long)&stat), 0, 0, 0, SSC_WAIT_COMPLETION);
bp->bio_resid = 0;
devstat_end_transaction_bio(&sc->stats, bp);
biodone(bp);
s = splbio();
}
sc->busy = 0;
return;
}
static struct ssc_s *
ssccreate(int unit)
{
struct ssc_s *sc;
if (unit == -1)
unit = sscunits++;
/* Make sure this unit isn't already in action */
LIST_FOREACH(sc, &ssc_softc_list, list) {
if (sc->unit == unit)
return (NULL);
}
MALLOC(sc, struct ssc_s *,sizeof(*sc), M_SSC, M_WAITOK);
bzero(sc, sizeof(*sc));
LIST_INSERT_HEAD(&ssc_softc_list, sc, list);
sc->unit = unit;
bioq_init(&sc->bio_queue);
devstat_add_entry(&sc->stats, "ssc", sc->unit, DEV_BSIZE,
DEVSTAT_NO_ORDERED_TAGS,
DEVSTAT_TYPE_DIRECT | DEVSTAT_TYPE_IF_OTHER,
DEVSTAT_PRIORITY_OTHER);
sc->dev = disk_create(sc->unit, &sc->disk,
DSO_ONESLICE|DSO_NOLABELS,
&ssc_cdevsw, &sscdisk_cdevsw);
sc->dev->si_drv1 = sc;
sc->nsect = SSC_NSECT;
sc->fd = ssc(ia64_tpa((u_int64_t) "/vol/v7/dfr/moo.fs"),
1, 0, 0, SSC_OPEN);
if (sc->unit == 0)
sscrootready = 1;
return (sc);
}
static void
ssc_clone (void *arg, char *name, int namelen, dev_t *dev)
{
int i, u;
if (*dev != NODEV)
return;
i = dev_stdclone(name, NULL, "ssc", &u);
if (i == 0)
return;
/* XXX: should check that next char is [\0sa-h] */
/*
* Now we cheat: We just create the disk, but don't match.
* Since we run before it, subr_disk.c::disk_clone() will
* find our disk and match the sought for device.
*/
ssccreate(u);
return;
}
static void
ssc_drvinit(void *unused)
{
ssccreate(-1);
}
SYSINIT(sscdev,SI_SUB_DRIVERS,SI_ORDER_MIDDLE+CDEV_MAJOR, ssc_drvinit,NULL)
static void
ssc_takeroot(void *junk)
{
if (sscrootready)
rootdevnames[0] = "ufs:/dev/ssc0";
}
SYSINIT(ssc_root, SI_SUB_MOUNT_ROOT, SI_ORDER_FIRST, ssc_takeroot, NULL);

215
sys/ia64/ia64/support.S
View File

@ -63,123 +63,132 @@
* fu{byte,word} : fetch a byte (word) from user memory
*/
LEAF(suword, 1)
#if 0
LDGP(pv)
ENTRY(suword, 2)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
movl r14=VM_MAXUSER_ADDRESS;; // make sure address is ok
cmp.geu p6,p0=in0,r14
(p6) br.dpnt.few fusufault
lda t0, fusufault /* trap faults */
ldq t2, curproc
ldq t2, P_ADDR(t2)
stq t0, U_PCB_ONFAULT(t2)
movl r14=fusufault // set up fault handler.
add r15=GD_CURPROC,r13 // find curproc
;;
ld8 r15=[r15]
;;
add r15=P_ADDR,r15 // find pcb
;;
ld8 r15=[r15]
;;
add r15=U_PCB_ONFAULT,r15
;;
st8 [r15]=r14
;;
st8.rel [in0]=in1 // try the store
;;
st8 [r15]=r0 // clean up
stq a1, 0(a0) /* try the store */
mov ret0=r0
br.ret.sptk.few rp
stq zero, U_PCB_ONFAULT(t2) /* clean up */
mov zero, v0
RET
#endif
END(suword)
LEAF(subyte, 1)
#if 0
LDGP(pv)
ENTRY(subyte, 2)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
movl r14=VM_MAXUSER_ADDRESS;; // make sure address is ok
cmp.geu p6,p0=in0,r14
(p6) br.dpnt.few fusufault
lda t0, fusufault /* trap faults */
ldq t2, curproc
ldq t2, P_ADDR(t2)
stq t0, U_PCB_ONFAULT(t2)
movl r14=fusufault // set up fault handler.
add r15=GD_CURPROC,r13 // find curproc
;;
ld8 r15=[r15]
;;
add r15=P_ADDR,r15 // find pcb
;;
ld8 r15=[r15]
;;
add r15=U_PCB_ONFAULT,r15
;;
st8 [r15]=r14
;;
st1.rel [in0]=in1 // try the store
;;
st8 [r15]=r0 // clean up
zap a1, 0xfe, a1 /* mask off the byte to store */
insbl a1, a0, a1 /* shift it to the right place */
ldq_u t0, 0(a0) /* read the qword to store it in */
mskbl t0, a0, t0 /* make a place for our byte */
or a1, t0, a1 /* move it in */
stq_u a1, 0(a0) /* and put the byte back */
mov ret0=r0
br.ret.sptk.few rp
stq zero, U_PCB_ONFAULT(t2) /* clean up */
mov zero, v0
RET
#endif
END(subyte)
LEAF(fuword, 1)
#if 0
LDGP(pv)
ENTRY(fuword, 1)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
movl r14=VM_MAXUSER_ADDRESS;; // make sure address is ok
cmp.geu p6,p0=in0,r14
(p6) br.dpnt.few fusufault
lda t0, fusufault /* trap faults */
ldq t2, curproc
ldq t2, P_ADDR(t2)
stq t0, U_PCB_ONFAULT(t2)
movl r14=fusufault // set up fault handler.
add r15=GD_CURPROC,r13 // find curproc
;;
ld8 r15=[r15]
;;
add r15=P_ADDR,r15 // find pcb
;;
ld8 r15=[r15]
;;
add r15=U_PCB_ONFAULT,r15
;;
st8 [r15]=r14
;;
ld8.acq ret0=[in0] // try the fetch
;;
st8 [r15]=r0 // clean up
ldq v0, 0(a0) /* try the fetch */
br.ret.sptk.few rp
stq zero, U_PCB_ONFAULT(t2) /* clean up */
RET
#endif
END(fuword)
LEAF(fubyte, 1)
#if 0
LDGP(pv)
ENTRY(fubyte, 1)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
movl r14=VM_MAXUSER_ADDRESS;; // make sure address is ok
cmp.geu p6,p0=in0,r14
(p6) br.dpnt.few fusufault
lda t0, fusufault /* trap faults */
ldq t2, curproc
ldq t2, P_ADDR(t2)
stq t0, U_PCB_ONFAULT(t2)
movl r14=fusufault // set up fault handler.
add r15=GD_CURPROC,r13 // find curproc
;;
ld8 r15=[r15]
;;
add r15=P_ADDR,r15 // find pcb
;;
ld8 r15=[r15]
;;
add r15=U_PCB_ONFAULT,r15
;;
st8 [r15]=r14
;;
ld1.acq ret0=[in0] // try the fetch
;;
st8 [r15]=r0 // clean up
ldq_u v0, 0(a0) /* get the word containing our byte */
extbl v0, a0, v0 /* extract the byte */
br.ret.sptk.few rp
stq zero, U_PCB_ONFAULT(t2) /* clean up */
RET
#endif
END(fubyte)
LEAF(suibyte, 2)
#if 0
ldiq v0, -1
RET
#endif
END(suibyte)
ENTRY(suibyte, 2)
mov ret0=-1
br.ret.sptk.few rp
END(suibyte)
LEAF(fusufault, 0)
#if 0
ldq t0, curproc
ldq t0, P_ADDR(t0)
stq zero, U_PCB_ONFAULT(t0)
ldiq v0, -1
RET
#endif
ENTRY(fusufault, 0)
st8 [r15]=r0 ;; // r15 points at onfault
mov ret0=r0
br.ret.sptk.few rp
END(fusufault)
LEAF(fswintrberr, 0)
XLEAF(fuswintr) /* XXX what is a 'word'? */
XLEAF(suswintr) /* XXX what is a 'word'? */
#if 0
LDGP(pv)
ldiq v0, -1
RET
#endif
ENTRY(fswintrberr, 0)
XENTRY(fuswintr) /* XXX what is a 'word'? */
XENTRY(suswintr) /* XXX what is a 'word'? */
mov ret0=-1
br.ret.sptk.few rp
END(fswintrberr)
/**************************************************************************/
@ -190,7 +199,7 @@ END(fswintrberr)
*
* int copystr(char *from, char *to, size_t len, size_t *lenp);
*/
LEAF(copystr, 4)
ENTRY(copystr, 4)
mov r14=in2 // r14 = i = len
cmp.eq p6,p0=r0,in2
(p6) br.cond.spnt.few 2f // if (len == 0), bail out
@ -223,13 +232,13 @@ LEAF(copystr, 4)
END(copystr)
NESTED(copyinstr, 4)
ENTRY(copyinstr, 4)
alloc loc0=ar.pfs,4,3,4,0
mov loc1=rp
movl loc2=VM_MAXUSER_ADDRESS // make sure that src addr
;;
cmp.ltu p6,p0=in0,loc2 // is in user space.
cmp.geu p6,p0=in0,loc2 // is in user space.
;;
(p6) br.cond.spnt.few copyerr // if it's not, error out.
movl r14=copyerr // set up fault handler.
@ -257,13 +266,13 @@ NESTED(copyinstr, 4)
END(copyinstr)
NESTED(copyoutstr, 4)
ENTRY(copyoutstr, 4)
alloc loc0=ar.pfs,4,3,4,0
mov loc1=rp
movl loc2=VM_MAXUSER_ADDRESS // make sure that dest addr
;;
cmp.ltu p6,p0=in1,loc2 // is in user space.
cmp.geu p6,p0=in1,loc2 // is in user space.
;;
(p6) br.cond.spnt.few copyerr // if it's not, error out.
movl r14=copyerr // set up fault handler.
@ -294,8 +303,8 @@ END(copyoutstr)
/*
* Not the fastest bcopy in the world.
*/
LEAF(bcopy, 3)
XLEAF(ovbcopy)
ENTRY(bcopy, 3)
XENTRY(ovbcopy)
mov ret0=r0 // return zero for copy{in,out}
;;
@ -361,7 +370,7 @@ XLEAF(ovbcopy)
END(bcopy)
LEAF(memcpy,3)
ENTRY(memcpy,3)
mov r14=in0 ;;
mov in0=in1 ;;
@ -370,7 +379,7 @@ LEAF(memcpy,3)
END(memcpy)
NESTED(copyin, 3)
ENTRY(copyin, 3)
alloc loc0=ar.pfs,3,3,3,0
mov loc1=rp
@ -404,7 +413,7 @@ NESTED(copyin, 3)
END(copyin)
NESTED(copyout, 3)
ENTRY(copyout, 3)
alloc loc0=ar.pfs,3,3,3,0
mov loc1=rp
@ -438,7 +447,7 @@ NESTED(copyout, 3)
END(copyout)
LEAF(copyerr, 0)
ENTRY(copyerr, 0)
add r14=GD_CURPROC,r13 ;; // find curproc
ld8 r14=[r14] ;;
@ -464,7 +473,7 @@ END(copyerr)
*/
LEAF(setjmp, 1)
ENTRY(setjmp, 1)
#if 0
LDGP(pv)
@ -486,7 +495,7 @@ LEAF(setjmp, 1)
#endif
END(setjmp)
LEAF(longjmp, 1)
ENTRY(longjmp, 1)
#if 0
LDGP(pv)

215
sys/ia64/ia64/support.s
View File

@ -63,123 +63,132 @@
* fu{byte,word} : fetch a byte (word) from user memory
*/
LEAF(suword, 1)
#if 0
LDGP(pv)
ENTRY(suword, 2)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
movl r14=VM_MAXUSER_ADDRESS;; // make sure address is ok
cmp.geu p6,p0=in0,r14
(p6) br.dpnt.few fusufault
lda t0, fusufault /* trap faults */
ldq t2, curproc
ldq t2, P_ADDR(t2)
stq t0, U_PCB_ONFAULT(t2)
movl r14=fusufault // set up fault handler.
add r15=GD_CURPROC,r13 // find curproc
;;
ld8 r15=[r15]
;;
add r15=P_ADDR,r15 // find pcb
;;
ld8 r15=[r15]
;;
add r15=U_PCB_ONFAULT,r15
;;
st8 [r15]=r14
;;
st8.rel [in0]=in1 // try the store
;;
st8 [r15]=r0 // clean up
stq a1, 0(a0) /* try the store */
mov ret0=r0
br.ret.sptk.few rp
stq zero, U_PCB_ONFAULT(t2) /* clean up */
mov zero, v0
RET
#endif
END(suword)
LEAF(subyte, 1)
#if 0
LDGP(pv)
ENTRY(subyte, 2)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
movl r14=VM_MAXUSER_ADDRESS;; // make sure address is ok
cmp.geu p6,p0=in0,r14
(p6) br.dpnt.few fusufault
lda t0, fusufault /* trap faults */
ldq t2, curproc
ldq t2, P_ADDR(t2)
stq t0, U_PCB_ONFAULT(t2)
movl r14=fusufault // set up fault handler.
add r15=GD_CURPROC,r13 // find curproc
;;
ld8 r15=[r15]
;;
add r15=P_ADDR,r15 // find pcb
;;
ld8 r15=[r15]
;;
add r15=U_PCB_ONFAULT,r15
;;
st8 [r15]=r14
;;
st1.rel [in0]=in1 // try the store
;;
st8 [r15]=r0 // clean up
zap a1, 0xfe, a1 /* mask off the byte to store */
insbl a1, a0, a1 /* shift it to the right place */
ldq_u t0, 0(a0) /* read the qword to store it in */
mskbl t0, a0, t0 /* make a place for our byte */
or a1, t0, a1 /* move it in */
stq_u a1, 0(a0) /* and put the byte back */
mov ret0=r0
br.ret.sptk.few rp
stq zero, U_PCB_ONFAULT(t2) /* clean up */
mov zero, v0
RET
#endif
END(subyte)
LEAF(fuword, 1)
#if 0
LDGP(pv)
ENTRY(fuword, 1)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
movl r14=VM_MAXUSER_ADDRESS;; // make sure address is ok
cmp.geu p6,p0=in0,r14
(p6) br.dpnt.few fusufault
lda t0, fusufault /* trap faults */
ldq t2, curproc
ldq t2, P_ADDR(t2)
stq t0, U_PCB_ONFAULT(t2)
movl r14=fusufault // set up fault handler.
add r15=GD_CURPROC,r13 // find curproc
;;
ld8 r15=[r15]
;;
add r15=P_ADDR,r15 // find pcb
;;
ld8 r15=[r15]
;;
add r15=U_PCB_ONFAULT,r15
;;
st8 [r15]=r14
;;
ld8.acq ret0=[in0] // try the fetch
;;
st8 [r15]=r0 // clean up
ldq v0, 0(a0) /* try the fetch */
br.ret.sptk.few rp
stq zero, U_PCB_ONFAULT(t2) /* clean up */
RET
#endif
END(fuword)
LEAF(fubyte, 1)
#if 0
LDGP(pv)
ENTRY(fubyte, 1)
ldiq t0, VM_MAXUSER_ADDRESS /* verify address validity */
cmpult a0, t0, t1
beq t1, fusufault
movl r14=VM_MAXUSER_ADDRESS;; // make sure address is ok
cmp.geu p6,p0=in0,r14
(p6) br.dpnt.few fusufault
lda t0, fusufault /* trap faults */
ldq t2, curproc
ldq t2, P_ADDR(t2)
stq t0, U_PCB_ONFAULT(t2)
movl r14=fusufault // set up fault handler.
add r15=GD_CURPROC,r13 // find curproc
;;
ld8 r15=[r15]
;;
add r15=P_ADDR,r15 // find pcb
;;
ld8 r15=[r15]
;;
add r15=U_PCB_ONFAULT,r15
;;
st8 [r15]=r14
;;
ld1.acq ret0=[in0] // try the fetch
;;
st8 [r15]=r0 // clean up
ldq_u v0, 0(a0) /* get the word containing our byte */
extbl v0, a0, v0 /* extract the byte */
br.ret.sptk.few rp
stq zero, U_PCB_ONFAULT(t2) /* clean up */
RET
#endif
END(fubyte)
LEAF(suibyte, 2)
#if 0
ldiq v0, -1
RET
#endif
END(suibyte)
ENTRY(suibyte, 2)
mov ret0=-1
br.ret.sptk.few rp
END(suibyte)
LEAF(fusufault, 0)
#if 0
ldq t0, curproc
ldq t0, P_ADDR(t0)
stq zero, U_PCB_ONFAULT(t0)
ldiq v0, -1
RET
#endif
ENTRY(fusufault, 0)
st8 [r15]=r0 ;; // r15 points at onfault
mov ret0=r0
br.ret.sptk.few rp
END(fusufault)
LEAF(fswintrberr, 0)
XLEAF(fuswintr) /* XXX what is a 'word'? */
XLEAF(suswintr) /* XXX what is a 'word'? */
#if 0
LDGP(pv)
ldiq v0, -1
RET
#endif
ENTRY(fswintrberr, 0)
XENTRY(fuswintr) /* XXX what is a 'word'? */
XENTRY(suswintr) /* XXX what is a 'word'? */
mov ret0=-1
br.ret.sptk.few rp
END(fswintrberr)
/**************************************************************************/
@ -190,7 +199,7 @@ END(fswintrberr)
*
* int copystr(char *from, char *to, size_t len, size_t *lenp);
*/
LEAF(copystr, 4)
ENTRY(copystr, 4)
mov r14=in2 // r14 = i = len
cmp.eq p6,p0=r0,in2
(p6) br.cond.spnt.few 2f // if (len == 0), bail out
@ -223,13 +232,13 @@ LEAF(copystr, 4)
END(copystr)
NESTED(copyinstr, 4)
ENTRY(copyinstr, 4)
alloc loc0=ar.pfs,4,3,4,0
mov loc1=rp
movl loc2=VM_MAXUSER_ADDRESS // make sure that src addr
;;
cmp.ltu p6,p0=in0,loc2 // is in user space.
cmp.geu p6,p0=in0,loc2 // is in user space.
;;
(p6) br.cond.spnt.few copyerr // if it's not, error out.
movl r14=copyerr // set up fault handler.
@ -257,13 +266,13 @@ NESTED(copyinstr, 4)
END(copyinstr)
NESTED(copyoutstr, 4)
ENTRY(copyoutstr, 4)
alloc loc0=ar.pfs,4,3,4,0
mov loc1=rp
movl loc2=VM_MAXUSER_ADDRESS // make sure that dest addr
;;
cmp.ltu p6,p0=in1,loc2 // is in user space.
cmp.geu p6,p0=in1,loc2 // is in user space.
;;
(p6) br.cond.spnt.few copyerr // if it's not, error out.
movl r14=copyerr // set up fault handler.
@ -294,8 +303,8 @@ END(copyoutstr)
/*
* Not the fastest bcopy in the world.
*/
LEAF(bcopy, 3)
XLEAF(ovbcopy)
ENTRY(bcopy, 3)
XENTRY(ovbcopy)
mov ret0=r0 // return zero for copy{in,out}
;;
@ -361,7 +370,7 @@ XLEAF(ovbcopy)
END(bcopy)
LEAF(memcpy,3)
ENTRY(memcpy,3)
mov r14=in0 ;;
mov in0=in1 ;;
@ -370,7 +379,7 @@ LEAF(memcpy,3)
END(memcpy)
NESTED(copyin, 3)
ENTRY(copyin, 3)
alloc loc0=ar.pfs,3,3,3,0
mov loc1=rp
@ -404,7 +413,7 @@ NESTED(copyin, 3)
END(copyin)
NESTED(copyout, 3)
ENTRY(copyout, 3)
alloc loc0=ar.pfs,3,3,3,0
mov loc1=rp
@ -438,7 +447,7 @@ NESTED(copyout, 3)
END(copyout)
LEAF(copyerr, 0)
ENTRY(copyerr, 0)
add r14=GD_CURPROC,r13 ;; // find curproc
ld8 r14=[r14] ;;
@ -464,7 +473,7 @@ END(copyerr)
*/
LEAF(setjmp, 1)
ENTRY(setjmp, 1)
#if 0
LDGP(pv)
@ -486,7 +495,7 @@ LEAF(setjmp, 1)
#endif
END(setjmp)
LEAF(longjmp, 1)
ENTRY(longjmp, 1)
#if 0
LDGP(pv)

14
sys/ia64/ia64/swtch.s
View File

@ -42,7 +42,7 @@
* in the PCB is set to the return address from savectx().)
*/
LEAF(savectx, 1)
ENTRY(savectx, 1)
flushrs // push out caller's dirty regs
mov r3=ar.unat // caller's value for ar.unat
;;
@ -103,7 +103,7 @@ LEAF(savectx, 1)
* return a second time with a non-zero return value.
*/
LEAF(restorectx, 1)
ENTRY(restorectx, 1)
add r3=U_PCB_UNAT,in0 // point at NaT for r4..r7
mov ar.rsc=0 ;; // switch off the RSE
ld8 r16=[r3] // load NaT for r4..r7
@ -164,10 +164,16 @@ LEAF(restorectx, 1)
* address specified by the r5 register and with one argument, taken
* from r6.
*/
LEAF(switch_trampoline, 0)
ENTRY(switch_trampoline, 0)
MTX_EXIT(sched_lock, r14, r15)
alloc r16=ar.pfs,0,0,1,0
// Clear sched_lock.mtx_recurse (normally restored in cpu_switch).
addl r15=@ltoff(sched_lock),gp ;;
ld8 r15=[r15] ;;
add r15=MTX_RECURSE,r15 ;;
st4 [r15]=r0
alloc r14=ar.pfs,0,0,1,0
mov b7=r4
mov b0=r5
mov out0=r6

6
sys/ia64/ia64/synch_machdep.c
View File

@ -553,10 +553,14 @@ cpu_switch()
{
struct proc *p = curproc;
if (savectx(&p->p_addr->u_pcb))
if (savectx(&p->p_addr->u_pcb)) {
sched_lock.mtx_lock = CURTHD;
sched_lock.mtx_recurse = p->p_addr->u_pcb.pcb_schednest;
return;
}
p = chooseproc();
curproc = p;
ia64_set_k7((u_int64_t) curproc);
restorectx(&p->p_addr->u_pcb);
}

36
sys/ia64/ia64/trap.c
View File

@ -239,13 +239,6 @@ trap(int vector, struct trapframe *framep)
u_quad_t sticks;
int user;
#if 0
/*
* Find our per-cpu globals.
*/
globalp = (struct globaldata *) alpha_pal_rdval(); /* XXx */
#endif
cnt.v_trap++;
p = curproc;
ucode = 0;
@ -395,7 +388,7 @@ trap(int vector, struct trapframe *framep)
if (map != kernel_map) {
/*
* Keep swapout from messing with us
* during thiscritical time.
* during this critical time.
*/
++p->p_lock;
@ -509,7 +502,6 @@ syscall(code, framep)
u_int64_t code;
struct trapframe *framep;
{
#if 0
struct sysent *callp;
struct proc *p;
int error = 0;
@ -518,12 +510,6 @@ syscall(code, framep)
u_int64_t args[10]; /* XXX */
u_int hidden = 0, nargs;
/*
* Find our per-cpu globals.
*/
#if 0
globalp = (struct globaldata *) alpha_pal_rdval();
#endif
mtx_enter(&Giant, MTX_DEF);
#if notdef /* can't happen, ever. */
@ -538,9 +524,10 @@ syscall(code, framep)
sticks = p->p_sticks;
#ifdef DIAGNOSTIC
alpha_fpstate_check(p);
ia64_fpstate_check(p);
#endif
#if 0
if (p->p_sysent->sv_prepsyscall) {
/* (*p->p_sysent->sv_prepsyscall)(framep, args, &code, &params); */
panic("prepsyscall");
@ -588,6 +575,8 @@ syscall(code, framep)
case 0:
break;
}
#endif
#ifdef KTRACE
if (KTRPOINT(p, KTR_SYSCALL))
ktrsyscall(p->p_tracep, code, (callp->sy_narg & SYF_ARGMASK), args + hidden);
@ -604,12 +593,12 @@ syscall(code, framep)
switch (error) {
case 0:
framep->tf_regs[FRAME_V0] = p->p_retval[0];
framep->tf_regs[FRAME_A4] = p->p_retval[1];
framep->tf_regs[FRAME_A3] = 0;
framep->tf_r[FRAME_R8] = p->p_retval[0];
framep->tf_r[FRAME_R9] = p->p_retval[1];
framep->tf_r[FRAME_R10] = 0;
break;
case ERESTART:
framep->tf_regs[FRAME_PC] = opc;
framep->tf_cr_iip = opc;
break;
case EJUSTRETURN:
break;
@ -620,8 +609,8 @@ syscall(code, framep)
else
error = p->p_sysent->sv_errtbl[error];
}
framep->tf_regs[FRAME_V0] = error;
framep->tf_regs[FRAME_A3] = 1;
framep->tf_r[FRAME_R8] = error;
framep->tf_r[FRAME_R10] = 1;
break;
}
@ -631,7 +620,7 @@ syscall(code, framep)
*/
p = curproc;
userret(p, framep->tf_regs[FRAME_PC], sticks, 1);
userret(p, framep->tf_cr_iip, sticks, 1);
#ifdef KTRACE
if (KTRPOINT(p, KTR_SYSRET))
ktrsysret(p->p_tracep, code, error, p->p_retval[0]);
@ -644,7 +633,6 @@ syscall(code, framep)
*/
STOPEVENT(p, S_SCX, code);
mtx_exit(&Giant, MTX_DEF);
#endif
}
/*

25
sys/ia64/ia64/vm_machdep.c
View File

@ -110,6 +110,14 @@ vm_fault_quick(v, prot)
return(r);
}
struct ia64_fdesc {
u_int64_t func;
u_int64_t gp;
};
#define FDESC_FUNC(fn) (((struct ia64_fdesc *) fn)->func)
#define FDESC_GP(fn) (((struct ia64_fdesc *) fn)->gp)
/*
* Finish a fork operation, with process p2 nearly set up.
* Copy and update the pcb, set up the stack so that the child
@ -185,8 +193,8 @@ cpu_fork(p1, p2, flags)
* Set up return-value registers as fork() libc stub expects.
*/
p2tf->tf_r[FRAME_R8] = 0; /* child's pid (linux) */
p2tf->tf_r[FRAME_R9] = 0; /* no error */
p2tf->tf_r[FRAME_R10] = 1; /* is child (FreeBSD) */
p2tf->tf_r[FRAME_R9] = 1; /* is child (FreeBSD) */
p2tf->tf_r[FRAME_R10] = 0; /* no error */
/*
* Turn off RSE for a moment and work out our current
@ -249,12 +257,17 @@ cpu_fork(p1, p2, flags)
* Arrange for continuation at child_return(), which
* will return to exception_return(). Note that the child
* process doesn't stay in the kernel for long!
*
* We should really deal with the function descriptor
* for child_return in switch_trampoline so that a
* kthread started from a loaded module can have the
* right value for gp.
*/
up->u_pcb.pcb_sp = (u_int64_t)p2tf - 16;
up->u_pcb.pcb_r4 = (u_int64_t)child_return;
up->u_pcb.pcb_r5 = (u_int64_t)exception_return;
up->u_pcb.pcb_r4 = FDESC_FUNC(child_return);
up->u_pcb.pcb_r5 = FDESC_FUNC(exception_return);
up->u_pcb.pcb_r6 = (u_int64_t)p2;
up->u_pcb.pcb_b0 = (u_int64_t)switch_trampoline;
up->u_pcb.pcb_b0 = FDESC_FUNC(switch_trampoline);
}
}
@ -270,7 +283,7 @@ cpu_set_fork_handler(p, func, arg)
void (*func) __P((void *));
void *arg;
{
p->p_addr->u_pcb.pcb_r4 = (u_int64_t) func;
p->p_addr->u_pcb.pcb_r4 = FDESC_FUNC(func);
p->p_addr->u_pcb.pcb_r6 = (u_int64_t) arg;
}

75
sys/ia64/include/asm.h
View File

@ -67,90 +67,48 @@
#endif
/*
* LEAF
* ENTRY
* Declare a global leaf function.
* A leaf function does not call other functions.
*/
#define LEAF(_name_, _n_args_) \
#define ENTRY(_name_, _n_args_) \
.global _name_; \
.align 16; \
.proc _name_; \
_name_:; \
.regstk _n_args_, 0, 0, 0 \
MCOUNT
#define LEAF_NOPROFILE(_name_, _n_args_) \
#define ENTRY_NOPROFILE(_name_, _n_args_) \
.global _name_; \
.align 16; \
.proc _name_; \
_name_:; \
.regstk _n_args_, 0, 0, 0
/*
* STATIC_LEAF
* STATIC_ENTRY
* Declare a local leaf function.
*/
#define STATIC_LEAF(_name_, _n_args_) \
#define STATIC_ENTRY(_name_, _n_args_) \
.align 16; \
.proc _name_; \
_name_:; \
.regstk _n_args_, 0, 0, 0 \
MCOUNT
/*
* XLEAF
* XENTRY
* Global alias for a leaf function, or alternate entry point
*/
#define XLEAF(_name_) \
#define XENTRY(_name_) \
.globl _name_; \
_name_:
/*
* STATIC_XLEAF
* STATIC_XENTRY
* Local alias for a leaf function, or alternate entry point
*/
#define STATIC_XLEAF(_name_) \
_name_:
/*
* NESTED
* Declare a (global) nested function
* A nested function calls other functions and needs
* to use alloc to save registers.
*/
#define NESTED(_name_,_n_args_) \
.globl _name_; \
.proc _name_; \
_name_:; \
.regstk _n_args_, 0, 0, 0 \
MCOUNT
#define NESTED_NOPROFILE(_name_,_n_args_) \
.globl _name_; \
.proc _name_; \
_name_:; \
.regstk _n_args_, 0, 0, 0
/*
* STATIC_NESTED
* Declare a local nested function.
*/
#define STATIC_NESTED(_name_,_n_args_) \
.proc _name_; \
_name_:; \
.regstk _n_args_, 0, 0, 0 \
MCOUNT
/*
* XNESTED
* Same as XLEAF, for a nested function.
*/
#define XNESTED(_name_) \
.globl _name_; \
_name_:
/*
* STATIC_XNESTED
* Same as STATIC_XLEAF, for a nested function.
*/
#define STATIC_XNESTED(_name_) \
#define STATIC_XENTRY(_name_) \
_name_:
@ -201,10 +159,11 @@ _name_ = _value_
* Allocate space for a message (a read-only ascii string)
*/
#define ASCIZ .asciz
#define MSG(msg,reg,label) \
lda reg, label; \
.data; \
label: ASCIZ msg; \
#define MSG(msg,reg,label) \
addl reg,@ltoff(label),gp;; \
ld8 reg=[reg];; \
.data; \
label: ASCIZ msg; \
.text;
/*

160
sys/ia64/include/ia64_cpu.h
View File

@ -182,6 +182,166 @@ ia64_tpa(u_int64_t va)
return result;
}
/*
* Read the value of ar.k0.
*/
static __inline u_int64_t
ia64_get_k0(void)
{
u_int64_t result;
__asm __volatile("mov %0=ar.k0" : "=r" (result));
return result;
}
/*
* Read the value of ar.k1.
*/
static __inline u_int64_t
ia64_get_k1(void)
{
u_int64_t result;
__asm __volatile("mov %0=ar.k1" : "=r" (result));
return result;
}
/*
* Read the value of ar.k2.
*/
static __inline u_int64_t
ia64_get_k2(void)
{
u_int64_t result;
__asm __volatile("mov %0=ar.k2" : "=r" (result));
return result;
}
/*
* Read the value of ar.k3.
*/
static __inline u_int64_t
ia64_get_k3(void)
{
u_int64_t result;
__asm __volatile("mov %0=ar.k3" : "=r" (result));
return result;
}
/*
* Read the value of ar.k4.
*/
static __inline u_int64_t
ia64_get_k4(void)
{
u_int64_t result;
__asm __volatile("mov %0=ar.k4" : "=r" (result));
return result;
}
/*
* Read the value of ar.k5.
*/
static __inline u_int64_t
ia64_get_k5(void)
{
u_int64_t result;
__asm __volatile("mov %0=ar.k5" : "=r" (result));
return result;
}
/*
* Read the value of ar.k6.
*/
static __inline u_int64_t
ia64_get_k6(void)
{
u_int64_t result;
__asm __volatile("mov %0=ar.k6" : "=r" (result));
return result;
}
/*
* Read the value of ar.k7.
*/
static __inline u_int64_t
ia64_get_k7(void)
{
u_int64_t result;
__asm __volatile("mov %0=ar.k7" : "=r" (result));
return result;
}
/*
* Write the value of ar.k0.
*/
static __inline void
ia64_set_k0(u_int64_t v)
{
__asm __volatile("mov ar.k0=%0" :: "r" (v));
}
/*
* Write the value of ar.k1.
*/
static __inline void
ia64_set_k1(u_int64_t v)
{
__asm __volatile("mov ar.k1=%0" :: "r" (v));
}
/*
* Write the value of ar.k2.
*/
static __inline void
ia64_set_k2(u_int64_t v)
{
__asm __volatile("mov ar.k2=%0" :: "r" (v));
}
/*
* Write the value of ar.k3.
*/
static __inline void
ia64_set_k3(u_int64_t v)
{
__asm __volatile("mov ar.k3=%0" :: "r" (v));
}
/*
* Write the value of ar.k4.
*/
static __inline void
ia64_set_k4(u_int64_t v)
{
__asm __volatile("mov ar.k4=%0" :: "r" (v));
}
/*
* Write the value of ar.k5.
*/
static __inline void
ia64_set_k5(u_int64_t v)
{
__asm __volatile("mov ar.k5=%0" :: "r" (v));
}
/*
* Write the value of ar.k6.
*/
static __inline void
ia64_set_k6(u_int64_t v)
{
__asm __volatile("mov ar.k6=%0" :: "r" (v));
}
/*
* Write the value of ar.k7.
*/
static __inline void
ia64_set_k7(u_int64_t v)
{
__asm __volatile("mov ar.k7=%0" :: "r" (v));
}
/*
* Read the value of ar.itc.
*/

25
sys/ia64/include/mutex.h
View File

@ -536,7 +536,9 @@ _mtx_exit(struct mtx *mtxp, int type, const char *file, int line)
#define MTX_ENTER(lck, rPSR, rOLD, rNEW, rLCK) \
mov rPSR=psr ; \
mov rNEW=globalp ; \
mov rLCK=lck+MTX_LOCK ;; \
addl rLCK=@ltoff(lck),gp ;; \
ld8 rLCK=[rLCK] ;; \
add rLCK=MTX_LOCK,rLCK ;; \
rsm psr.i ; \
mov ar.ccv=MTX_UNOWNED ; \
add rNEW=PC_CURPROC,rNEW ;; \
@ -544,18 +546,19 @@ _mtx_exit(struct mtx *mtxp, int type, const char *file, int line)
1: cmpxchg8.acq rOLD=[rLCK],rNEW,ar.ccv ;; \
cmp.eq p1,p0=MTX_UNOWNED,rOLD ;; \
(p1) br.cond.spnt.few 1b ;; \
mov rLCK=lck+MTX_SAVEPSR ;; \
addl rLCK=@ltoff(lck),gp ;; \
ld8 rLCK=[rLCK] ;; \
add rLCK=MTX_SAVEPSR,rLCK ;; \
st4 [rLCK]=rPSR
#define MTX_EXIT(lck, rTMP, rLCK) \
mov rTMP=MTX_UNOWNED ; \
addl rLCK=@ltoff(lck),gp;; \
add rLCK=MTX_LOCK,rLCK;; \
st8.rel [rLCK]=rTMP ;; \
addl rLCK=@ltoff(lck),gp;; \
add rLCK=MTX_SAVEPSR,rLCK;; \
ld4 rTMP=[rLCK] ;; \
mov psr.l=rTMP ;; \
#define MTX_EXIT(lck, rTMP, rLCK) \
mov rTMP=MTX_UNOWNED ; \
addl rLCK=@ltoff(lck),gp;; \
ld8 rLCK=[rLCK];; \
add rLCK=MTX_LOCK,rLCK;; \
st8.rel [rLCK]=rTMP,MTX_SAVEPSR-MTX_LOCK ;; \
ld4 rTMP=[rLCK] ;; \
mov psr.l=rTMP ;; \
srlz.d
#endif /* !LOCORE */

4
sys/ia64/include/pal.h
View File

@ -88,8 +88,8 @@ struct ia64_pal_result {
};
extern struct ia64_pal_result
ia64_call_pal_static(u_int64_t proc, u_int64_t arg1,
u_int64_t arg2, u_int64_t arg3);
ia64_call_pal(u_int64_t proc, u_int64_t arg1,
u_int64_t arg2, u_int64_t arg3);
#endif /* _MACHINE_PAL_H_ */

1
sys/ia64/include/pcb.h
View File

@ -58,6 +58,7 @@ struct pcb {
u_int64_t pcb_unat; /* ar.unat for r4..r7 */
u_int64_t pcb_rnat;
u_int64_t pcb_pr; /* predicates */
u_int64_t pcb_schednest; /* sched_lock state */
u_int64_t pcb_onfault; /* for copy faults */
u_int64_t pcb_accessaddr; /* for [fs]uswintr */

1
sys/ia64/include/proc.h
View File

@ -37,6 +37,7 @@
struct mdproc {
u_long md_flags;
vm_offset_t md_bspstore; /* initial ar.bspstore */
struct trapframe *md_tf; /* trap/syscall registers */
};

68
sys/ia64/include/profile.h
View File

@ -136,74 +136,8 @@ LX99: SETGP(pv)
#define MCOUNT __asm (" \
.globl _mcount; \
.ent _mcount 0; \
.proc _mcount; \
_mcount:; \
.frame $30,0,$26; \
.set noat; \
.set noreorder; \
\
lda $30, -192($30); \
\
stq $28, 0($30); \
stq $0, 8($30); \
stq $1, 16($30); \
stq $2, 24($30); \
stq $3, 32($30); \
stq $4, 40($30); \
stq $5, 48($30); \
stq $6, 56($30); \
stq $7, 64($30); \
stq $8, 72($30); \
stq $15, 80($30); \
stq $16, 88($30); \
stq $17, 96($30); \
stq $18, 104($30); \
stq $19, 112($30); \
stq $20, 120($30); \
stq $21, 128($30); \
stq $22, 136($30); \
stq $23, 144($30); \
stq $24, 152($30); \
stq $25, 160($30); \
stq $26, 168($30); \
stq $27, 176($30); \
stq $29, 184($30); \
\
br $27, LX98; \
LX98: ldgp $29,0($27); \
mov $26, $16; \
mov $28, $17; \
jsr $26,mcount; \
ldgp $29,0($26); \
\
ldq $0, 8($30); \
ldq $1, 16($30); \
ldq $2, 24($30); \
ldq $3, 32($30); \
ldq $4, 40($30); \
ldq $5, 48($30); \
ldq $6, 56($30); \
ldq $7, 64($30); \
ldq $8, 72($30); \
ldq $15, 80($30); \
ldq $16, 88($30); \
ldq $17, 96($30); \
ldq $18, 104($30); \
ldq $19, 112($30); \
ldq $20, 120($30); \
ldq $21, 128($30); \
ldq $22, 136($30); \
ldq $23, 144($30); \
ldq $24, 152($30); \
ldq $25, 160($30); \
ldq $26, 168($30); \
ldq $27, 176($30); \
ldq $29, 184($30); \
\
ldq $28, 0($30); \
\
lda $30, 192($30); \
ret $31, ($28), 1; \
\
.end _mcount");

6
sys/ia64/include/reg.h
View File

@ -29,10 +29,16 @@
#ifndef _MACHINE_REG_H_
#define _MACHINE_REG_H_
#ifndef _IA64_FPREG_DEFINED
struct ia64_fpreg {
u_int64_t fpr_bits[2];
} __attribute__ ((aligned (16)));
#define _IA64_FPREG_DEFINED
#endif
struct reg {
u_int64_t r_regs[128];
};

10
sys/ia64/include/signal.h
View File

@ -35,6 +35,16 @@ typedef long sig_atomic_t;
#ifndef _ANSI_SOURCE
#ifndef _IA64_FPREG_DEFINED
struct ia64_fpreg {
unsigned long fpr_bits[2];
} __attribute__ ((aligned (16)));
#define _IA64_FPREG_DEFINED
#endif
/*
* Information pushed on stack when a signal is delivered.
* This is used by the kernel to restore state following

10
sys/ia64/include/vmparam.h
View File

@ -54,15 +54,7 @@
* kernel stack.
*/
#define USRTEXT CLBYTES
/* #define USRSTACK VM_MAXUSER_ADDRESS */
/*
* This stack location is suitable for OSF1 emulation. Some OSF
* programs are built as 32bit and assume that the stack is reachable
* with a 32bit value. OSF1 manages to have a variable location for
* the user stack which we should probably also support.
*/
#define USRSTACK (0x12000000LL - (UPAGES*PAGE_SIZE))
#define USRSTACK VM_MAXUSER_ADDRESS
/*
* Virtual memory related constants, all in bytes

141
sys/libkern/ia64/__divdi3.S Normal file
View File

@ -0,0 +1,141 @@
.file "__divdi3.s"
// $FreeBSD$
//
// Copyright (c) 2000, Intel Corporation
// All rights reserved.
//
// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
// Intel Corporation.
//
// WARRANTY DISCLAIMER
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Intel Corporation is the author of this code, and requests that all
// problem reports or change requests be submitted to it directly at
// http://developer.intel.com/opensource.
//
.section .text
.proc __divdi3#
.align 32
.global __divdi3#
.align 32
// 64-bit signed integer divide
__divdi3:
{ .mii
alloc r31=ar.pfs,2,0,0,0
nop.i 0
nop.i 0;;
} { .mmi
// 64-BIT SIGNED INTEGER DIVIDE BEGINS HERE
setf.sig f8=r32
setf.sig f9=r33
nop.i 0;;
} { .mfb
nop.m 0
fcvt.xf f6=f8
nop.b 0
} { .mfb
nop.m 0
fcvt.xf f7=f9
nop.b 0;;
} { .mfi
nop.m 0
// Step (1)
// y0 = 1 / b in f8
frcpa.s1 f8,p6=f6,f7
nop.i 0;;
} { .mfi
nop.m 0
// Step (2)
// e0 = 1 - b * y0 in f9
(p6) fnma.s1 f9=f7,f8,f1
nop.i 0
} { .mfi
nop.m 0
// Step (3)
// q0 = a * y0 in f10
(p6) fma.s1 f10=f6,f8,f0
nop.i 0;;
} { .mfi
nop.m 0
// Step (4)
// e1 = e0 * e0 in f11
(p6) fma.s1 f11=f9,f9,f0
nop.i 0
} { .mfi
nop.m 0
// Step (5)
// q1 = q0 + e0 * q0 in f10
(p6) fma.s1 f10=f9,f10,f10
nop.i 0;;
} { .mfi
nop.m 0
// Step (6)
// y1 = y0 + e0 * y0 in f8
(p6) fma.s1 f8=f9,f8,f8
nop.i 0;;
} { .mfi
nop.m 0
// Step (7)
// q2 = q1 + e1 * q1 in f9
(p6) fma.s1 f9=f11,f10,f10
nop.i 0;;
} { .mfi
nop.m 0
// Step (8)
// y2 = y1 + e1 * y1 in f8
(p6) fma.s1 f8=f11,f8,f8
nop.i 0;;
} { .mfi
nop.m 0
// Step (9)
// r2 = a - b * q2 in f10
(p6) fnma.s1 f10=f7,f9,f6
nop.i 0;;
} { .mfi
nop.m 0
// Step (10)
// q3 = q2 + r2 * y2 in f8
(p6) fma.s1 f8=f10,f8,f9
nop.i 0;;
} { .mfb
nop.m 0
// Step (11)
// q = trunc (q3)
fcvt.fx.trunc.s1 f8=f8
nop.b 0;;
} { .mmi
// quotient will be in r8 (if b != 0)
getf.sig r8=f8
nop.m 0
nop.i 0;;
}
// 64-BIT SIGNED INTEGER DIVIDE ENDS HERE
{ .mmb
nop.m 0
nop.m 0
br.ret.sptk b0;;
}
.endp __divdi3

123
sys/libkern/ia64/__divsi3.S Normal file
View File

@ -0,0 +1,123 @@
.file "__divsi3.s"
// $FreeBSD$
//
// Copyright (c) 2000, Intel Corporation
// All rights reserved.
//
// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
// Intel Corporation.
//
// WARRANTY DISCLAIMER
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Intel Corporation is the author of this code, and requests that all
// problem reports or change requests be submitted to it directly at
// http://developer.intel.com/opensource.
//
.section .text
// 32-bit signed integer divide
.proc __divsi3#
.align 32
.global __divsi3#
.align 32
__divsi3:
{ .mii
alloc r31=ar.pfs,2,0,0,0
nop.i 0
nop.i 0;;
} { .mii
nop.m 0
// 32-BIT SIGNED INTEGER DIVIDE BEGINS HERE
// general register used:
// r32 - 32-bit signed integer dividend
// r33 - 32-bit signed integer divisor
// r8 - 32-bit signed integer result
// r2 - scratch register
// floating-point registers used: f6, f7, f8, f9
// predicate registers used: p6
sxt4 r32=r32
sxt4 r33=r33;;
} { .mmb
setf.sig f6=r32
setf.sig f7=r33
nop.b 0;;
} { .mfi
nop.m 0
fcvt.xf f6=f6
nop.i 0
} { .mfi
nop.m 0
fcvt.xf f7=f7
mov r2 = 0x0ffdd;;
} { .mfi
setf.exp f9 = r2
// (1) y0
frcpa.s1 f8,p6=f6,f7
nop.i 0;;
} { .mfi
nop.m 0
// (2) q0 = a * y0
(p6) fma.s1 f6=f6,f8,f0
nop.i 0
} { .mfi
nop.m 0
// (3) e0 = 1 - b * y0
(p6) fnma.s1 f7=f7,f8,f1
nop.i 0;;
} { .mfi
nop.m 0
// (4) q1 = q0 + e0 * q0
(p6) fma.s1 f6=f7,f6,f6
nop.i 0
} { .mfi
nop.m 0
// (5) e1 = e0 * e0 + 2^-34
(p6) fma.s1 f7=f7,f7,f9
nop.i 0;;
} { .mfi
nop.m 0
// (6) q2 = q1 + e1 * q1
(p6) fma.s1 f8=f7,f6,f6
nop.i 0;;
} { .mfi
nop.m 0
// (7) q = trunc(q2)
fcvt.fx.trunc.s1 f8=f8
nop.i 0;;
} { .mmi
// quotient will be in the least significant 32 bits of r8 (if b != 0)
getf.sig r8=f8
nop.m 0
nop.i 0;;
}
// 32-BIT SIGNED INTEGER DIVIDE ENDS HERE
{ .mmb
nop.m 0
nop.m 0
br.ret.sptk b0;;
}
.endp __divsi3

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.file "__moddi3.s"
// $FreeBSD$
//
// Copyright (c) 2000, Intel Corporation
// All rights reserved.
//
// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
// Intel Corporation.
//
// WARRANTY DISCLAIMER
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Intel Corporation is the author of this code, and requests that all
// problem reports or change requests be submitted to it directly at
// http://developer.intel.com/opensource.
//
.section .text
// 64-bit signed integer remainder
.proc __moddi3#
.align 32
.global __moddi3#
.align 32
__moddi3:
{ .mii
alloc r31=ar.pfs,3,0,0,0
nop.i 0
nop.i 0
} { .mmb
// 64-BIT SIGNED INTEGER REMAINDER BEGINS HERE
// general register used:
// r32 - 64-bit signed integer dividend
// r33 - 64-bit signed integer divisor
// r8 - 64-bit signed integer result
// r2 - scratch register
// floating-point registers used: f6, f7, f8, f9, f10, f11, f12
// predicate registers used: p6
setf.sig f12=r32 // holds a in integer form
setf.sig f7=r33
nop.b 0
} { .mlx
nop.m 0
//movl r2=0x8000000000000000;;
movl r2=0xffffffffffffffff;;
} { .mfi
// get the 2's complement of b
sub r33=r0,r33
fcvt.xf f6=f12
nop.i 0
} { .mfi
nop.m 0
fcvt.xf f7=f7
nop.i 0;;
} { .mfi
nop.m 0
// Step (1)
// y0 = 1 / b in f8
frcpa.s1 f8,p6=f6,f7
nop.i 0;;
} { .mfi
nop.m 0
// Step (2)
// q0 = a * y0 in f10
(p6) fma.s1 f10=f6,f8,f0
nop.i 0
} { .mfi
nop.m 0
// Step (3)
// e0 = 1 - b * y0 in f9
(p6) fnma.s1 f9=f7,f8,f1
nop.i 0;;
} { .mfi
nop.m 0
// Step (4)
// q1 = q0 + e0 * q0 in f10
(p6) fma.s1 f10=f9,f10,f10
nop.i 0
} { .mfi
nop.m 0
// Step (5)
// e1 = e0 * e0 in f11
(p6) fma.s1 f11=f9,f9,f0
nop.i 0;;
} { .mfi
nop.m 0
// Step (6)
// y1 = y0 + e0 * y0 in f8
(p6) fma.s1 f8=f9,f8,f8
nop.i 0;;
} { .mfi
nop.m 0
// Step (7)
// q2 = q1 + e1 * q1 in f9
(p6) fma.s1 f9=f11,f10,f10
nop.i 0;;
} { .mfi
nop.m 0
// Step (8)
// y2 = y1 + e1 * y1 in f8
(p6) fma.s1 f8=f11,f8,f8
nop.i 0;;
} { .mfi
nop.m 0
// Step (9)
// r2 = a - b * q2 in f10
(p6) fnma.s1 f10=f7,f9,f6
nop.i 0;;
} { .mfi
setf.sig f7=r33
// Step (10)
// q3 = q2 + r2 * y2 in f8
(p6) fma.s1 f8=f10,f8,f9
nop.i 0;;
} { .mfi
nop.m 0
// (11) q = trunc(q3)
fcvt.fx.trunc.s1 f8=f8
nop.i 0;;
} { .mfi
nop.m 0
// (12) r = a + (-b) * q
xma.l f8=f8,f7,f12
nop.i 0;;
} { .mib
getf.sig r8=f8
nop.i 0
nop.b 0
}
// 64-BIT SIGNED INTEGER REMAINDER ENDS HERE
{ .mib
nop.m 0
nop.i 0
br.ret.sptk b0;;
}
.endp __moddi3

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.file "__modsi3.s"
// $FreeBSD$
//
// Copyright (c) 2000, Intel Corporation
// All rights reserved.
//
// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
// Intel Corporation.
//
// WARRANTY DISCLAIMER
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Intel Corporation is the author of this code, and requests that all
// problem reports or change requests be submitted to it directly at
// http://developer.intel.com/opensource.
//
.section .text
// 32-bit signed integer remainder
.proc __modsi3#
.align 32
.global __modsi3#
.align 32
__modsi3:
{ .mii
alloc r31=ar.pfs,2,0,0,0
nop.i 0
nop.i 0;;
} { .mii
nop.m 0
// 32-BIT SIGNED INTEGER REMAINDER BEGINS HERE
// general register used:
// r32 - 32-bit signed integer dividend
// r33 - 32-bit signed integer divisor
// r8 - 32-bit signed integer result
// r2 - scratch register
// floating-point registers used: f6, f7, f8, f9, f10, f11
// predicate registers used: p6
sxt4 r32=r32
sxt4 r33=r33;;
} { .mmb
setf.sig f11=r32
setf.sig f7=r33
nop.b 0;;
} { .mfi
// get 2's complement of b
sub r33=r0,r33
fcvt.xf f6=f11
nop.i 0
} { .mfi
nop.m 0
fcvt.xf f7=f7
mov r2 = 0x0ffdd;;
} { .mfi
setf.exp f9 = r2
// (1) y0
frcpa.s1 f8,p6=f6,f7
nop.i 0;;
} { .mfi
nop.m 0
// (2) q0 = a * y0
(p6) fma.s1 f10=f6,f8,f0
nop.i 0
} { .mfi
nop.m 0
// (3) e0 = 1 - b * y0
(p6) fnma.s1 f8=f7,f8,f1
nop.i 0;;
} { .mfi
// 2's complement of b
setf.sig f7=r33
// (4) q1 = q0 + e0 * q0
(p6) fma.s1 f10=f8,f10,f10
nop.i 0
} { .mfi
nop.m 0
// (5) e1 = e0 * e0 + 2^-34
(p6) fma.s1 f8=f8,f8,f9
nop.i 0;;
} { .mfi
nop.m 0
// (6) q2 = q1 + e1 * q1
(p6) fma.s1 f8=f8,f10,f10
nop.i 0;;
} { .mfi
nop.m 0
// (7) q = trunc(q2)
fcvt.fx.trunc.s1 f8=f8
nop.i 0;;
} { .mfi
nop.m 0
// (8) r = a + (-b) * q
xma.l f8=f8,f7,f11
nop.i 0;;
} { .mmi
// remainder will be in the least significant 32 bits of r8 (if b != 0)
getf.sig r8=f8
nop.m 0
nop.i 0;;
}
// 32-BIT SIGNED INTEGER REMAINDER ENDS HERE
{ .mmb
nop.m 0
nop.m 0
br.ret.sptk b0;;
}
.endp __modsi3

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.file "__udivdi3.s"
// $FreeBSD$
//
// Copyright (c) 2000, Intel Corporation
// All rights reserved.
//
// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
// Intel Corporation.
//
// WARRANTY DISCLAIMER
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Intel Corporation is the author of this code, and requests that all
// problem reports or change requests be submitted to it directly at
// http://developer.intel.com/opensource.
//
.section .text
.proc __udivdi3#
.align 32
.global __udivdi3#
.align 32
// 64-bit unsigned integer divide
__udivdi3:
{ .mii
alloc r31=ar.pfs,2,0,0,0
nop.i 0
nop.i 0;;
}
{ .mmi
// 64-BIT UNSIGNED INTEGER DIVIDE BEGINS HERE
setf.sig f8=r32
setf.sig f9=r33
nop.i 0;;
} { .mfb
nop.m 0
fma.s1 f6=f8,f1,f0
nop.b 0
} { .mfb
nop.m 0
fma.s1 f7=f9,f1,f0
nop.b 0;;
} { .mfi
nop.m 0
// Step (1)
// y0 = 1 / b in f8
frcpa.s1 f8,p6=f6,f7
nop.i 0;;
} { .mfi
nop.m 0
// Step (2)
// e0 = 1 - b * y0 in f9
(p6) fnma.s1 f9=f7,f8,f1
nop.i 0
} { .mfi
nop.m 0
// Step (3)
// q0 = a * y0 in f10
(p6) fma.s1 f10=f6,f8,f0
nop.i 0;;
} { .mfi
nop.m 0
// Step (4)
// e1 = e0 * e0 in f11
(p6) fma.s1 f11=f9,f9,f0
nop.i 0
} { .mfi
nop.m 0
// Step (5)
// q1 = q0 + e0 * q0 in f10
(p6) fma.s1 f10=f9,f10,f10
nop.i 0;;
} { .mfi
nop.m 0
// Step (6)
// y1 = y0 + e0 * y0 in f8
(p6) fma.s1 f8=f9,f8,f8
nop.i 0;;
} { .mfi
nop.m 0
// Step (7)
// q2 = q1 + e1 * q1 in f9
(p6) fma.s1 f9=f11,f10,f10
nop.i 0;;
} { .mfi
nop.m 0
// Step (8)
// y2 = y1 + e1 * y1 in f8
(p6) fma.s1 f8=f11,f8,f8
nop.i 0;;
} { .mfi
nop.m 0
// Step (9)
// r2 = a - b * q2 in f10
(p6) fnma.s1 f10=f7,f9,f6
nop.i 0;;
} { .mfi
nop.m 0
// Step (10)
// q3 = q2 + r2 * y2 in f8
(p6) fma.s1 f8=f10,f8,f9
nop.i 0;;
} { .mfb
nop.m 0
// (11) q = trunc(q3)
fcvt.fxu.trunc.s1 f8=f8
nop.b 0;;
} { .mmi
// quotient will be in r8 (if b != 0)
getf.sig r8=f8
nop.m 0
nop.i 0;;
}
// 64-BIT UNSIGNED INTEGER DIVIDE ENDS HERE
{ .mmb
nop.m 0
nop.m 0
br.ret.sptk b0;;
}
.endp __udivdi3

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.file "__udivsi3.s"
// $FreeBSD$
//
// Copyright (c) 2000, Intel Corporation
// All rights reserved.
//
// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
// Intel Corporation.
//
// WARRANTY DISCLAIMER
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Intel Corporation is the author of this code, and requests that all
// problem reports or change requests be submitted to it directly at
// http://developer.intel.com/opensource.
//
.section .text
// 32-bit unsigned integer divide
.proc __udivsi3#
.align 32
.global __udivsi3#
.align 32
__udivsi3:
{ .mii
alloc r31=ar.pfs,2,0,0,0
nop.i 0
nop.i 0;;
} { .mii
nop.m 0
// 32-BIT UNSIGNED INTEGER DIVIDE BEGINS HERE
// general register used:
// r32 - 32-bit unsigned integer dividend
// r33 - 32-bit unsigned integer divisor
// r8 - 32-bit unsigned integer result
// r2 - scratch register
// floating-point registers used: f6, f7, f8, f9
// predicate registers used: p6
zxt4 r32=r32
zxt4 r33=r33;;
} { .mmb
setf.sig f6=r32
setf.sig f7=r33
nop.b 0;;
} { .mfi
nop.m 0
fcvt.xf f6=f6
nop.i 0
} { .mfi
nop.m 0
fcvt.xf f7=f7
mov r2 = 0x0ffdd;;
} { .mfi
setf.exp f9 = r2
// (1) y0
frcpa.s1 f8,p6=f6,f7
nop.i 0;;
} { .mfi
nop.m 0
// (2) q0 = a * y0
(p6) fma.s1 f6=f6,f8,f0
nop.i 0
} { .mfi
nop.m 0
// (3) e0 = 1 - b * y0
(p6) fnma.s1 f7=f7,f8,f1
nop.i 0;;
} { .mfi
nop.m 0
// (4) q1 = q0 + e0 * q0
(p6) fma.s1 f6=f7,f6,f6
nop.i 0
} { .mfi
nop.m 0
// (5) e1 = e0 * e0 + 2^-34
(p6) fma.s1 f7=f7,f7,f9
nop.i 0;;
} { .mfi
nop.m 0
// (6) q2 = q1 + e1 * q1
(p6) fma.s1 f8=f7,f6,f6
nop.i 0;;
} { .mfi
nop.m 0
// (7) q = trunc(q2)
fcvt.fxu.trunc.s1 f8=f8
nop.i 0;;
} { .mmi
// quotient will be in the least significant 32 bits of r8 (if b != 0)
getf.sig r8=f8
nop.m 0
nop.i 0;;
}
// 32-BIT UNSIGNED INTEGER DIVIDE ENDS HERE
{ .mmb
nop.m 0
nop.m 0
br.ret.sptk b0;;
}
.endp __udivsi3

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.file "__umoddi3.s"
// $FreeBSD$
//
// Copyright (c) 2000, Intel Corporation
// All rights reserved.
//
// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
// Intel Corporation.
//
// WARRANTY DISCLAIMER
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Intel Corporation is the author of this code, and requests that all
// problem reports or change requests be submitted to it directly at
// http://developer.intel.com/opensource.
//
.section .text
// 64-bit unsigned integer remainder
.proc __umoddi3#
.align 32
.global __umoddi3#
.align 32
__umoddi3:
{ .mii
alloc r31=ar.pfs,3,0,0,0
nop.i 0
nop.i 0
} { .mmb
// 64-BIT UNSIGNED INTEGER REMAINDER BEGINS HERE
// general register used:
// r32 - 64-bit unsigned integer dividend
// r33 - 64-bit unsigned integer divisor
// r8 - 64-bit unsigned integer result
// floating-point registers used: f6, f7, f8, f9, f10, f11, f12
// predicate registers used: p6
setf.sig f12=r32 // holds a in integer form
setf.sig f7=r33
nop.b 0;;
} { .mfi
// get 2's complement of b
sub r33=r0,r33
fcvt.xuf.s1 f6=f12
nop.i 0
} { .mfi
nop.m 0
fcvt.xuf.s1 f7=f7
nop.i 0;;
} { .mfi
nop.m 0
// Step (1)
// y0 = 1 / b in f8
frcpa.s1 f8,p6=f6,f7
nop.i 0;;
} { .mfi
nop.m 0
// Step (2)
// q0 = a * y0 in f10
(p6) fma.s1 f10=f6,f8,f0
nop.i 0
} { .mfi
nop.m 0
// Step (3)
// e0 = 1 - b * y0 in f9
(p6) fnma.s1 f9=f7,f8,f1
nop.i 0;;
} { .mfi
nop.m 0
// Step (4)
// q1 = q0 + e0 * q0 in f10
(p6) fma.s1 f10=f9,f10,f10
nop.i 0
} { .mfi
nop.m 0
// Step (5)
// e1 = e0 * e0 in f11
(p6) fma.s1 f11=f9,f9,f0
nop.i 0;;
} { .mfi
nop.m 0
// Step (6)
// y1 = y0 + e0 * y0 in f8
(p6) fma.s1 f8=f9,f8,f8
nop.i 0;;
} { .mfi
nop.m 0
// Step (7)
// q2 = q1 + e1 * q1 in f9
(p6) fma.s1 f9=f11,f10,f10
nop.i 0;;
} { .mfi
nop.m 0
// Step (8)
// y2 = y1 + e1 * y1 in f8
(p6) fma.s1 f8=f11,f8,f8
nop.i 0;;
} { .mfi
nop.m 0
// Step (9)
// r2 = a - b * q2 in f10
(p6) fnma.s1 f10=f7,f9,f6
nop.i 0;;
} { .mfi
// f7=-b
setf.sig f7=r33
// Step (10)
// q3 = q2 + r2 * y2 in f8
(p6) fma.s1 f8=f10,f8,f9
nop.i 0;;
} { .mfi
nop.m 0
// (11) q = trunc(q3)
fcvt.fxu.trunc.s1 f8=f8
nop.i 0;;
} { .mfi
nop.m 0
// (12) r = a + (-b) * q
xma.l f8=f8,f7,f12
nop.i 0;;
} { .mib
getf.sig r8=f8
nop.i 0
nop.b 0
}
// 64-BIT UNSIGNED INTEGER REMAINDER ENDS HERE
{ .mib
nop.m 0
nop.i 0
br.ret.sptk b0;;
}
.endp __umoddi3

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.file "__umodsi3.s"
// $FreeBSD$
//
// Copyright (c) 2000, Intel Corporation
// All rights reserved.
//
// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
// Intel Corporation.
//
// WARRANTY DISCLAIMER
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Intel Corporation is the author of this code, and requests that all
// problem reports or change requests be submitted to it directly at
// http://developer.intel.com/opensource.
//
.section .text
// 32-bit unsigned integer remainder
.proc __umodsi3#
.align 32
.global __umodsi3#
.align 32
__umodsi3:
{ .mii
alloc r31=ar.pfs,2,0,0,0
nop.i 0
nop.i 0;;
} { .mii
nop.m 0
// 32-BIT UNSIGNED INTEGER REMAINDER BEGINS HERE
// general register used:
// r32 - 32-bit unsigned integer dividend
// r33 - 32-bit unsigned integer divisor
// r8 - 32-bit unsigned integer result
// r2 - scratch register
// floating-point registers used: f6, f7, f8, f9, f10, f11
// predicate registers used: p6
zxt4 r32=r32
zxt4 r33=r33;;
} { .mmb
setf.sig f11=r32
setf.sig f7=r33
nop.b 0;;
} { .mfi
nop.m 0
fcvt.xf f6=f11
nop.i 0
} { .mfi
// get 2's complement of b
sub r33=r0,r33
fcvt.xf f7=f7
mov r2 = 0x0ffdd;;
} { .mfi
setf.exp f9 = r2
// (1) y0
frcpa.s1 f8,p6=f6,f7
nop.i 0;;
} { .mfi
nop.m 0
// (2) q0 = a * y0
(p6) fma.s1 f10=f6,f8,f0
nop.i 0
} { .mfi
nop.m 0
// (3) e0 = 1 - b * y0
(p6) fnma.s1 f8=f7,f8,f1
nop.i 0;;
} { .mfi
nop.m 0
// (4) q1 = q0 + e0 * q0
(p6) fma.s1 f10=f8,f10,f10
nop.i 0
} { .mfi
// get 2's complement of b
setf.sig f7=r33
// (5) e1 = e0 * e0 + 2^-34
(p6) fma.s1 f8=f8,f8,f9
nop.i 0;;
} { .mfi
nop.m 0
// (6) q2 = q1 + e1 * q1
(p6) fma.s1 f8=f8,f10,f10
nop.i 0;;
} { .mfi
nop.m 0
// (7) q = trunc(q2)
fcvt.fxu.trunc.s1 f8=f8
nop.i 0;;
} { .mfi
nop.m 0
// (8) r = a + (-b) * q
xma.l f8=f8,f7,f11
nop.i 0;;
} { .mmi
// remainder will be in the least significant 32 bits of r8 (if b != 0)
getf.sig r8=f8
nop.m 0
nop.i 0;;
}
// 32-BIT UNSIGNED INTEGER REMAINDER ENDS HERE
{ .mmb
nop.m 0
nop.m 0
br.ret.sptk b0;;
}
.endp __umodsi3

47
sys/libkern/ia64/byte_swap_2.S Normal file
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/* $FreeBSD$ */
/* $NetBSD: byte_swap_2.S,v 1.2 1996/10/17 03:08:08 cgd Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#include <machine/asm.h>
#ifndef NAME
#define NAME byte_swap_2
#endif
/*
* Byte-swap a 2-byte quantity. (Convert 0x0123 to 0x2301.)
*
* Argument is an unsigned 2-byte integer (u_int16_t).
*/
ENTRY(NAME, 1) /* in0 = 0x0123 */
extr.u ret0=in0,8,8 /* ret0 = 0x 01 */
;;
dep ret0=ret0,in0,8,8 /* ret0 = 0x2301 */
br.ret.sptk.few rp
END(NAME)

54
sys/libkern/ia64/byte_swap_4.S Normal file
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/* $FreeBSD$ */
/* $NetBSD: byte_swap_4.S,v 1.2 1996/10/17 03:08:09 cgd Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#include <machine/asm.h>
#ifndef NAME
#define NAME byte_swap_4
#endif
/*
* Byte-swap a 4-byte quantity. (Convert 0x01234567 to 0x67452301.)
*
* Argument is an unsigned 4-byte integer (u_int32_t).
*/
ENTRY(NAME, 1) /* in0 = 0x01234567 */
extr.u r16=in0,0,8 /* r16 = 0x 67 */
extr.u r17=in0,8,8 /* r17 = 0x 45 */
extr.u r18=in0,16,8 /* r18 = 0x 23 */
extr.u ret0=in0,24,8 /* ret0 = 0x 01 */
;;
dep ret0=ret0,r16,24,8 /* ret0 = 0x67 01 */
;;
dep ret0=ret0,r17,16,8 /* ret0 = 0x6745 01 */
;;
dep ret0=ret0,r16,8,8 /* ret0 = 0x67452301 */
br.ret.sptk.few rp
END(NAME)

33
sys/libkern/ia64/htonl.S Normal file
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/* $FreeBSD$ */
/* $NetBSD: htonl.S,v 1.1 1996/04/17 22:36:52 cgd Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#define NAME htonl
#include <libkern/ia64/byte_swap_4.S>

33
sys/libkern/ia64/htons.S Normal file
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/* $FreeBSD$ */
/* $NetBSD: htons.S,v 1.1 1996/04/17 22:36:54 cgd Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#define NAME htons
#include <libkern/ia64/byte_swap_2.S>

33
sys/libkern/ia64/ntohl.S Normal file
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/* $FreeBSD$ */
/* $NetBSD: ntohl.S,v 1.1 1996/04/17 22:36:57 cgd Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#define NAME ntohl
#include <libkern/ia64/byte_swap_4.S>

33
sys/libkern/ia64/ntohs.S Normal file
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/* $FreeBSD$ */
/* $NetBSD: ntohs.S,v 1.1 1996/04/17 22:37:02 cgd Exp $ */
/*
* Copyright (c) 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#define NAME ntohs
#include <libkern/ia64/byte_swap_2.S>