Add some new fields and bits from NVMe 1.4.
MFC after: 2 weeks Sponsored by: iXsystems, Inc.
This commit is contained in:
Alexander Motin
parent
f9e3413a3c
commit
8de2d8c009
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=350399
@ -49,7 +49,7 @@ nvme_print_controller(struct nvme_controller_data *cdata)
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uint8_t str[128];
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char cbuf[UINT128_DIG + 1];
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uint16_t oncs, oacs;
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uint8_t compare, write_unc, dsm, vwc_present;
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uint8_t compare, write_unc, dsm, t;
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uint8_t security, fmt, fw, nsmgmt;
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uint8_t fw_slot1_ro, fw_num_slots;
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uint8_t ns_smart;
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@ -63,8 +63,6 @@ nvme_print_controller(struct nvme_controller_data *cdata)
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NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK;
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dsm = (oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) &
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NVME_CTRLR_DATA_ONCS_DSM_MASK;
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vwc_present = (cdata->vwc >> NVME_CTRLR_DATA_VWC_PRESENT_SHIFT) &
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NVME_CTRLR_DATA_VWC_PRESENT_MASK;
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oacs = cdata->oacs;
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security = (oacs >> NVME_CTRLR_DATA_OACS_SECURITY_SHIFT) &
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@ -107,8 +105,10 @@ nvme_print_controller(struct nvme_controller_data *cdata)
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printf("Recommended Arb Burst: %d\n", cdata->rab);
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printf("IEEE OUI Identifier: %02x %02x %02x\n",
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cdata->ieee[0], cdata->ieee[1], cdata->ieee[2]);
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printf("Multi-Path I/O Capabilities: %s%s%s%s\n",
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printf("Multi-Path I/O Capabilities: %s%s%s%s%s\n",
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(cdata->mic == 0) ? "Not Supported" : "",
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((cdata->mic >> NVME_CTRLR_DATA_MIC_ANAR_SHIFT) &
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NVME_CTRLR_DATA_MIC_SRIOVVF_MASK) ? "Asymmetric, " : "",
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((cdata->mic >> NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT) &
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NVME_CTRLR_DATA_MIC_SRIOVVF_MASK) ? "SR-IOV VF, " : "",
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((cdata->mic >> NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT) &
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@ -149,9 +149,24 @@ nvme_print_controller(struct nvme_controller_data *cdata)
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printf("Virtualization Management: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_VM_SHIFT) &
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NVME_CTRLR_DATA_OACS_VM_MASK) ? "" : "Not ");
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printf("Doorbell Buffer Config %sSupported\n",
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printf("Doorbell Buffer Config: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT) &
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NVME_CTRLR_DATA_OACS_DBBUFFER_MASK) ? "" : "Not ");
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printf("Get LBA Status: %sSupported\n",
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((oacs >> NVME_CTRLR_DATA_OACS_GETLBA_SHIFT) &
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NVME_CTRLR_DATA_OACS_GETLBA_MASK) ? "" : "Not ");
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printf("Sanitize: ");
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if (cdata->sanicap != 0) {
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printf("%s%s%s\n",
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((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_CES_SHIFT) &
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NVME_CTRLR_DATA_SANICAP_CES_SHIFT) ? "crypto, " : "",
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((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_BES_SHIFT) &
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NVME_CTRLR_DATA_SANICAP_BES_SHIFT) ? "block, " : "",
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((cdata->sanicap >> NVME_CTRLR_DATA_SANICAP_OWS_SHIFT) &
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NVME_CTRLR_DATA_SANICAP_OWS_SHIFT) ? "overwrite" : "");
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} else {
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printf("Not Supported\n");
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}
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printf("Abort Command Limit: %d\n", cdata->acl+1);
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printf("Async Event Request Limit: %d\n", cdata->aerl+1);
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printf("Number of Firmware Slots: ");
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@ -197,6 +212,9 @@ nvme_print_controller(struct nvme_controller_data *cdata)
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printf("Timestamp feature: %sSupported\n",
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((oncs >> NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT) &
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NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK) ? "" : "Not ");
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printf("Verify feature: %sSupported\n",
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((oncs >> NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT) &
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NVME_CTRLR_DATA_ONCS_VERIFY_MASK) ? "" : "Not ");
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printf("Fused Operation Support: %s%s\n",
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(cdata->fuses == 0) ? "Not Supported" : "",
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((cdata->fuses >> NVME_CTRLR_DATA_FUSES_CNW_SHIFT) &
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@ -208,8 +226,13 @@ nvme_print_controller(struct nvme_controller_data *cdata)
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NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK) ? "All-NVM" : "Per-NS",
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((cdata->fna >> NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT) &
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NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK) ? "All-NVM" : "Per-NS");
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printf("Volatile Write Cache: %s\n",
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vwc_present ? "Present" : "Not Present");
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t = (cdata->vwc >> NVME_CTRLR_DATA_VWC_ALL_SHIFT) &
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NVME_CTRLR_DATA_VWC_ALL_MASK;
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printf("Volatile Write Cache: %s%s\n",
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((cdata->vwc >> NVME_CTRLR_DATA_VWC_PRESENT_SHIFT) &
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NVME_CTRLR_DATA_VWC_PRESENT_MASK) ? "Present" : "Not Present",
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(t == NVME_CTRLR_DATA_VWC_ALL_NO) ? ", no flush all" :
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(t == NVME_CTRLR_DATA_VWC_ALL_YES) ? ", flush all" : "");
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if (nsmgmt) {
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printf("\n");
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@ -175,6 +175,9 @@
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/* SR-IOV Virtual Function */
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#define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2)
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#define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1)
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/* Asymmetric Namespace Access Reporting */
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#define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3)
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#define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1)
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/** OACS - optional admin command support */
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/* supports security send/receive commands */
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@ -204,6 +207,9 @@
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/* supports Doorbell Buffer Config */
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#define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8)
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#define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1)
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/* supports Get LBA Status */
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#define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9)
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#define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1)
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/** firmware updates */
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/* first slot is read-only */
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@ -212,6 +218,9 @@
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/* number of firmware slots */
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#define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1)
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#define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7)
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/* firmware activation without reset */
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#define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4)
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#define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1)
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/** log page attributes */
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/* per namespace smart/health log page */
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@ -228,6 +237,26 @@
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#define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0)
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#define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1)
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/** Sanitize Capabilities */
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/* Crypto Erase Support */
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#define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0)
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#define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1)
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/* Block Erase Support */
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#define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1)
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#define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1)
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/* Overwrite Support */
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#define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2)
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#define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1)
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/* No-Deallocate Inhibited */
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#define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29)
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#define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1)
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/* No-Deallocate Modifies Media After Sanitize */
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#define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30)
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#define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3)
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#define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0)
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#define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1)
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#define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2)
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/** submission queue entry size */
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#define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0)
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#define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF)
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@ -255,6 +284,8 @@
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#define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1)
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#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6)
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#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1)
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#define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7)
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#define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1)
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/** Fused Operation Support */
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#define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0)
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@ -269,8 +300,15 @@
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#define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1)
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/** volatile write cache */
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/* volatile write cache present */
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#define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0)
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#define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1)
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/* flush all namespaces supported */
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#define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1)
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#define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3)
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#define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0)
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#define NVME_CTRLR_DATA_VWC_ALL_NO (2)
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#define NVME_CTRLR_DATA_VWC_ALL_YES (3)
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/** namespace features */
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/* thin provisioning */
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@ -285,6 +323,9 @@
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/* NGUID and EUI64 fields are not reusable */
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#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3)
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#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1)
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/* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
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#define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4)
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#define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1)
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/** formatted lba size */
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#define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0)
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@ -793,12 +834,27 @@ struct nvme_controller_data {
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/** Controller Attributes */
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uint32_t ctratt; /* bitfield really */
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uint8_t reserved1[12];
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/** Read Recovery Levels Supported */
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uint16_t rrls;
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uint8_t reserved1[9];
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/** Controller Type */
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uint8_t cntrltype;
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/** FRU Globally Unique Identifier */
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uint8_t fguid[16];
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uint8_t reserved2[128];
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/** Command Retry Delay Time 1 */
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uint16_t crdt1;
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/** Command Retry Delay Time 2 */
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uint16_t crdt2;
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/** Command Retry Delay Time 3 */
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uint16_t crdt3;
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uint8_t reserved2[122];
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/* bytes 256-511: admin command set attributes */
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@ -878,7 +934,34 @@ struct nvme_controller_data {
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/** Sanitize Capabilities */
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uint32_t sanicap; /* Really a bitfield */
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uint8_t reserved3[180];
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/** Host Memory Buffer Minimum Descriptor Entry Size */
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uint32_t hmminds;
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/** Host Memory Maximum Descriptors Entries */
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uint16_t hmmaxd;
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/** NVM Set Identifier Maximum */
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uint16_t nsetidmax;
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/** Endurance Group Identifier Maximum */
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uint16_t endgidmax;
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/** ANA Transition Time */
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uint8_t anatt;
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/** Asymmetric Namespace Access Capabilities */
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uint8_t anacap;
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/** ANA Group Identifier Maximum */
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uint32_t anagrpmax;
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/** Number of ANA Group Identifiers */
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uint32_t nanagrpid;
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/** Persistent Event Log Size */
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uint32_t pels;
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uint8_t reserved3[156];
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/* bytes 512-703: nvm command set attributes */
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/** submission queue entry size */
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@ -913,7 +996,9 @@ struct nvme_controller_data {
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/** NVM Vendor Specific Command Configuration */
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uint8_t nvscc;
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uint8_t reserved5;
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/** Namespace Write Protection Capabilities */
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uint8_t nwpc;
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/** Atomic Compare & Write Unit */
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uint16_t acwu;
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@ -922,8 +1007,11 @@ struct nvme_controller_data {
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/** SGL Support */
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uint32_t sgls;
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/** Maximum Number of Allowed Namespaces */
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uint32_t mnan;
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/* bytes 540-767: Reserved */
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uint8_t reserved7[228];
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uint8_t reserved7[224];
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/** NVM Subsystem NVMe Qualified Name */
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uint8_t subnqn[256];
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@ -1008,8 +1096,38 @@ struct nvme_namespace_data {
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/** NVM Capacity */
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uint8_t nvmcap[16];
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/* bytes 64-103: Reserved */
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uint8_t reserved5[40];
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/** Namespace Preferred Write Granularity */
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uint16_t npwg;
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/** Namespace Preferred Write Alignment */
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uint16_t npwa;
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/** Namespace Preferred Deallocate Granularity */
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uint16_t npdg;
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/** Namespace Preferred Deallocate Alignment */
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uint16_t npda;
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/** Namespace Optimal Write Size */
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uint16_t nows;
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/* bytes 74-91: Reserved */
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uint8_t reserved5[18];
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/** ANA Group Identifier */
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uint32_t anagrpid;
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/* bytes 96-98: Reserved */
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uint8_t reserved6[3];
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/** Namespace Attributes */
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uint8_t nsattr;
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/** NVM Set Identifier */
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uint16_t nvmsetid;
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/** Endurance Group Identifier */
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uint16_t endgid;
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/** Namespace Globally Unique Identifier */
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uint8_t nguid[16];
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@ -1020,7 +1138,7 @@ struct nvme_namespace_data {
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/** lba format support */
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uint32_t lbaf[16];
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uint8_t reserved6[192];
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uint8_t reserved7[192];
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uint8_t vendor_specific[3712];
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} __packed __aligned(4);
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@ -1402,6 +1520,10 @@ void nvme_controller_data_swapbytes(struct nvme_controller_data *s)
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s->rtd3e = le32toh(s->rtd3e);
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s->oaes = le32toh(s->oaes);
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s->ctratt = le32toh(s->ctratt);
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s->rrls = le16toh(s->rrls);
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s->crdt1 = le16toh(s->crdt1);
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s->crdt2 = le16toh(s->crdt2);
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s->crdt3 = le16toh(s->crdt3);
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s->oacs = le16toh(s->oacs);
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s->wctemp = le16toh(s->wctemp);
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s->cctemp = le16toh(s->cctemp);
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@ -1415,6 +1537,13 @@ void nvme_controller_data_swapbytes(struct nvme_controller_data *s)
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s->mntmt = le16toh(s->mntmt);
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s->mxtmt = le16toh(s->mxtmt);
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s->sanicap = le32toh(s->sanicap);
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s->hmminds = le32toh(s->hmminds);
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s->hmmaxd = le16toh(s->hmmaxd);
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s->nsetidmax = le16toh(s->nsetidmax);
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s->endgidmax = le16toh(s->endgidmax);
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s->anagrpmax = le32toh(s->anagrpmax);
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s->nanagrpid = le32toh(s->nanagrpid);
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s->pels = le32toh(s->pels);
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s->maxcmd = le16toh(s->maxcmd);
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s->nn = le32toh(s->nn);
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s->oncs = le16toh(s->oncs);
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@ -1423,6 +1552,7 @@ void nvme_controller_data_swapbytes(struct nvme_controller_data *s)
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s->awupf = le16toh(s->awupf);
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s->acwu = le16toh(s->acwu);
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s->sgls = le32toh(s->sgls);
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s->mnan = le32toh(s->mnan);
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for (i = 0; i < 32; i++)
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nvme_power_state_swapbytes(&s->power_state[i]);
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}
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@ -1442,6 +1572,14 @@ void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s)
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s->nabo = le16toh(s->nabo);
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s->nabspf = le16toh(s->nabspf);
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s->noiob = le16toh(s->noiob);
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s->npwg = le16toh(s->npwg);
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s->npwa = le16toh(s->npwa);
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s->npdg = le16toh(s->npdg);
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s->npda = le16toh(s->npda);
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s->nows = le16toh(s->nows);
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s->anagrpid = le32toh(s->anagrpid);
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s->nvmsetid = le16toh(s->nvmsetid);
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s->endgid = le16toh(s->endgid);
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for (i = 0; i < 16; i++)
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s->lbaf[i] = le32toh(s->lbaf[i]);
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}
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