From 8e015fd886d70065bd9488acb4111055cd53fa9a Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Fri, 26 Apr 2013 05:42:35 +0000 Subject: [PATCH] Octeon 2 (6xxx) and newer CPUs don't use the clock CPU speed for its I/O clock. Thankfully, the simple executive provies a way to querry the proper clock that works on all models. Move to asking for the SCLK via this interface. This gets the serial console working after we start init and open the console and set the divisor (which turned the output from good to bad). I can login on the console now. --- sys/mips/cavium/uart_dev_oct16550.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/mips/cavium/uart_dev_oct16550.c b/sys/mips/cavium/uart_dev_oct16550.c index 06d0001e73d0..753559ff7a92 100644 --- a/sys/mips/cavium/uart_dev_oct16550.c +++ b/sys/mips/cavium/uart_dev_oct16550.c @@ -656,7 +656,7 @@ oct16550_bus_probe (struct uart_softc *sc) int error; bas = &sc->sc_bas; - bas->rclk = uart_oct16550_class.uc_rclk = cvmx_sysinfo_get()->cpu_clock_hz; + bas->rclk = uart_oct16550_class.uc_rclk = cvmx_clock_get_rate(CVMX_CLOCK_SCLK); error = oct16550_probe(bas); if (error) {