Handle mge(4) chip revision differences at run-time rather then compile time,
which is more flexible for future revisions, and lets eliminate some #defines and compile conditionals. Obtained from: Semihalf
This commit is contained in:
parent
2872efae88
commit
8e1dc58e8c
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=186892
@ -69,14 +69,11 @@ __FBSDID("$FreeBSD$");
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
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#define MGE_VER2 1
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#endif
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#define MV_PHY_ADDR_BASE 8
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#include <dev/mge/if_mgevar.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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#include "miibus_if.h"
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@ -103,6 +100,10 @@ static void mge_start_locked(struct ifnet *ifp);
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static void mge_watchdog(struct mge_softc *sc);
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static int mge_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
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static uint32_t mge_tfut_ipg(uint32_t val, int ver);
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static uint32_t mge_rx_ipg(uint32_t val, int ver);
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static void mge_ver_params(struct mge_softc *sc);
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static void mge_intrs_ctrl(struct mge_softc *sc, int enable);
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static void mge_intr_rx(void *arg);
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static void mge_intr_rx_locked(struct mge_softc *sc, int count);
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@ -206,6 +207,57 @@ mge_get_mac_address(struct mge_softc *sc, uint8_t *addr)
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addr[5] = (mac_l & 0x000000ff);
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}
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static uint32_t
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mge_tfut_ipg(uint32_t val, int ver)
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{
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switch (ver) {
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case 1:
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return ((val & 0x3fff) << 4);
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case 2:
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default:
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return ((val & 0xffff) << 4);
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}
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}
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static uint32_t
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mge_rx_ipg(uint32_t val, int ver)
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{
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switch (ver) {
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case 1:
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return ((val & 0x3fff) << 8);
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case 2:
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default:
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return (((val & 0x8000) << 10) | ((val & 0x7fff) << 7));
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}
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}
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static void
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mge_ver_params(struct mge_softc *sc)
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{
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uint32_t d, r;
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soc_id(&d, &r);
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if (d == MV_DEV_88F6281 || d == MV_DEV_MV78100) {
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sc->mge_ver = 2;
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sc->mge_mtu = 0x4e8;
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sc->mge_tfut_ipg_max = 0xFFFF;
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sc->mge_rx_ipg_max = 0xFFFF;
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sc->mge_tx_arb_cfg = 0xFC0000FF;
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sc->mge_tx_tok_cfg = 0xFFFF7FFF;
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sc->mge_tx_tok_cnt = 0x3FFFFFFF;
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} else {
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sc->mge_ver = 1;
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sc->mge_mtu = 0x458;
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sc->mge_tfut_ipg_max = 0x3FFF;
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sc->mge_rx_ipg_max = 0x3FFF;
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sc->mge_tx_arb_cfg = 0x000000FF;
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sc->mge_tx_tok_cfg = 0x3FFFFFFF;
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sc->mge_tx_tok_cnt = 0x3FFFFFFF;
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}
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}
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static void
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mge_set_mac_address(struct mge_softc *sc)
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{
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@ -564,6 +616,9 @@ mge_attach(device_t dev)
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if (device_get_unit(dev) == 0)
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sc_mge0 = sc;
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/* Set chip version-dependent parameters */
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mge_ver_params(sc);
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/* Initialize mutexes */
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mtx_init(&sc->transmit_lock, device_get_nameunit(dev), "mge TX lock", MTX_DEF);
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mtx_init(&sc->receive_lock, device_get_nameunit(dev), "mge RX lock", MTX_DEF);
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@ -797,23 +852,25 @@ mge_init_locked(void *arg)
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/* Setup multicast filters */
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mge_setup_multicast(sc);
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#if defined(MGE_VER2)
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MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL1, MGE_RGMII_EN);
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MGE_WRITE(sc, MGE_FIXED_PRIO_CONF, MGE_FIXED_PRIO_EN(0));
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#endif
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/* Initialize TX queue configuration registers */
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MGE_WRITE(sc, MGE_TX_TOKEN_COUNT(0), MGE_TX_TOKEN_Q0_DFLT);
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MGE_WRITE(sc, MGE_TX_TOKEN_CONF(0), MGE_TX_TOKEN_Q0_DFLT);
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MGE_WRITE(sc, MGE_TX_ARBITER_CONF(0), MGE_TX_ARB_Q0_DFLT);
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if (sc->mge_ver == 2) {
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MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL1, MGE_RGMII_EN);
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MGE_WRITE(sc, MGE_FIXED_PRIO_CONF, MGE_FIXED_PRIO_EN(0));
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}
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/* Initialize TX queue configuration registers */
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MGE_WRITE(sc, MGE_TX_TOKEN_COUNT(0), sc->mge_tx_tok_cnt);
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MGE_WRITE(sc, MGE_TX_TOKEN_CONF(0), sc->mge_tx_tok_cfg);
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MGE_WRITE(sc, MGE_TX_ARBITER_CONF(0), sc->mge_tx_arb_cfg);
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/* Clear TX queue configuration registers for unused queues */
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for (i = 1; i < 7; i++) {
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MGE_WRITE(sc, MGE_TX_TOKEN_COUNT(i), MGE_TX_TOKEN_Q1_7_DFLT);
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MGE_WRITE(sc, MGE_TX_TOKEN_CONF(i), MGE_TX_TOKEN_Q1_7_DFLT);
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MGE_WRITE(sc, MGE_TX_ARBITER_CONF(i), MGE_TX_ARB_Q1_7_DFLT);
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MGE_WRITE(sc, MGE_TX_TOKEN_COUNT(i), 0);
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MGE_WRITE(sc, MGE_TX_TOKEN_CONF(i), 0);
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MGE_WRITE(sc, MGE_TX_ARBITER_CONF(i), 0);
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}
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/* Set default MTU */
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MGE_WRITE(sc, MGE_MTU, MGE_MTU_DEFAULT);
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MGE_WRITE(sc, sc->mge_mtu, 0);
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/* Port configuration */
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MGE_WRITE(sc, MGE_PORT_CONFIG,
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@ -1688,12 +1745,12 @@ mge_set_rxic(struct mge_softc *sc)
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{
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uint32_t reg;
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if (sc->rx_ic_time > MGE_SDMA_RX_IPG_MAX)
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sc->rx_ic_time = MGE_SDMA_RX_IPG_MAX;
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if (sc->rx_ic_time > sc->mge_rx_ipg_max)
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sc->rx_ic_time = sc->mge_rx_ipg_max;
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reg = MGE_READ(sc, MGE_SDMA_CONFIG);
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reg &= ~MGE_SDMA_RX_IPG(MGE_SDMA_RX_IPG_MAX);
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reg |= MGE_SDMA_RX_IPG(sc->rx_ic_time);
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reg &= ~mge_rx_ipg(sc->mge_rx_ipg_max, sc->mge_ver);
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reg |= mge_rx_ipg(sc->rx_ic_time, sc->mge_ver);
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MGE_WRITE(sc, MGE_SDMA_CONFIG, reg);
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}
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@ -1702,12 +1759,12 @@ mge_set_txic(struct mge_softc *sc)
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{
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uint32_t reg;
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if (sc->tx_ic_time > MGE_TX_FIFO_URGENT_TRSH_IPG_MAX)
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sc->tx_ic_time = MGE_TX_FIFO_URGENT_TRSH_IPG_MAX;
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if (sc->tx_ic_time > sc->mge_tfut_ipg_max)
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sc->tx_ic_time = sc->mge_tfut_ipg_max;
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reg = MGE_READ(sc, MGE_TX_FIFO_URGENT_TRSH);
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reg &= ~MGE_TX_FIFO_URGENT_TRSH_IPG(MGE_TX_FIFO_URGENT_TRSH_IPG_MAX);
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reg |= MGE_TX_FIFO_URGENT_TRSH_IPG(sc->tx_ic_time);
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reg &= ~mge_tfut_ipg(sc->mge_tfut_ipg_max, sc->mge_ver);
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reg |= mge_tfut_ipg(sc->tx_ic_time, sc->mge_ver);
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MGE_WRITE(sc, MGE_TX_FIFO_URGENT_TRSH, reg);
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}
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@ -1715,9 +1772,10 @@ static int
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mge_sysctl_ic(SYSCTL_HANDLER_ARGS)
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{
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struct mge_softc *sc = (struct mge_softc *)arg1;
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uint32_t time = (arg2 == MGE_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
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uint32_t time;
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int error;
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time = (arg2 == MGE_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
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error = sysctl_handle_int(oidp, &time, 0, req);
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if (error != 0)
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return(error);
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@ -91,6 +91,14 @@ struct mge_softc {
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uint32_t tx_ic_time;
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struct mge_desc_wrapper mge_tx_desc[MGE_TX_DESC_NUM];
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struct mge_desc_wrapper mge_rx_desc[MGE_RX_DESC_NUM];
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uint32_t mge_tfut_ipg_max; /* TX FIFO Urgent Threshold */
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uint32_t mge_rx_ipg_max;
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uint32_t mge_tx_arb_cfg;
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uint32_t mge_tx_tok_cfg;
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uint32_t mge_tx_tok_cnt;
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uint16_t mge_mtu;
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int mge_ver;
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};
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@ -183,15 +191,6 @@ struct mge_softc {
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#define MGE_SDMA_RX_BYTE_SWAP (1 << 4)
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#define MGE_SDMA_TX_BYTE_SWAP (1 << 5)
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#define MGE_SDMA_DESC_SWAP_MODE (1 << 6)
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#if defined(MGE_VER2)
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#define MGE_SDMA_RX_IPG_MAX 0xFFFF
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#define MGE_SDMA_RX_IPG(val) ((((val) & 0x8000) << 10) | \
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(((val) & 0x7fff) << 7))
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#else
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#define MGE_SDMA_RX_IPG_MAX 0x3FFF
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#define MGE_SDMA_RX_IPG(val) (((val) & 0x3fff) << 8)
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#endif
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#define MGE_PORT_SERIAL_CTRL 0x43c
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#define PORT_SERIAL_ENABLE (1 << 0) /* serial port enable */
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@ -248,13 +247,6 @@ struct mge_softc {
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#define MGE_COLLISION_LIMIT(val) (((val) & 0x3f) << 16)
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#define MGE_DROP_ODD_PREAMBLE (1 << 22)
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#if defined(MGE_VER2)
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#define MGE_MTU 0x4e8
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#else
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#define MGE_MTU 0x458
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#endif
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#define MGE_MTU_DEFAULT 0x0
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#define MGE_PORT_INT_CAUSE 0x460
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#define MGE_PORT_INT_MASK 0x468
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#define MGE_PORT_INT_RX (1 << 0)
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@ -277,13 +269,6 @@ struct mge_softc {
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#define MGE_RX_FIFO_URGENT_TRSH 0x470
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#define MGE_TX_FIFO_URGENT_TRSH 0x474
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#if defined(MGE_VER2)
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#define MGE_TX_FIFO_URGENT_TRSH_IPG_MAX 0xFFFF
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#define MGE_TX_FIFO_URGENT_TRSH_IPG(vl) (((vl) & 0xFFFF) << 4)
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#else
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#define MGE_TX_FIFO_URGENT_TRSH_IPG_MAX 0x3FFF
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#define MGE_TX_FIFO_URGENT_TRSH_IPG(vl) (((vl) & 0x3FFF) << 4)
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#endif
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#define MGE_FIXED_PRIO_CONF 0x4dc
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#define MGE_FIXED_PRIO_EN(q) (1 << (q))
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@ -300,12 +285,7 @@ struct mge_softc {
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#define MGE_TX_TOKEN_COUNT(q) (0x700 + ((q)<<4))
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#define MGE_TX_TOKEN_CONF(q) (0x704 + ((q)<<4))
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#define MGE_TX_TOKEN_Q0_DFLT 0x3fffffff
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#define MGE_TX_TOKEN_Q1_7_DFLT 0x0
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#define MGE_TX_ARBITER_CONF(q) (0x704 + ((q)<<4))
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#define MGE_TX_ARB_Q0_DFLT 0xff
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#define MGE_TX_ARB_Q1_7_DFLT 0x0
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#define MGE_MCAST_REG_NUMBER 64
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#define MGE_DA_FILTER_SPEC_MCAST(i) (0x1400 + ((i) << 2))
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