Disable 'C'-compressed ISA extension.
It works excellent, but KDB disassembler and DTrace FBT provider for RISC-V do lack support for it. They currently handle 4-byte instructions only, while C-compressed ISA extension introduces 2-byte instructions freely mixing them together. So disable it for now. Reviewed by: markj@ Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D16436
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=336716
@ -367,9 +367,9 @@ CFLAGS += -mcpu=8540 -Wa,-me500 -mspe=yes -mabi=spe -mfloat-gprs=double
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.if ${MACHINE_CPUARCH} == "riscv"
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.if ${MACHINE_CPUARCH} == "riscv"
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.if ${MACHINE_ARCH:Mriscv*sf}
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.if ${MACHINE_ARCH:Mriscv*sf}
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CFLAGS += -march=rv64imac -mabi=lp64
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CFLAGS += -march=rv64ima -mabi=lp64
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.else
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.else
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CFLAGS += -march=rv64imafdc -mabi=lp64d
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CFLAGS += -march=rv64imafd -mabi=lp64d
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.endif
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.endif
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.endif
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.endif
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@ -103,7 +103,7 @@ CFLAGS+= -ffreestanding ${CFLAGS_NO_SIMD}
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.if ${MACHINE_CPUARCH} == "aarch64"
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.if ${MACHINE_CPUARCH} == "aarch64"
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CFLAGS+= -mgeneral-regs-only -fPIC
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CFLAGS+= -mgeneral-regs-only -fPIC
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.elif ${MACHINE_CPUARCH} == "riscv"
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.elif ${MACHINE_CPUARCH} == "riscv"
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CFLAGS+= -march=rv64imac -mabi=lp64
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CFLAGS+= -march=rv64ima -mabi=lp64
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.else
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.else
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CFLAGS+= -msoft-float
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CFLAGS+= -msoft-float
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.endif
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.endif
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@ -131,7 +131,7 @@ INLINE_LIMIT?= 8000
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.endif
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.endif
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.if ${MACHINE_CPUARCH} == "riscv"
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.if ${MACHINE_CPUARCH} == "riscv"
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CFLAGS.gcc+= -mcmodel=medany -march=rv64imafdc -mabi=lp64
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CFLAGS.gcc+= -mcmodel=medany -march=rv64imafd -mabi=lp64
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INLINE_LIMIT?= 8000
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INLINE_LIMIT?= 8000
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.endif
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.endif
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