Adds the first files from the RMI work with my re-work of their
intr_machdep.c to use updated interfaces etc. More coming.. and some day it may compile ;-)
This commit is contained in:
Randall Stewart
parent
3f907e3338
commit
8f28855b07
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/mips/; revision=198155
24
sys/mips/rmi/files.xlr
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24
sys/mips/rmi/files.xlr
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@ -0,0 +1,24 @@
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# $FreeBSD$
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mips/rmi/xlr_boot1_console.c standard
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mips/rmi/xlr_machdep.c standard
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#mips/rmi/clock.c standard
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mips/rmi/iodi.c standard
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mips/rmi/msgring.c standard
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mips/rmi/msgring_xls.c standard
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mips/rmi/board.c standard
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mips/rmi/on_chip.c standard
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mips/rmip/intr_machdep.c standard
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mips/rmi/xlr_i2c.c optional iic
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mips/rmi/uart_bus_xlr_iodi.c optional uart
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mips/rmi/uart_cpu_mips_xlr.c optional uart
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mips/rmi/perfmon_kern.c optional xlr_perfmon
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mips/rmi/perfmon_percpu.c optional xlr_perfmon
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mips/rmi/pcibus.c optional pci
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mips/rmi/xlr_pci.c optional pci
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mips/rmi/xls_ehci.c optional usb ehci
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dev/rmi/xlr/rge.c optional rge
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dev/iicbus/xlr_rtc.c optional xlr_rtc
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dev/iicbus/xlr_temperature.c optional xlr_temperature
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dev/iicbus/xlr_eeprom.c optional xlr_eeprom
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dev/rmi/sec/rmisec.c optional rmisec
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dev/rmi/sec/rmilib.c optional rmisec
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175
sys/mips/rmi/intr_machdep.c
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175
sys/mips/rmi/intr_machdep.c
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/*-
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* Copyright (c) 2006 Fill this file and put your name here
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* Copyright (c) 2002-2004 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/kernel.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/cpuinfo.h>
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#include <machine/cpuregs.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/trap.h>
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#include <machine/hwfunc.h>
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#include <machine/intrcnt.h>
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struct mips_intrhand mips_intr_handlers[XLR_MAX_INTR];
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static void
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mips_mask_hard_irq(void *source)
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{
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uintptr_t irq = (uintptr_t)source;
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write_c0_eimr64(read_c0_eimr64() & ~(1ULL<<irq));
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}
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static void
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mips_unmask_hard_irq(void *source)
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{
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uintptr_t irq = (uintptr_t)source;
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write_c0_eimr64(read_c0_eimr64() | (1ULL<<irq));
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}
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void
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cpu_establish_hardintr(const char *name, driver_filter_t *filt,
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void (*handler)(void*), void *arg, int irq, int flags, void **cookiep)
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{
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struct mips_intrhand *mih; /* descriptor for the IRQ */
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struct intr_event *ie; /* descriptor for the IRQ */
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int errcode;
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if (intr < 0 || intr > XLR_MAX_INTR)
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panic("%s called for unknown hard intr %d", __func__, intr);
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/* FIXME locking - not needed now, because we do this only on startup from
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CPU0 */
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mih = &mips_intr_handlers[irq];
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mih->cntp = &intrcnt[irq];
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ie = mih->mih_event;
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if (ie == NULL) {
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errcode = intr_event_create(&event, (void *)(uintptr_t)irq, 0,
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irq, mips_mask_hard_irq, mips_unmask_hard_irq,
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NULL, NULL, "hard intr%d:", irq);
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if (errcode) {
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printf("Could not create event for intr %d\n", irq);
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return;
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}
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}
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intr_event_add_handler(event, name, filt, handler, arg,
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intr_priority(flags), flags, cookiep);
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mih->mih_event = ie;
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mips_unmask_hard_irq((void*)(uintptr_t)irq);
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}
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void
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cpu_establish_softintr(const char *name, driver_filter_t *filt,
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void (*handler)(void*), void *arg, int irq, int flags,
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void **cookiep)
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{
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/* we don't separate them into soft/hard like other mips */
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cpu_establish_hardintr(name, filt, handler, arg, intr, flags, cookiep);
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}
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void
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cpu_intr(struct trapframe *tf)
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{
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struct mips_intrhand *mih;
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struct intr_handler *ih;
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struct intr_event *ie;
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register_t eirr;
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int i, thread, error;
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critical_enter();
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eirr = read_c0_eirr64();
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if (eirr == 0) {
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critical_exit();
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return;
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}
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/* No need to clear the EIRR here. the handler is gonna
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* write to compare which clears eirr also
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*/
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if (eirr & (1 << IRQ_TIMER)) {
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count_compare_clockhandler(tf);
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critical_exit();
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return;
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}
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/* FIXME sched pin >? LOCK>? */
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for(i = sizeof(eirr)*8 - 1; i>=0; i--) {
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if ((eirr & 1ULL<<i) == 0)
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continue;
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#ifdef SMP
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/* These are reserved interrupts */
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if((i == IPI_AST) || (i == IPI_RENDEZVOUS) || (i == IPI_STOP)
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|| (i == IPI_SMP_CALL_FUNCTION)) {
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write_c0_eirr64(1ULL << i);
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pic_ack(i);
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smp_handle_ipi(tf, i);
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pic_delayed_ack(i);
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continue;
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}
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#ifdef XLR_PERFMON
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if (i == IPI_PERFMON) {
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write_c0_eirr64(1ULL << i);
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pic_ack(i);
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xlr_perfmon_sampler(NULL);
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pic_delayed_ack(i);
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continue;
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}
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#endif
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#endif
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mih = &mips_intr_handlers[i];
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atomic_add_long(mih->cntp, 1);
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ie = mih->mih_event;
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write_c0_eirr64(1ULL << i);
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if (!ie || TAILQ_EMPTY(&ie->ie_handlers)) {
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printf("stray interrupt %d\n", i);
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continue;
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}
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if (intr_event_handle(ie, tf) != 0) {
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printf("stray %s interrupt %d\n",
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hard ? "hard" : "soft", i);
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}
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}
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critical_exit();
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}
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10
sys/mips/rmi/std.xlr
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10
sys/mips/rmi/std.xlr
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@ -0,0 +1,10 @@
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# $FreeBSD$
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files "../xlr/files.xlr"
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#
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# XXXMIPS: It's a stub, isn't it?
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#
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cpu CPU_MIPSXLR
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option NOFPU
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# Kludge for now
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options TARGET_XLR_XLS
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