PowerNV: XICS support for PowerNV/OPAL
Make XICS to be OPAL-aware. Created by: Nathan Whitehorn <nwhitehorn@freebsd.org> Submitted by: Wojciech Macek <wma@semihalf.com> Sponsored by: FreeBSD Foundation
This commit is contained in:
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cf47945d85
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8fc8068eba
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=328042
@ -23,7 +23,7 @@ MPC85XX opt_platform.h
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POWERMAC opt_platform.h
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PS3 opt_platform.h
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MAMBO
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POWERNV
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POWERNV opt_platform.h
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PSERIES
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PSIM
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@ -31,7 +31,7 @@ options POWERMAC #NewWorld Apple PowerMacs
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options PS3 #Sony Playstation 3
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options MAMBO #IBM Mambo Full System Simulator
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options PSERIES #PAPR-compliant systems (e.g. IBM p)
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options POWERNV #Non-virtualized OpenPOWER systems
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options POWERNV #Non-virtualized OpenPOWER systems
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options FDT #Flattened Device Tree
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options SCHED_ULE #ULE scheduler
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@ -59,6 +59,8 @@ int opal_call(uint64_t token, ...);
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#define OPAL_PCI_SET_XIVE_PE 37
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#define OPAL_PCI_RESET 49
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#define OPAL_PCI_POLL 62
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#define OPAL_SET_XIVE 19
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#define OPAL_GET_XIVE 20
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#define OPAL_PCI_SET_PE 31
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#define OPAL_GET_MSI_32 39
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#define OPAL_GET_MSI_64 40
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@ -28,6 +28,8 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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@ -48,6 +50,10 @@ __FBSDID("$FreeBSD$");
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#ifdef POWERNV
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#include <powerpc/powernv/opal.h>
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#endif
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#include "phyp-hvcall.h"
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#include "pic_if.h"
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@ -82,7 +88,7 @@ static device_method_t xicp_methods[] = {
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DEVMETHOD(pic_mask, xicp_mask),
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DEVMETHOD(pic_unmask, xicp_unmask),
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{ 0, 0 },
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DEVMETHOD_END
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};
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static device_method_t xics_methods[] = {
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@ -90,11 +96,14 @@ static device_method_t xics_methods[] = {
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DEVMETHOD(device_probe, xics_probe),
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DEVMETHOD(device_attach, xics_attach),
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{ 0, 0 },
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DEVMETHOD_END
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};
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struct xicp_softc {
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struct mtx sc_mtx;
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struct resource *mem[MAXCPU];
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int cpu_range[2];
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int ibm_int_on;
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int ibm_int_off;
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@ -105,6 +114,7 @@ struct xicp_softc {
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struct {
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int irq;
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int vector;
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int cpu;
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} intvecs[256];
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int nintvecs;
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};
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@ -129,31 +139,43 @@ EARLY_DRIVER_MODULE(xicp, ofwbus, xicp_driver, xicp_devclass, 0, 0,
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EARLY_DRIVER_MODULE(xics, ofwbus, xics_driver, xics_devclass, 0, 0,
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BUS_PASS_INTERRUPT);
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#ifdef POWERNV
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static struct resource *
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xicp_mem_for_cpu(int cpu)
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{
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device_t dev;
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struct xicp_softc *sc;
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int i;
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for (i = 0; (dev = devclass_get_device(xicp_devclass, i)) != NULL; i++){
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sc = device_get_softc(dev);
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if (cpu >= sc->cpu_range[0] && cpu < sc->cpu_range[1])
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return (sc->mem[cpu - sc->cpu_range[0]]);
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}
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return (NULL);
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}
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#endif
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static int
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xicp_probe(device_t dev)
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{
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if (ofw_bus_get_name(dev) == NULL || strcmp(ofw_bus_get_name(dev),
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"interrupt-controller") != 0)
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "ibm,ppc-xicp"))
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return (ENXIO);
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device_set_desc(dev, "PAPR virtual interrupt controller");
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device_set_desc(dev, "External Interrupt Presentation Controller");
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return (BUS_PROBE_GENERIC);
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}
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static int
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xics_probe(device_t dev)
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{
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if (ofw_bus_get_name(dev) == NULL || strcmp(ofw_bus_get_name(dev),
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"interrupt-controller") != 0)
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "ibm,ppc-xics"))
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return (ENXIO);
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device_set_desc(dev, "PAPR virtual interrupt source");
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device_set_desc(dev, "External Interrupt Source Controller");
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return (BUS_PROBE_GENERIC);
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}
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@ -163,14 +185,54 @@ xicp_attach(device_t dev)
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struct xicp_softc *sc = device_get_softc(dev);
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phandle_t phandle = ofw_bus_get_node(dev);
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if (rtas_exists()) {
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sc->ibm_int_on = rtas_token_lookup("ibm,int-on");
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sc->ibm_int_off = rtas_token_lookup("ibm,int-off");
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sc->ibm_set_xive = rtas_token_lookup("ibm,set-xive");
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sc->ibm_get_xive = rtas_token_lookup("ibm,get-xive");
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#ifdef POWERNV
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} else if (opal_check() == 0) {
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/* No init needed */
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#endif
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} else {
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device_printf(dev, "Cannot attach without RTAS or OPAL\n");
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return (ENXIO);
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}
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if (OF_hasprop(phandle, "ibm,interrupt-server-ranges")) {
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OF_getencprop(phandle, "ibm,interrupt-server-ranges",
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sc->cpu_range, sizeof(sc->cpu_range));
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sc->cpu_range[1] += sc->cpu_range[0];
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device_printf(dev, "Handling CPUs %d-%d\n", sc->cpu_range[0],
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sc->cpu_range[1]-1);
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} else {
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sc->cpu_range[0] = 0;
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sc->cpu_range[1] = mp_ncpus;
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}
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#ifdef POWERNV
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if (mfmsr() & PSL_HV) {
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int i;
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for (i = 0; i < sc->cpu_range[1] - sc->cpu_range[0]; i++) {
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sc->mem[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&i, RF_ACTIVE);
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if (sc->mem[i] == NULL) {
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device_printf(dev, "Could not alloc mem "
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"resource %d\n", i);
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return (ENXIO);
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}
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/* Unmask interrupts on all cores */
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bus_write_1(sc->mem[i], 4, 0xff);
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bus_write_1(sc->mem[i], 12, 0xff);
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}
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}
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#endif
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mtx_init(&sc->sc_mtx, "XICP", NULL, MTX_DEF);
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sc->nintvecs = 0;
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sc->ibm_int_on = rtas_token_lookup("ibm,int-on");
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sc->ibm_int_off = rtas_token_lookup("ibm,int-off");
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sc->ibm_set_xive = rtas_token_lookup("ibm,set-xive");
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sc->ibm_get_xive = rtas_token_lookup("ibm,get-xive");
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powerpc_register_pic(dev, OF_xref_from_node(phandle), MAX_XICP_IRQS,
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1 /* Number of IPIs */, FALSE);
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root_pic = dev;
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@ -219,9 +281,23 @@ xicp_bind(device_t dev, u_int irq, cpuset_t cpumask)
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ncpus++;
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}
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/* XXX: super inefficient */
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for (i = 0; i < sc->nintvecs; i++) {
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if (sc->intvecs[i].irq == irq) {
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sc->intvecs[i].cpu = cpu;
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break;
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}
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}
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KASSERT(i < sc->nintvecs, ("Binding non-configured interrupt"));
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if (rtas_exists())
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error = rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
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XICP_PRIORITY, &status);
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#ifdef POWERNV
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else
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error = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
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#endif
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error = rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
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XICP_PRIORITY, &status);
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if (error < 0)
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panic("Cannot bind interrupt %d to CPU %d", irq, cpu);
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}
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@ -230,23 +306,45 @@ static void
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xicp_dispatch(device_t dev, struct trapframe *tf)
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{
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struct xicp_softc *sc;
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struct resource *regs = NULL;
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uint64_t xirr, junk;
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int i;
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#ifdef POWERNV
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if (mfmsr() & PSL_HV) {
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regs = xicp_mem_for_cpu(PCPU_GET(cpuid));
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KASSERT(regs != NULL,
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("Can't find regs for CPU %d", PCPU_GET(cpuid)));
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}
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#endif
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sc = device_get_softc(dev);
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for (;;) {
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/* Return value in R4, use the PFT call */
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phyp_pft_hcall(H_XIRR, 0, 0, 0, 0, &xirr, &junk, &junk);
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if (regs) {
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xirr = bus_read_4(regs, 4);
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} else {
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/* Return value in R4, use the PFT call */
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phyp_pft_hcall(H_XIRR, 0, 0, 0, 0, &xirr, &junk, &junk);
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}
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xirr &= 0x00ffffff;
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if (xirr == 0) { /* No more pending interrupts? */
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phyp_hcall(H_CPPR, (uint64_t)0xff);
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if (regs)
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bus_write_1(regs, 4, 0xff);
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else
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phyp_hcall(H_CPPR, (uint64_t)0xff);
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break;
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}
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if (xirr == XICP_IPI) { /* Magic number for IPIs */
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xirr = MAX_XICP_IRQS; /* Map to FreeBSD magic */
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phyp_hcall(H_IPI, (uint64_t)(PCPU_GET(cpuid)),
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0xff); /* Clear IPI */
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/* Clear IPI */
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if (regs)
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bus_write_1(regs, 12, 0xff);
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else
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phyp_hcall(H_IPI, (uint64_t)(PCPU_GET(cpuid)),
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0xff);
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}
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/* XXX: super inefficient */
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@ -271,9 +369,13 @@ xicp_enable(device_t dev, u_int irq, u_int vector)
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KASSERT(sc->nintvecs + 1 < nitems(sc->intvecs),
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("Too many XICP interrupts"));
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/* Bind to this CPU to start: distrib. ID is last entry in gserver# */
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cpu = PCPU_GET(cpuid);
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mtx_lock(&sc->sc_mtx);
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sc->intvecs[sc->nintvecs].irq = irq;
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sc->intvecs[sc->nintvecs].vector = vector;
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sc->intvecs[sc->nintvecs].cpu = cpu;
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mb();
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sc->nintvecs++;
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mtx_unlock(&sc->sc_mtx);
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@ -282,11 +384,20 @@ xicp_enable(device_t dev, u_int irq, u_int vector)
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if (irq == MAX_XICP_IRQS)
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return;
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/* Bind to this CPU to start: distrib. ID is last entry in gserver# */
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cpu = PCPU_GET(cpuid);
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rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu, XICP_PRIORITY,
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&status);
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xicp_unmask(dev, irq);
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if (rtas_exists()) {
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rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
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XICP_PRIORITY, &status);
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xicp_unmask(dev, irq);
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#ifdef POWERNV
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} else {
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status = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
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/* Unmask implicit for OPAL */
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if (status != 0)
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panic("OPAL_SET_XIVE IRQ %d -> cpu %d failed: %d", irq,
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cpu, status);
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#endif
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}
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}
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static void
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@ -298,14 +409,24 @@ xicp_eoi(device_t dev, u_int irq)
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irq = XICP_IPI;
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xirr = irq | (XICP_PRIORITY << 24);
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phyp_hcall(H_EOI, xirr);
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#ifdef POWERNV
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if (mfmsr() & PSL_HV)
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bus_write_4(xicp_mem_for_cpu(PCPU_GET(cpuid)), 4, xirr);
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else
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#endif
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phyp_hcall(H_EOI, xirr);
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}
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static void
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xicp_ipi(device_t dev, u_int cpu)
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{
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phyp_hcall(H_IPI, (uint64_t)cpu, XICP_PRIORITY);
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#ifdef POWERNV
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if (mfmsr() & PSL_HV)
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bus_write_1(xicp_mem_for_cpu(cpu), 12, XICP_PRIORITY);
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else
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#endif
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phyp_hcall(H_IPI, (uint64_t)cpu, XICP_PRIORITY);
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}
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static void
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@ -317,7 +438,21 @@ xicp_mask(device_t dev, u_int irq)
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if (irq == MAX_XICP_IRQS)
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return;
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rtas_call_method(sc->ibm_int_off, 1, 1, irq, &status);
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if (rtas_exists()) {
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rtas_call_method(sc->ibm_int_off, 1, 1, irq, &status);
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#ifdef POWERNV
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} else {
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int i;
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for (i = 0; i < sc->nintvecs; i++) {
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if (sc->intvecs[i].irq == irq) {
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break;
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}
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}
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KASSERT(i < sc->nintvecs, ("Masking unconfigured interrupt"));
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opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2, 0xff);
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#endif
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}
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}
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static void
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@ -329,6 +464,21 @@ xicp_unmask(device_t dev, u_int irq)
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if (irq == MAX_XICP_IRQS)
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return;
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rtas_call_method(sc->ibm_int_on, 1, 1, irq, &status);
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if (rtas_exists()) {
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rtas_call_method(sc->ibm_int_on, 1, 1, irq, &status);
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#ifdef POWERNV
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} else {
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int i;
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for (i = 0; i < sc->nintvecs; i++) {
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if (sc->intvecs[i].irq == irq) {
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break;
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}
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}
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KASSERT(i < sc->nintvecs, ("Unmasking unconfigured interrupt"));
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opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2,
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XICP_PRIORITY);
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#endif
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}
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}
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