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PowerNV: XICS support for PowerNV/OPAL

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Make XICS to be OPAL-aware.

Created by:            Nathan Whitehorn <nwhitehorn@freebsd.org>
Submitted by:          Wojciech Macek <wma@semihalf.com>
Sponsored by:          FreeBSD Foundation
This commit is contained in:
Wojciech Macek 2018-01-16 06:24:19 +00:00
parent cf47945d85
commit 8fc8068eba
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=328042
4 changed files with 184 additions and 32 deletions
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2
sys/conf/options.powerpc
View File

@ -23,7 +23,7 @@ MPC85XX opt_platform.h
POWERMAC opt_platform.h
PS3 opt_platform.h
MAMBO
POWERNV
POWERNV opt_platform.h
PSERIES
PSIM

2
sys/powerpc/conf/GENERIC64
View File

@ -31,7 +31,7 @@ options POWERMAC #NewWorld Apple PowerMacs
options PS3 #Sony Playstation 3
options MAMBO #IBM Mambo Full System Simulator
options PSERIES #PAPR-compliant systems (e.g. IBM p)
options POWERNV #Non-virtualized OpenPOWER systems
options POWERNV #Non-virtualized OpenPOWER systems
options FDT #Flattened Device Tree
options SCHED_ULE #ULE scheduler

2
sys/powerpc/powernv/opal.h
View File

@ -59,6 +59,8 @@ int opal_call(uint64_t token, ...);
#define OPAL_PCI_SET_XIVE_PE 37
#define OPAL_PCI_RESET 49
#define OPAL_PCI_POLL 62
#define OPAL_SET_XIVE 19
#define OPAL_GET_XIVE 20
#define OPAL_PCI_SET_PE 31
#define OPAL_GET_MSI_32 39
#define OPAL_GET_MSI_64 40

210
sys/powerpc/pseries/xics.c
View File

@ -28,6 +28,8 @@
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_platform.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/module.h>
@ -48,6 +50,10 @@ __FBSDID("$FreeBSD$");
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#ifdef POWERNV
#include <powerpc/powernv/opal.h>
#endif
#include "phyp-hvcall.h"
#include "pic_if.h"
@ -82,7 +88,7 @@ static device_method_t xicp_methods[] = {
DEVMETHOD(pic_mask, xicp_mask),
DEVMETHOD(pic_unmask, xicp_unmask),
{ 0, 0 },
DEVMETHOD_END
};
static device_method_t xics_methods[] = {
@ -90,11 +96,14 @@ static device_method_t xics_methods[] = {
DEVMETHOD(device_probe, xics_probe),
DEVMETHOD(device_attach, xics_attach),
{ 0, 0 },
DEVMETHOD_END
};
struct xicp_softc {
struct mtx sc_mtx;
struct resource *mem[MAXCPU];
int cpu_range[2];
int ibm_int_on;
int ibm_int_off;
@ -105,6 +114,7 @@ struct xicp_softc {
struct {
int irq;
int vector;
int cpu;
} intvecs[256];
int nintvecs;
};
@ -129,31 +139,43 @@ EARLY_DRIVER_MODULE(xicp, ofwbus, xicp_driver, xicp_devclass, 0, 0,
EARLY_DRIVER_MODULE(xics, ofwbus, xics_driver, xics_devclass, 0, 0,
BUS_PASS_INTERRUPT);
#ifdef POWERNV
static struct resource *
xicp_mem_for_cpu(int cpu)
{
device_t dev;
struct xicp_softc *sc;
int i;
for (i = 0; (dev = devclass_get_device(xicp_devclass, i)) != NULL; i++){
sc = device_get_softc(dev);
if (cpu >= sc->cpu_range[0] && cpu < sc->cpu_range[1])
return (sc->mem[cpu - sc->cpu_range[0]]);
}
return (NULL);
}
#endif
static int
xicp_probe(device_t dev)
{
if (ofw_bus_get_name(dev) == NULL || strcmp(ofw_bus_get_name(dev),
"interrupt-controller") != 0)
return (ENXIO);
if (!ofw_bus_is_compatible(dev, "ibm,ppc-xicp"))
return (ENXIO);
device_set_desc(dev, "PAPR virtual interrupt controller");
device_set_desc(dev, "External Interrupt Presentation Controller");
return (BUS_PROBE_GENERIC);
}
static int
xics_probe(device_t dev)
{
if (ofw_bus_get_name(dev) == NULL || strcmp(ofw_bus_get_name(dev),
"interrupt-controller") != 0)
return (ENXIO);
if (!ofw_bus_is_compatible(dev, "ibm,ppc-xics"))
return (ENXIO);
device_set_desc(dev, "PAPR virtual interrupt source");
device_set_desc(dev, "External Interrupt Source Controller");
return (BUS_PROBE_GENERIC);
}
@ -163,14 +185,54 @@ xicp_attach(device_t dev)
struct xicp_softc *sc = device_get_softc(dev);
phandle_t phandle = ofw_bus_get_node(dev);
if (rtas_exists()) {
sc->ibm_int_on = rtas_token_lookup("ibm,int-on");
sc->ibm_int_off = rtas_token_lookup("ibm,int-off");
sc->ibm_set_xive = rtas_token_lookup("ibm,set-xive");
sc->ibm_get_xive = rtas_token_lookup("ibm,get-xive");
#ifdef POWERNV
} else if (opal_check() == 0) {
/* No init needed */
#endif
} else {
device_printf(dev, "Cannot attach without RTAS or OPAL\n");
return (ENXIO);
}
if (OF_hasprop(phandle, "ibm,interrupt-server-ranges")) {
OF_getencprop(phandle, "ibm,interrupt-server-ranges",
sc->cpu_range, sizeof(sc->cpu_range));
sc->cpu_range[1] += sc->cpu_range[0];
device_printf(dev, "Handling CPUs %d-%d\n", sc->cpu_range[0],
sc->cpu_range[1]-1);
} else {
sc->cpu_range[0] = 0;
sc->cpu_range[1] = mp_ncpus;
}
#ifdef POWERNV
if (mfmsr() & PSL_HV) {
int i;
for (i = 0; i < sc->cpu_range[1] - sc->cpu_range[0]; i++) {
sc->mem[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&i, RF_ACTIVE);
if (sc->mem[i] == NULL) {
device_printf(dev, "Could not alloc mem "
"resource %d\n", i);
return (ENXIO);
}
/* Unmask interrupts on all cores */
bus_write_1(sc->mem[i], 4, 0xff);
bus_write_1(sc->mem[i], 12, 0xff);
}
}
#endif
mtx_init(&sc->sc_mtx, "XICP", NULL, MTX_DEF);
sc->nintvecs = 0;
sc->ibm_int_on = rtas_token_lookup("ibm,int-on");
sc->ibm_int_off = rtas_token_lookup("ibm,int-off");
sc->ibm_set_xive = rtas_token_lookup("ibm,set-xive");
sc->ibm_get_xive = rtas_token_lookup("ibm,get-xive");
powerpc_register_pic(dev, OF_xref_from_node(phandle), MAX_XICP_IRQS,
1 /* Number of IPIs */, FALSE);
root_pic = dev;
@ -219,9 +281,23 @@ xicp_bind(device_t dev, u_int irq, cpuset_t cpumask)
ncpus++;
}
/* XXX: super inefficient */
for (i = 0; i < sc->nintvecs; i++) {
if (sc->intvecs[i].irq == irq) {
sc->intvecs[i].cpu = cpu;
break;
}
}
KASSERT(i < sc->nintvecs, ("Binding non-configured interrupt"));
if (rtas_exists())
error = rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
XICP_PRIORITY, &status);
#ifdef POWERNV
else
error = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
#endif
error = rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
XICP_PRIORITY, &status);
if (error < 0)
panic("Cannot bind interrupt %d to CPU %d", irq, cpu);
}
@ -230,23 +306,45 @@ static void
xicp_dispatch(device_t dev, struct trapframe *tf)
{
struct xicp_softc *sc;
struct resource *regs = NULL;
uint64_t xirr, junk;
int i;
#ifdef POWERNV
if (mfmsr() & PSL_HV) {
regs = xicp_mem_for_cpu(PCPU_GET(cpuid));
KASSERT(regs != NULL,
("Can't find regs for CPU %d", PCPU_GET(cpuid)));
}
#endif
sc = device_get_softc(dev);
for (;;) {
/* Return value in R4, use the PFT call */
phyp_pft_hcall(H_XIRR, 0, 0, 0, 0, &xirr, &junk, &junk);
if (regs) {
xirr = bus_read_4(regs, 4);
} else {
/* Return value in R4, use the PFT call */
phyp_pft_hcall(H_XIRR, 0, 0, 0, 0, &xirr, &junk, &junk);
}
xirr &= 0x00ffffff;
if (xirr == 0) { /* No more pending interrupts? */
phyp_hcall(H_CPPR, (uint64_t)0xff);
if (regs)
bus_write_1(regs, 4, 0xff);
else
phyp_hcall(H_CPPR, (uint64_t)0xff);
break;
}
if (xirr == XICP_IPI) { /* Magic number for IPIs */
xirr = MAX_XICP_IRQS; /* Map to FreeBSD magic */
phyp_hcall(H_IPI, (uint64_t)(PCPU_GET(cpuid)),
0xff); /* Clear IPI */
/* Clear IPI */
if (regs)
bus_write_1(regs, 12, 0xff);
else
phyp_hcall(H_IPI, (uint64_t)(PCPU_GET(cpuid)),
0xff);
}
/* XXX: super inefficient */
@ -271,9 +369,13 @@ xicp_enable(device_t dev, u_int irq, u_int vector)
KASSERT(sc->nintvecs + 1 < nitems(sc->intvecs),
("Too many XICP interrupts"));
/* Bind to this CPU to start: distrib. ID is last entry in gserver# */
cpu = PCPU_GET(cpuid);
mtx_lock(&sc->sc_mtx);
sc->intvecs[sc->nintvecs].irq = irq;
sc->intvecs[sc->nintvecs].vector = vector;
sc->intvecs[sc->nintvecs].cpu = cpu;
mb();
sc->nintvecs++;
mtx_unlock(&sc->sc_mtx);
@ -282,11 +384,20 @@ xicp_enable(device_t dev, u_int irq, u_int vector)
if (irq == MAX_XICP_IRQS)
return;
/* Bind to this CPU to start: distrib. ID is last entry in gserver# */
cpu = PCPU_GET(cpuid);
rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu, XICP_PRIORITY,
&status);
xicp_unmask(dev, irq);
if (rtas_exists()) {
rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
XICP_PRIORITY, &status);
xicp_unmask(dev, irq);
#ifdef POWERNV
} else {
status = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
/* Unmask implicit for OPAL */
if (status != 0)
panic("OPAL_SET_XIVE IRQ %d -> cpu %d failed: %d", irq,
cpu, status);
#endif
}
}
static void
@ -298,14 +409,24 @@ xicp_eoi(device_t dev, u_int irq)
irq = XICP_IPI;
xirr = irq | (XICP_PRIORITY << 24);
phyp_hcall(H_EOI, xirr);
#ifdef POWERNV
if (mfmsr() & PSL_HV)
bus_write_4(xicp_mem_for_cpu(PCPU_GET(cpuid)), 4, xirr);
else
#endif
phyp_hcall(H_EOI, xirr);
}
static void
xicp_ipi(device_t dev, u_int cpu)
{
phyp_hcall(H_IPI, (uint64_t)cpu, XICP_PRIORITY);
#ifdef POWERNV
if (mfmsr() & PSL_HV)
bus_write_1(xicp_mem_for_cpu(cpu), 12, XICP_PRIORITY);
else
#endif
phyp_hcall(H_IPI, (uint64_t)cpu, XICP_PRIORITY);
}
static void
@ -317,7 +438,21 @@ xicp_mask(device_t dev, u_int irq)
if (irq == MAX_XICP_IRQS)
return;
rtas_call_method(sc->ibm_int_off, 1, 1, irq, &status);
if (rtas_exists()) {
rtas_call_method(sc->ibm_int_off, 1, 1, irq, &status);
#ifdef POWERNV
} else {
int i;
for (i = 0; i < sc->nintvecs; i++) {
if (sc->intvecs[i].irq == irq) {
break;
}
}
KASSERT(i < sc->nintvecs, ("Masking unconfigured interrupt"));
opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2, 0xff);
#endif
}
}
static void
@ -329,6 +464,21 @@ xicp_unmask(device_t dev, u_int irq)
if (irq == MAX_XICP_IRQS)
return;
rtas_call_method(sc->ibm_int_on, 1, 1, irq, &status);
if (rtas_exists()) {
rtas_call_method(sc->ibm_int_on, 1, 1, irq, &status);
#ifdef POWERNV
} else {
int i;
for (i = 0; i < sc->nintvecs; i++) {
if (sc->intvecs[i].irq == irq) {
break;
}
}
KASSERT(i < sc->nintvecs, ("Unmasking unconfigured interrupt"));
opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2,
XICP_PRIORITY);
#endif
}
}