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e1000: Add support for future client platforms

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MFC after:	2 weeks
Sponsored by:	BBOX.io
This commit is contained in:
Kevin Bowling 2023-02-08 18:14:41 -07:00
parent 5636590214
commit 905ae5881b
4 changed files with 38 additions and 0 deletions
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11
sys/dev/e1000/e1000_api.c
View File

@ -355,6 +355,16 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
case E1000_DEV_ID_PCH_LNL_I219_V21:
mac->type = e1000_pch_mtp;
break;
case E1000_DEV_ID_PCH_ARL_I219_LM24:
case E1000_DEV_ID_PCH_ARL_I219_V24:
case E1000_DEV_ID_PCH_PTP_I219_LM25:
case E1000_DEV_ID_PCH_PTP_I219_V25:
case E1000_DEV_ID_PCH_PTP_I219_LM26:
case E1000_DEV_ID_PCH_PTP_I219_V26:
case E1000_DEV_ID_PCH_PTP_I219_LM27:
case E1000_DEV_ID_PCH_PTP_I219_V27:
mac->type = e1000_pch_ptp;
break;
case E1000_DEV_ID_82575EB_COPPER:
case E1000_DEV_ID_82575EB_FIBER_SERDES:
case E1000_DEV_ID_82575GB_QUAD_COPPER:
@ -511,6 +521,7 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)
case e1000_pch_tgp:
case e1000_pch_adp:
case e1000_pch_mtp:
case e1000_pch_ptp:
e1000_init_function_pointers_ich8lan(hw);
break;
case e1000_82575:

9
sys/dev/e1000/e1000_hw.h
View File

@ -183,6 +183,14 @@ struct e1000_hw;
#define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8
#define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5
#define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6
#define E1000_DEV_ID_PCH_ARL_I219_LM24 0x57A0
#define E1000_DEV_ID_PCH_ARL_I219_V24 0x57A1
#define E1000_DEV_ID_PCH_PTP_I219_LM25 0x57B3
#define E1000_DEV_ID_PCH_PTP_I219_V25 0x57B4
#define E1000_DEV_ID_PCH_PTP_I219_LM26 0x57B5
#define E1000_DEV_ID_PCH_PTP_I219_V26 0x57B6
#define E1000_DEV_ID_PCH_PTP_I219_LM27 0x57B7
#define E1000_DEV_ID_PCH_PTP_I219_V27 0x57B8
#define E1000_DEV_ID_82576 0x10C9
#define E1000_DEV_ID_82576_FIBER 0x10E6
#define E1000_DEV_ID_82576_SERDES 0x10E7
@ -274,6 +282,7 @@ enum e1000_mac_type {
e1000_pch_tgp,
e1000_pch_adp,
e1000_pch_mtp,
e1000_pch_ptp,
e1000_82575,
e1000_82576,
e1000_82580,

7
sys/dev/e1000/e1000_ich8lan.c
View File

@ -352,6 +352,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
case e1000_pch_tgp:
case e1000_pch_adp:
case e1000_pch_mtp:
case e1000_pch_ptp:
if (e1000_phy_is_accessible_pchlan(hw))
break;
@ -504,6 +505,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
case e1000_pch_tgp:
case e1000_pch_adp:
case e1000_pch_mtp:
case e1000_pch_ptp:
/* In case the PHY needs to be in mdio slow mode,
* set slow mode and try to get the PHY id again.
*/
@ -806,6 +808,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
case e1000_pch_tgp:
case e1000_pch_adp:
case e1000_pch_mtp:
case e1000_pch_ptp:
/* multicast address update for pch2 */
mac->ops.update_mc_addr_list =
e1000_update_mc_addr_list_pch2lan;
@ -1851,6 +1854,7 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
case e1000_pch_tgp:
case e1000_pch_adp:
case e1000_pch_mtp:
case e1000_pch_ptp:
hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
break;
default:
@ -2310,6 +2314,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
case e1000_pch_tgp:
case e1000_pch_adp:
case e1000_pch_mtp:
case e1000_pch_ptp:
sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
break;
default:
@ -3435,6 +3440,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
case e1000_pch_tgp:
case e1000_pch_adp:
case e1000_pch_mtp:
case e1000_pch_ptp:
bank1_offset = nvm->flash_bank_size;
act_offset = E1000_ICH_NVM_SIG_WORD;
@ -4409,6 +4415,7 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
case e1000_pch_tgp:
case e1000_pch_adp:
case e1000_pch_mtp:
case e1000_pch_ptp:
word = NVM_COMPAT;
valid_csum_mask = NVM_COMPAT_VALID_CSUM;
break;

11
sys/dev/e1000/if_em.c
View File

@ -203,6 +203,14 @@ static pci_vendor_info_t em_vendor_info_array[] =
PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"),
PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"),
PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"),
PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"),
PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"),
PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"),
PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"),
PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"),
PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"),
PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"),
PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"),
/* required last entry */
PVID_END
};
@ -1256,6 +1264,7 @@ em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
case e1000_pch_tgp:
case e1000_pch_adp:
case e1000_pch_mtp:
case e1000_pch_ptp:
case e1000_82574:
case e1000_82583:
case e1000_80003es2lan:
@ -2655,6 +2664,7 @@ em_reset(if_ctx_t ctx)
case e1000_pch_tgp:
case e1000_pch_adp:
case e1000_pch_mtp:
case e1000_pch_ptp:
pba = E1000_PBA_26K;
break;
case e1000_82575:
@ -2768,6 +2778,7 @@ em_reset(if_ctx_t ctx)
case e1000_pch_tgp:
case e1000_pch_adp:
case e1000_pch_mtp:
case e1000_pch_ptp:
hw->fc.high_water = 0x5C20;
hw->fc.low_water = 0x5048;
hw->fc.pause_time = 0x0650;