e1000: Add support for future client platforms
MFC after: 2 weeks Sponsored by: BBOX.io
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5636590214
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@ -355,6 +355,16 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
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case E1000_DEV_ID_PCH_LNL_I219_V21:
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mac->type = e1000_pch_mtp;
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break;
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case E1000_DEV_ID_PCH_ARL_I219_LM24:
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case E1000_DEV_ID_PCH_ARL_I219_V24:
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case E1000_DEV_ID_PCH_PTP_I219_LM25:
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case E1000_DEV_ID_PCH_PTP_I219_V25:
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case E1000_DEV_ID_PCH_PTP_I219_LM26:
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case E1000_DEV_ID_PCH_PTP_I219_V26:
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case E1000_DEV_ID_PCH_PTP_I219_LM27:
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case E1000_DEV_ID_PCH_PTP_I219_V27:
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mac->type = e1000_pch_ptp;
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break;
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case E1000_DEV_ID_82575EB_COPPER:
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case E1000_DEV_ID_82575EB_FIBER_SERDES:
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case E1000_DEV_ID_82575GB_QUAD_COPPER:
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@ -511,6 +521,7 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_ptp:
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e1000_init_function_pointers_ich8lan(hw);
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break;
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case e1000_82575:
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@ -183,6 +183,14 @@ struct e1000_hw;
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#define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8
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#define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5
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#define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6
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#define E1000_DEV_ID_PCH_ARL_I219_LM24 0x57A0
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#define E1000_DEV_ID_PCH_ARL_I219_V24 0x57A1
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#define E1000_DEV_ID_PCH_PTP_I219_LM25 0x57B3
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#define E1000_DEV_ID_PCH_PTP_I219_V25 0x57B4
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#define E1000_DEV_ID_PCH_PTP_I219_LM26 0x57B5
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#define E1000_DEV_ID_PCH_PTP_I219_V26 0x57B6
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#define E1000_DEV_ID_PCH_PTP_I219_LM27 0x57B7
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#define E1000_DEV_ID_PCH_PTP_I219_V27 0x57B8
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#define E1000_DEV_ID_82576 0x10C9
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#define E1000_DEV_ID_82576_FIBER 0x10E6
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#define E1000_DEV_ID_82576_SERDES 0x10E7
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@ -274,6 +282,7 @@ enum e1000_mac_type {
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e1000_pch_tgp,
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e1000_pch_adp,
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e1000_pch_mtp,
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e1000_pch_ptp,
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e1000_82575,
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e1000_82576,
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e1000_82580,
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@ -352,6 +352,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_ptp:
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if (e1000_phy_is_accessible_pchlan(hw))
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break;
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@ -504,6 +505,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_ptp:
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/* In case the PHY needs to be in mdio slow mode,
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* set slow mode and try to get the PHY id again.
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*/
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@ -806,6 +808,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_ptp:
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/* multicast address update for pch2 */
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mac->ops.update_mc_addr_list =
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e1000_update_mc_addr_list_pch2lan;
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@ -1851,6 +1854,7 @@ void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_ptp:
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hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
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break;
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default:
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@ -2310,6 +2314,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_ptp:
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sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
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break;
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default:
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@ -3435,6 +3440,7 @@ static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_ptp:
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bank1_offset = nvm->flash_bank_size;
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act_offset = E1000_ICH_NVM_SIG_WORD;
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@ -4409,6 +4415,7 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_ptp:
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word = NVM_COMPAT;
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valid_csum_mask = NVM_COMPAT_VALID_CSUM;
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break;
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@ -203,6 +203,14 @@ static pci_vendor_info_t em_vendor_info_array[] =
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PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"),
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PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"),
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PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"),
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PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"),
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PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"),
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PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"),
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PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"),
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PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"),
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PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"),
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PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"),
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PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"),
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/* required last entry */
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PVID_END
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};
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@ -1256,6 +1264,7 @@ em_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_ptp:
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case e1000_82574:
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case e1000_82583:
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case e1000_80003es2lan:
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@ -2655,6 +2664,7 @@ em_reset(if_ctx_t ctx)
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_ptp:
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pba = E1000_PBA_26K;
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break;
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case e1000_82575:
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@ -2768,6 +2778,7 @@ em_reset(if_ctx_t ctx)
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case e1000_pch_tgp:
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case e1000_pch_adp:
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case e1000_pch_mtp:
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case e1000_pch_ptp:
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hw->fc.high_water = 0x5C20;
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hw->fc.low_water = 0x5048;
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hw->fc.pause_time = 0x0650;
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