Import device-tree files from Linux 5.18
This commit is contained in:
Emmanuel Vadot
parent
b7d8b5635a
commit
9066e824ca
@ -3,9 +3,10 @@ DT_DOC_CHECKER ?= dt-doc-validate
|
||||
DT_EXTRACT_EX ?= dt-extract-example
|
||||
DT_MK_SCHEMA ?= dt-mk-schema
|
||||
|
||||
DT_SCHEMA_LINT = $(shell which yamllint)
|
||||
DT_SCHEMA_LINT = $(shell which yamllint || \
|
||||
echo "warning: python package 'yamllint' not installed, skipping" >&2)
|
||||
|
||||
DT_SCHEMA_MIN_VERSION = 2021.2.1
|
||||
DT_SCHEMA_MIN_VERSION = 2022.3
|
||||
|
||||
PHONY += check_dtschema_version
|
||||
check_dtschema_version:
|
||||
@ -24,18 +25,11 @@ quiet_cmd_extract_ex = DTEX $@
|
||||
$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
|
||||
$(call if_changed,extract_ex)
|
||||
|
||||
# Use full schemas when checking %.example.dts
|
||||
DT_TMP_SCHEMA := $(obj)/processed-schema-examples.json
|
||||
|
||||
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
|
||||
-name 'processed-schema*' ! \
|
||||
-name '*.example.dt.yaml' \)
|
||||
-name 'processed-schema*' \)
|
||||
|
||||
ifeq ($(DT_SCHEMA_FILES),)
|
||||
find_cmd = $(find_all_cmd)
|
||||
else
|
||||
find_cmd = echo $(addprefix $(srctree)/, $(DT_SCHEMA_FILES))
|
||||
endif
|
||||
find_cmd = $(find_all_cmd) | grep -F "$(DT_SCHEMA_FILES)"
|
||||
CHK_DT_DOCS := $(shell $(find_cmd))
|
||||
|
||||
quiet_cmd_yamllint = LINT $(src)
|
||||
cmd_yamllint = ($(find_cmd) | \
|
||||
@ -72,35 +66,14 @@ override DTC_FLAGS := \
|
||||
# Disable undocumented compatible checks until warning free
|
||||
override DT_CHECKER_FLAGS ?=
|
||||
|
||||
$(obj)/processed-schema-examples.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
|
||||
$(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
|
||||
$(call if_changed_rule,chkdt)
|
||||
|
||||
ifeq ($(DT_SCHEMA_FILES),)
|
||||
|
||||
# Unless DT_SCHEMA_FILES is specified, use the full schema for dtbs_check too.
|
||||
# Just copy processed-schema-examples.json
|
||||
|
||||
$(obj)/processed-schema.json: $(obj)/processed-schema-examples.json FORCE
|
||||
$(call if_changed,copy)
|
||||
|
||||
DT_SCHEMA_FILES = $(DT_DOCS)
|
||||
|
||||
else
|
||||
|
||||
# If DT_SCHEMA_FILES is specified, use it for processed-schema.json
|
||||
|
||||
$(obj)/processed-schema.json: DT_MK_SCHEMA_FLAGS := -u
|
||||
$(obj)/processed-schema.json: $(DT_SCHEMA_FILES) check_dtschema_version FORCE
|
||||
$(call if_changed,mk_schema)
|
||||
|
||||
endif
|
||||
|
||||
always-$(CHECK_DT_BINDING) += processed-schema-examples.json
|
||||
always-$(CHECK_DTBS) += processed-schema.json
|
||||
always-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
|
||||
always-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
|
||||
always-y += processed-schema.json
|
||||
always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dts, $(CHK_DT_DOCS))
|
||||
always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dtb, $(CHK_DT_DOCS))
|
||||
|
||||
# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of
|
||||
# build artifacts here before they are processed by scripts/Makefile.clean
|
||||
clean-files = $(shell find $(obj) \( -name '*.example.dts' -o \
|
||||
-name '*.example.dt.yaml' \) -delete 2>/dev/null)
|
||||
-name '*.example.dtb' \) -delete 2>/dev/null)
|
||||
|
||||
28
Bindings/arm/airoha.yaml
Normal file
28
Bindings/arm/airoha.yaml
Normal file
@ -0,0 +1,28 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/airoha.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Airoha SoC based Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Felix Fietkau <nbd@nbd.name>
|
||||
- John Crispin <john@phrozen.org>
|
||||
|
||||
description:
|
||||
Boards with an Airoha SoC shall have the following properties.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- airoha,en7523-evb
|
||||
- const: airoha,en7523
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@ -13,12 +13,46 @@ properties:
|
||||
$nodename:
|
||||
const: "/"
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- altr,socfpga-cyclone5
|
||||
- altr,socfpga-arria5
|
||||
- altr,socfpga-arria10
|
||||
- const: altr,socfpga
|
||||
oneOf:
|
||||
- description: Arria 5 boards
|
||||
items:
|
||||
- enum:
|
||||
- altr,socfpga-arria5-socdk
|
||||
- const: altr,socfpga-arria5
|
||||
- const: altr,socfpga
|
||||
|
||||
- description: Arria 10 boards
|
||||
items:
|
||||
- enum:
|
||||
- altr,socfpga-arria10-socdk
|
||||
- enclustra,mercury-aa1
|
||||
- const: altr,socfpga-arria10
|
||||
- const: altr,socfpga
|
||||
|
||||
- description: Cyclone 5 boards
|
||||
items:
|
||||
- enum:
|
||||
- altr,socfpga-cyclone5-socdk
|
||||
- denx,mcvevk
|
||||
- ebv,socrates
|
||||
- macnica,sodia
|
||||
- novtech,chameleon96
|
||||
- samtec,vining
|
||||
- terasic,de0-atlas
|
||||
- terasic,socfpga-cyclone5-sockit
|
||||
- const: altr,socfpga-cyclone5
|
||||
- const: altr,socfpga
|
||||
|
||||
- description: Stratix 10 boards
|
||||
items:
|
||||
- enum:
|
||||
- altr,socfpga-stratix10-socdk
|
||||
- const: altr,socfpga-stratix10
|
||||
|
||||
- description: SoCFPGA VT
|
||||
items:
|
||||
- const: altr,socfpga-vt
|
||||
- const: altr,socfpga
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
|
||||
@ -108,6 +108,7 @@ properties:
|
||||
- amlogic,p230
|
||||
- amlogic,p231
|
||||
- libretech,aml-s905d-pc
|
||||
- osmc,vero4k-plus
|
||||
- phicomm,n1
|
||||
- smartlabs,sml5442tw
|
||||
- videostrong,gxl-kii-pro
|
||||
@ -170,9 +171,14 @@ properties:
|
||||
- description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
|
||||
items:
|
||||
- enum:
|
||||
- amediatech,x96-air
|
||||
- amediatech,x96-air-gbit
|
||||
- bananapi,bpi-m5
|
||||
- cyx,a95xf3-air
|
||||
- cyx,a95xf3-air-gbit
|
||||
- hardkernel,odroid-c4
|
||||
- hardkernel,odroid-hc4
|
||||
- haochuangyi,h96-max
|
||||
- khadas,vim3l
|
||||
- seirobotics,sei610
|
||||
- const: amlogic,sm1
|
||||
@ -183,6 +189,12 @@ properties:
|
||||
- amlogic,ad401
|
||||
- const: amlogic,a1
|
||||
|
||||
- description: Boards with the Amlogic Meson S4 S805X2 SoC
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,aq222
|
||||
- const: amlogic,s4
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -42,7 +42,7 @@ patternProperties:
|
||||
description:
|
||||
The individual power management domains within this controller
|
||||
type: object
|
||||
$ref: /power/apple,pmgr-pwrstate.yaml#
|
||||
$ref: /schemas/power/apple,pmgr-pwrstate.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -119,6 +119,11 @@ examples:
|
||||
arm,hbi = <0x249>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
gic: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
/*
|
||||
* This CCI node corresponds to a CCI component whose control
|
||||
* registers sits at address 0x000000002c090000.
|
||||
|
||||
@ -175,6 +175,15 @@ properties:
|
||||
- const: microchip,lan9668
|
||||
- const: microchip,lan966
|
||||
|
||||
- description: Kontron KSwitch D10 MMT series
|
||||
items:
|
||||
- enum:
|
||||
- kontron,kswitch-d10-mmt-8g
|
||||
- kontron,kswitch-d10-mmt-6g-2gs
|
||||
- const: kontron,s1921
|
||||
- const: microchip,lan9668
|
||||
- const: microchip,lan966
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,sams70j19
|
||||
|
||||
@ -51,6 +51,7 @@ properties:
|
||||
- raspberrypi,3-model-b-plus
|
||||
- raspberrypi,3-compute-module
|
||||
- raspberrypi,3-compute-module-lite
|
||||
- raspberrypi,model-zero-2-w
|
||||
- const: brcm,bcm2837
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@ -62,8 +62,8 @@ Example 1 (ARM 64-bit, 6-cpu system, two clusters):
|
||||
The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
|
||||
are 1024 and 578 for cluster0 and cluster1. Further normalization
|
||||
is done by the operating system based on cluster0@max-freq=1100 and
|
||||
custer1@max-freq=850, final capacities are 1024 for cluster0 and
|
||||
446 for cluster1 (576*850/1100).
|
||||
cluster1@max-freq=850, final capacities are 1024 for cluster0 and
|
||||
446 for cluster1 (578*850/1100).
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
|
||||
@ -173,6 +173,7 @@ properties:
|
||||
- nvidia,tegra194-carmel
|
||||
- qcom,krait
|
||||
- qcom,kryo
|
||||
- qcom,kryo250
|
||||
- qcom,kryo260
|
||||
- qcom,kryo280
|
||||
- qcom,kryo385
|
||||
@ -232,17 +233,19 @@ properties:
|
||||
- ti,am4372
|
||||
|
||||
cpu-release-addr:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint64'
|
||||
|
||||
oneOf:
|
||||
- $ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
- $ref: '/schemas/types.yaml#/definitions/uint64'
|
||||
description:
|
||||
The DT specification defines this as 64-bit always, but some 32-bit Arm
|
||||
systems have used a 32-bit value which must be supported.
|
||||
Required for systems that have an "enable-method"
|
||||
property value of "spin-table".
|
||||
On ARM v8 64-bit systems must be a two cell
|
||||
property identifying a 64-bit zero-initialised
|
||||
memory location.
|
||||
|
||||
cpu-idle-states:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
items:
|
||||
maxItems: 1
|
||||
description: |
|
||||
List of phandles to idle state nodes supported
|
||||
by this cpu (see ./idle-states.yaml).
|
||||
|
||||
@ -86,6 +86,7 @@ This binding uses the common clock binding[1].
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of:
|
||||
"fsl,imx8dxl-clk"
|
||||
"fsl,imx8qm-clk"
|
||||
"fsl,imx8qxp-clk"
|
||||
followed by "fsl,scu-clk"
|
||||
|
||||
@ -762,6 +762,7 @@ properties:
|
||||
- enum:
|
||||
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
|
||||
- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
|
||||
- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
|
||||
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
|
||||
- fsl,imx8mm-evk # i.MX8MM EVK Board
|
||||
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
|
||||
@ -769,8 +770,13 @@ properties:
|
||||
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
|
||||
- gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
|
||||
- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
|
||||
- gw,imx8mm-gw7903 # i.MX8MM Gateworks Board
|
||||
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
|
||||
- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
|
||||
- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
|
||||
- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
|
||||
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
|
||||
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: Engicam i.Core MX8M Mini SoM based boards
|
||||
@ -787,6 +793,24 @@ properties:
|
||||
- const: kontron,imx8mm-n801x-som
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: Toradex Boards with Verdin iMX8M Mini Modules
|
||||
items:
|
||||
- enum:
|
||||
- toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
|
||||
- toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board
|
||||
- const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
|
||||
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: Toradex Boards with Verdin iMX8M Mini Wi-Fi / BT Modules
|
||||
items:
|
||||
- enum:
|
||||
- toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
|
||||
- toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
|
||||
- const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
|
||||
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: Variscite VAR-SOM-MX8MM based boards
|
||||
items:
|
||||
- const: variscite,var-som-mx8mm-symphony
|
||||
|
||||
26
Bindings/arm/intel,socfpga.yaml
Normal file
26
Bindings/arm/intel,socfpga.yaml
Normal file
@ -0,0 +1,26 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel SoCFPGA platform device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: "/"
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: AgileX boards
|
||||
items:
|
||||
- enum:
|
||||
- intel,n5x-socdk
|
||||
- intel,socfpga-agilex-socdk
|
||||
- const: intel,socfpga-agilex
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
20
Bindings/arm/linux,dummy-virt.yaml
Normal file
20
Bindings/arm/linux,dummy-virt.yaml
Normal file
@ -0,0 +1,20 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/linux,dummy-virt.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: QEMU virt machine
|
||||
|
||||
maintainers:
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: "/"
|
||||
compatible:
|
||||
const: linux,dummy-virt
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@ -30,6 +30,10 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt6580-evbp1
|
||||
- const: mediatek,mt6580
|
||||
- items:
|
||||
- enum:
|
||||
- prestigio,pmt5008-3g
|
||||
- const: mediatek,mt6582
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp1
|
||||
|
||||
@ -29,6 +29,7 @@ properties:
|
||||
- mediatek,mt8167-mmsys
|
||||
- mediatek,mt8173-mmsys
|
||||
- mediatek,mt8183-mmsys
|
||||
- mediatek,mt8186-mmsys
|
||||
- mediatek,mt8192-mmsys
|
||||
- mediatek,mt8365-mmsys
|
||||
- const: syscon
|
||||
|
||||
@ -81,4 +81,4 @@ Example:
|
||||
};
|
||||
};
|
||||
|
||||
[1]. Documentation/devicetree/bindings/arm/idle-states.yaml
|
||||
[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml
|
||||
|
||||
@ -27,6 +27,8 @@ properties:
|
||||
- qcom,sm6350-llcc
|
||||
- qcom,sm8150-llcc
|
||||
- qcom,sm8250-llcc
|
||||
- qcom,sm8350-llcc
|
||||
- qcom,sm8450-llcc
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
||||
@ -23,8 +23,12 @@ properties:
|
||||
- description: infinity2m boards
|
||||
items:
|
||||
- enum:
|
||||
- 100ask,dongshanpione # 100ask DongShanPiOne
|
||||
- honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit
|
||||
- m5stack,unitv2 # M5Stack UnitV2
|
||||
- miyoo,miyoo-mini # Miyoo Mini
|
||||
- wirelesstag,ido-som2d01 # Wireless Tag IDO-SOM2D01
|
||||
- wirelesstag,ido-sbc2d06-v1b-22w # Wireless Tag IDO-SBC2D06-1VB-22W
|
||||
- const: mstar,infinity2m
|
||||
|
||||
- description: infinity3 boards
|
||||
|
||||
48
Bindings/arm/npcm/nuvoton,gcr.yaml
Normal file
48
Bindings/arm/npcm/nuvoton,gcr.yaml
Normal file
@ -0,0 +1,48 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Global Control Registers block in Nuvoton SoCs
|
||||
|
||||
maintainers:
|
||||
- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
|
||||
|
||||
description:
|
||||
The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
|
||||
that expose misc functionality such as chip model and version information or
|
||||
pinmux settings.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- nuvoton,wpcm450-gcr
|
||||
- nuvoton,npcm750-gcr
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
|
||||
examples:
|
||||
- |
|
||||
gcr: syscon@800000 {
|
||||
compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
|
||||
reg = <0x800000 0x1000>;
|
||||
|
||||
mux-controller {
|
||||
compatible = "mmio-mux";
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x38 0x07>;
|
||||
idle-states = <2>;
|
||||
};
|
||||
};
|
||||
@ -20,6 +20,8 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- apm,potenza-pmu
|
||||
- apple,firestorm-pmu
|
||||
- apple,icestorm-pmu
|
||||
- arm,armv8-pmuv3 # Only for s/w models
|
||||
- arm,arm1136-pmu
|
||||
- arm,arm1176-pmu
|
||||
@ -66,6 +68,8 @@ properties:
|
||||
|
||||
interrupt-affinity:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
maxItems: 1
|
||||
description:
|
||||
When using SPIs, specifies a list of phandles to CPU
|
||||
nodes corresponding directly to the affinity of
|
||||
|
||||
@ -101,7 +101,7 @@ properties:
|
||||
bindings in [1]) must specify this property.
|
||||
|
||||
[1] Kernel documentation - ARM idle states bindings
|
||||
Documentation/devicetree/bindings/arm/idle-states.yaml
|
||||
Documentation/devicetree/bindings/cpu/idle-states.yaml
|
||||
|
||||
patternProperties:
|
||||
"^power-domain-":
|
||||
|
||||
@ -42,6 +42,7 @@ description: |
|
||||
sc7180
|
||||
sc7280
|
||||
sdm630
|
||||
sdm632
|
||||
sdm660
|
||||
sdm845
|
||||
sdx55
|
||||
@ -172,7 +173,21 @@ properties:
|
||||
- const: qcom,apq8094
|
||||
|
||||
- items:
|
||||
- const: qcom,msm8996-mtp
|
||||
- enum:
|
||||
- arrow,apq8096-db820c
|
||||
- inforce,ifc6640
|
||||
- const: qcom,apq8096-sbc
|
||||
- const: qcom,apq8096
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,msm8996-mtp
|
||||
- sony,dora-row
|
||||
- sony,kagura-row
|
||||
- sony,keyaki-row
|
||||
- xiaomi,gemini
|
||||
- xiaomi,scorpio
|
||||
- const: qcom,msm8996
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
@ -210,6 +225,11 @@ properties:
|
||||
- google,senor
|
||||
- const: qcom,sc7280
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp3
|
||||
- const: qcom,sdm632
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- xiaomi,lavender
|
||||
@ -262,6 +282,7 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8450-hdk
|
||||
- qcom,sm8450-qrd
|
||||
- const: qcom,sm8450
|
||||
|
||||
|
||||
@ -421,6 +421,15 @@ properties:
|
||||
- renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
|
||||
- const: renesas,r9a07g044
|
||||
|
||||
- description: RZ/V2L (R9A07G054)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,smarc-evk # SMARC EVK
|
||||
- enum:
|
||||
- renesas,r9a07g054l1 # Single Cortex-A55 RZ/V2L
|
||||
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
|
||||
- const: renesas,r9a07g054
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -481,6 +481,14 @@ properties:
|
||||
- const: pine64,pinebook-pro
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Pine64 PineNote
|
||||
items:
|
||||
- enum:
|
||||
- pine64,pinenote-v1.1
|
||||
- pine64,pinenote-v1.2
|
||||
- const: pine64,pinenote
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Pine64 Rock64
|
||||
items:
|
||||
- const: pine64,rock64
|
||||
@ -651,6 +659,11 @@ properties:
|
||||
- const: rockchip,rk3568-evb1-v10
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Rockchip RK3568 Banana Pi R2 Pro
|
||||
items:
|
||||
- const: rockchip,rk3568-bpi-r2pro
|
||||
- const: rockchip,rk3568
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -140,6 +140,8 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- insignal,arndale-octa # Insignal Arndale Octa
|
||||
- samsung,chagall-wifi # Samsung SM-T800
|
||||
- samsung,klimt-wifi # Samsung SM-T700
|
||||
- samsung,smdk5420 # Samsung SMDK5420 eval
|
||||
- const: samsung,exynos5420
|
||||
- const: samsung,exynos5
|
||||
|
||||
@ -28,6 +28,12 @@ properties:
|
||||
- enum:
|
||||
- st,stm32mp153
|
||||
- st,stm32mp157
|
||||
|
||||
- description: emtrion STM32MP1 Argon based Boards
|
||||
items:
|
||||
- const: emtrion,stm32mp157c-emsbc-argon
|
||||
- const: emtrion,stm32mp157c-emstamp-argon
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f429i-disco
|
||||
|
||||
@ -444,6 +444,11 @@ properties:
|
||||
- const: haoyu,a10-marsboard
|
||||
- const: allwinner,sun4i-a10
|
||||
|
||||
- description: HAOYU Electronics Marsboard A20
|
||||
items:
|
||||
- const: haoyu,a20-marsboard
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: MapleBoard MP130
|
||||
items:
|
||||
- const: mapleboard,mp130
|
||||
|
||||
@ -13,7 +13,6 @@ maintainers:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra20-pmc
|
||||
- nvidia,tegra20-pmc
|
||||
- nvidia,tegra30-pmc
|
||||
- nvidia,tegra114-pmc
|
||||
|
||||
27
Bindings/arm/tesla.yaml
Normal file
27
Bindings/arm/tesla.yaml
Normal file
@ -0,0 +1,27 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/tesla.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Tesla Full Self Driving(FSD) platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Alim Akhtar <alim.akhtar@samsung.com>
|
||||
- linux-fsd@tesla.com
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
|
||||
- description: FSD SoC board
|
||||
items:
|
||||
- enum:
|
||||
- tesla,fsd-evb # Tesla FSD Evaluation
|
||||
- const: tesla,fsd
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@ -46,6 +46,12 @@ properties:
|
||||
- ti,j7200-evm
|
||||
- const: ti,j7200
|
||||
|
||||
- description: K3 AM625 SoC
|
||||
items:
|
||||
- enum:
|
||||
- ti,am625-sk
|
||||
- const: ti,am625
|
||||
|
||||
- description: K3 AM642 SoC
|
||||
items:
|
||||
- enum:
|
||||
|
||||
189
Bindings/ata/ahci-platform.yaml
Normal file
189
Bindings/ata/ahci-platform.yaml
Normal file
@ -0,0 +1,189 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: AHCI SATA Controller
|
||||
|
||||
description: |
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
It is possible, but not required, to represent each port as a sub-node.
|
||||
It allows to enable each port independently when dealing with multiple
|
||||
PHYs.
|
||||
|
||||
maintainers:
|
||||
- Hans de Goede <hdegoede@redhat.com>
|
||||
- Jens Axboe <axboe@kernel.dk>
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- brcm,iproc-ahci
|
||||
- cavium,octeon-7130-ahci
|
||||
- hisilicon,hisi-ahci
|
||||
- ibm,476gtr-ahci
|
||||
- marvell,armada-3700-ahci
|
||||
- marvell,armada-8k-ahci
|
||||
- marvell,berlin2q-ahci
|
||||
- snps,dwc-ahci
|
||||
- snps,spear-ahci
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- $ref: "sata-common.yaml#"
|
||||
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- brcm,iproc-ahci
|
||||
- marvell,armada-8k-ahci
|
||||
- marvell,berlin2-ahci
|
||||
- marvell,berlin2q-ahci
|
||||
- const: generic-ahci
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,rk3568-dwc-ahci
|
||||
- const: snps,dwc-ahci
|
||||
- enum:
|
||||
- cavium,octeon-7130-ahci
|
||||
- hisilicon,hisi-ahci
|
||||
- ibm,476gtr-ahci
|
||||
- marvell,armada-3700-ahci
|
||||
- snps,dwc-ahci
|
||||
- snps,spear-ahci
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
description:
|
||||
Clock IDs array as required by the controller.
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
description:
|
||||
Names of clocks corresponding to IDs in the clock property.
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
ahci-supply:
|
||||
description:
|
||||
regulator for AHCI controller
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
phy-supply:
|
||||
description:
|
||||
regulator for PHY power
|
||||
|
||||
phys:
|
||||
description:
|
||||
List of all PHYs on this controller
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
description:
|
||||
Name specifier for the PHYs
|
||||
maxItems: 1
|
||||
|
||||
ports-implemented:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description: |
|
||||
Mask that indicates which ports that the HBA supports
|
||||
are available for software to use. Useful if PORTS_IMPL
|
||||
is not programmed by the BIOS, which is true with
|
||||
some embedded SoCs.
|
||||
maximum: 0x1f
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
target-supply:
|
||||
description:
|
||||
regulator for SATA target power
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
patternProperties:
|
||||
"^sata-port@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description:
|
||||
Subnode with configuration of the Ports.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
maxItems: 1
|
||||
|
||||
target-supply:
|
||||
description:
|
||||
regulator for SATA target power
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
anyOf:
|
||||
- required: [ phys ]
|
||||
- required: [ target-supply ]
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sata@ffe08000 {
|
||||
compatible = "snps,spear-ahci";
|
||||
reg = <0xffe08000 0x1000>;
|
||||
interrupts = <115>;
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/berlin2q.h>
|
||||
sata@f7e90000 {
|
||||
compatible = "marvell,berlin2q-ahci", "generic-ahci";
|
||||
reg = <0xf7e90000 0x1000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&chip CLKID_SATA>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata0: sata-port@0 {
|
||||
reg = <0>;
|
||||
phys = <&sata_phy 0>;
|
||||
target-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
sata1: sata-port@1 {
|
||||
reg = <1>;
|
||||
phys = <&sata_phy 1>;
|
||||
target-supply = <®_sata1>;
|
||||
};
|
||||
};
|
||||
109
Bindings/ata/cortina,gemini-sata-bridge.yaml
Normal file
109
Bindings/ata/cortina,gemini-sata-bridge.yaml
Normal file
@ -0,0 +1,109 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cortina Systems Gemini SATA Bridge
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |
|
||||
The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
|
||||
takes two Faraday Technology FTIDE010 PATA controllers and bridges
|
||||
them in different configurations to two SATA ports.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: cortina,gemini-sata-bridge
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
description: phandles to the reset lines for both SATA bridges
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: sata0
|
||||
- const: sata1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
description: phandles to the compulsory peripheral clocks
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: SATA0_PCLK
|
||||
- const: SATA1_PCLK
|
||||
|
||||
syscon:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: a phandle to the global Gemini system controller
|
||||
|
||||
cortina,gemini-ata-muxmode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
- 2
|
||||
- 3
|
||||
description: |
|
||||
Tell the desired multiplexing mode for the ATA controller and SATA
|
||||
bridges.
|
||||
Mode 0: ata0 master <-> sata0
|
||||
ata1 master <-> sata1
|
||||
ata0 slave interface brought out on IDE pads
|
||||
Mode 1: ata0 master <-> sata0
|
||||
ata1 master <-> sata1
|
||||
ata1 slave interface brought out on IDE pads
|
||||
Mode 2: ata1 master <-> sata1
|
||||
ata1 slave <-> sata0
|
||||
ata0 master and slave interfaces brought out on IDE pads
|
||||
Mode 3: ata0 master <-> sata0
|
||||
ata0 slave <-> sata1
|
||||
ata1 master and slave interfaces brought out on IDE pads
|
||||
|
||||
cortina,gemini-enable-ide-pins:
|
||||
type: boolean
|
||||
description: Enables the PATA to IDE connection.
|
||||
The muxmode setting decides whether ATA0 or ATA1 is brought out,
|
||||
and whether master, slave or both interfaces get brought out.
|
||||
|
||||
cortina,gemini-enable-sata-bridge:
|
||||
type: boolean
|
||||
description: Enables the PATA to SATA bridge inside the Gemnini SoC.
|
||||
The Muxmode decides what PATA blocks will be muxed out and how.
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
- cortina,gemini-ata-muxmode
|
||||
- resets
|
||||
- reset-names
|
||||
- compatible
|
||||
- reg
|
||||
- syscon
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/cortina,gemini-clock.h>
|
||||
sata@46000000 {
|
||||
compatible = "cortina,gemini-sata-bridge";
|
||||
reg = <0x46000000 0x100>;
|
||||
resets = <&rcon 26>, <&rcon 27>;
|
||||
reset-names = "sata0", "sata1";
|
||||
clocks = <&gcc GEMINI_CLK_GATE_SATA0>,
|
||||
<&gcc GEMINI_CLK_GATE_SATA1>;
|
||||
clock-names = "SATA0_PCLK", "SATA1_PCLK";
|
||||
syscon = <&syscon>;
|
||||
cortina,gemini-ata-muxmode = <3>;
|
||||
cortina,gemini-enable-ide-pins;
|
||||
cortina,gemini-enable-sata-bridge;
|
||||
};
|
||||
@ -51,6 +51,9 @@ properties:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
calxeda,tx-atten:
|
||||
description: |
|
||||
|
||||
@ -35,7 +35,10 @@ properties:
|
||||
The SRAM that needs to be claimed to access the display engine
|
||||
bus.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to SRAM
|
||||
- description: register value for device
|
||||
|
||||
ranges: true
|
||||
|
||||
|
||||
@ -21,6 +21,7 @@ properties:
|
||||
- const: nvidia,tegra210-aconnect
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra234-aconnect
|
||||
- nvidia,tegra186-aconnect
|
||||
- nvidia,tegra194-aconnect
|
||||
- const: nvidia,tegra210-aconnect
|
||||
|
||||
@ -34,7 +34,6 @@ properties:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- ti,sysc-omap2
|
||||
- ti,sysc-omap2
|
||||
- ti,sysc-omap4
|
||||
- ti,sysc-omap4-simple
|
||||
|
||||
62
Bindings/clock/apple,nco.yaml
Normal file
62
Bindings/clock/apple,nco.yaml
Normal file
@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/apple,nco.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Apple SoCs' NCO block
|
||||
|
||||
maintainers:
|
||||
- Martin Povišer <povik+lin@cutebit.org>
|
||||
|
||||
description: |
|
||||
The NCO (Numerically Controlled Oscillator) block found on Apple SoCs
|
||||
such as the t8103 (M1) is a programmable clock generator performing
|
||||
fractional division of a high frequency input clock.
|
||||
|
||||
It carries a number of independent channels and is typically used for
|
||||
generation of audio bitclocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- apple,t6000-nco
|
||||
- apple,t8103-nco
|
||||
- const: apple,nco
|
||||
|
||||
clocks:
|
||||
description:
|
||||
Specifies the reference clock from which the output clocks
|
||||
are derived through fractional division.
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
nco_clkref: clock-ref {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <900000000>;
|
||||
clock-output-names = "nco-ref";
|
||||
};
|
||||
|
||||
nco: clock-controller@23b044000 {
|
||||
compatible = "apple,t8103-nco", "apple,nco";
|
||||
reg = <0x3b044000 0x14000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&nco_clkref>;
|
||||
};
|
||||
@ -61,16 +61,4 @@ examples:
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
# Example UART controller node that consumes clock generated by the clock controller:
|
||||
- |
|
||||
uart0: serial@58018000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x58018000 0x2000>;
|
||||
clocks = <&clk 45>, <&clk 46>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupts = <0 9 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
91
Bindings/clock/cirrus,cs2000-cp.yaml
Normal file
91
Bindings/clock/cirrus,cs2000-cp.yaml
Normal file
@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
|
||||
|
||||
maintainers:
|
||||
- Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
|
||||
description: |
|
||||
The CS2000-CP is an extremely versatile system clocking device that
|
||||
utilizes a programmable phase lock loop.
|
||||
|
||||
Link: https://www.cirrus.com/products/cs2000/
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- cirrus,cs2000-cp
|
||||
|
||||
clocks:
|
||||
description:
|
||||
Common clock binding for CLK_IN, XTI/REF_CLK
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: clk_in
|
||||
- const: ref_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
cirrus,aux-output-source:
|
||||
description:
|
||||
Specifies the function of the auxiliary clock output pin
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum:
|
||||
- 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input
|
||||
- 1 # CS2000CP_AUX_OUTPUT_CLK_IN: clk_in input
|
||||
- 2 # CS2000CP_AUX_OUTPUT_CLK_OUT: clk_out output
|
||||
- 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status
|
||||
default: 0
|
||||
|
||||
cirrus,clock-skip:
|
||||
description:
|
||||
This mode allows the PLL to maintain lock even when CLK_IN
|
||||
has missing pulses for up to 20 ms.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
cirrus,dynamic-mode:
|
||||
description:
|
||||
In dynamic mode, the CLK_IN input is used to drive the
|
||||
digital PLL of the silicon.
|
||||
If not given, the static mode shall be used to derive the
|
||||
output signal directly from the REF_CLK input.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/cirrus,cs2000-cp.h>
|
||||
|
||||
i2c@0 {
|
||||
reg = <0x0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-controller@4f {
|
||||
#clock-cells = <0>;
|
||||
compatible = "cirrus,cs2000-cp";
|
||||
reg = <0x4f>;
|
||||
clocks = <&rcar_sound 0>, <&x12_clk>;
|
||||
clock-names = "clk_in", "ref_clk";
|
||||
cirrus,aux-output-source = <CS2000CP_AUX_OUTPUT_CLK_OUT>;
|
||||
};
|
||||
};
|
||||
@ -191,11 +191,4 @@ examples:
|
||||
};
|
||||
};
|
||||
|
||||
/* Consumer referencing the 5P49V5923 pin OUT1 */
|
||||
consumer {
|
||||
/* ... */
|
||||
clocks = <&vc5 1>;
|
||||
/* ... */
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
@ -40,12 +40,3 @@ examples:
|
||||
compatible = "fsl,imx1-ccm";
|
||||
reg = <0x0021b000 0x1000>;
|
||||
};
|
||||
|
||||
pwm@208000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx1-pwm";
|
||||
reg = <0x00208000 0x1000>;
|
||||
interrupts = <34>;
|
||||
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
@ -40,12 +40,3 @@ examples:
|
||||
reg = <0x10027000 0x800>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@1000a000 {
|
||||
compatible = "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX21_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
@ -83,12 +83,3 @@ examples:
|
||||
reg = <0x80040000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@8006c000 {
|
||||
compatible = "fsl,imx23-auart";
|
||||
reg = <0x8006c000 0x2000>;
|
||||
interrupts = <24>;
|
||||
clocks = <&clks 32>;
|
||||
dmas = <&dma_apbx 6>, <&dma_apbx 7>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
@ -176,11 +176,3 @@ examples:
|
||||
interrupts = <31>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@43f90000 {
|
||||
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
|
||||
reg = <0x43f90000 0x4000>;
|
||||
interrupts = <45>;
|
||||
clocks = <&clks 79>, <&clks 50>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
@ -44,12 +44,3 @@ examples:
|
||||
interrupts = <31>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
@ -106,12 +106,3 @@ examples:
|
||||
reg = <0x80040000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@8006a000 {
|
||||
compatible = "fsl,imx28-auart";
|
||||
reg = <0x8006a000 0x2000>;
|
||||
interrupts = <112>;
|
||||
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
|
||||
dma-names = "rx", "tx";
|
||||
clocks = <&clks 45>;
|
||||
};
|
||||
|
||||
@ -110,11 +110,3 @@ examples:
|
||||
interrupts = <31>, <53>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@43f90000 {
|
||||
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
||||
reg = <0x43f90000 0x4000>;
|
||||
interrupts = <45>;
|
||||
clocks = <&clks 10>, <&clks 30>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
@ -129,11 +129,3 @@ examples:
|
||||
interrupts = <31>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mmc@53fb4000 {
|
||||
compatible = "fsl,imx35-esdhc";
|
||||
reg = <0x53fb4000 0x4000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&clks 9>, <&clks 8>, <&clks 43>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
};
|
||||
|
||||
@ -108,14 +108,3 @@ examples:
|
||||
"upll", "sosc_bus_clk", "firc_bus_clk",
|
||||
"rosc", "spll_bus_clk";
|
||||
};
|
||||
|
||||
mmc@40380000 {
|
||||
compatible = "fsl,imx7ulp-usdhc";
|
||||
reg = <0x40380000 0x10000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&pcc2 IMX7ULP_CLK_USDHC1>;
|
||||
clock-names ="ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
@ -86,14 +86,3 @@ examples:
|
||||
"firc", "upll";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mmc@40380000 {
|
||||
compatible = "fsl,imx7ulp-usdhc";
|
||||
reg = <0x40380000 0x10000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
|
||||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&pcc2 IMX7ULP_CLK_USDHC1>;
|
||||
clock-names ="ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
@ -55,8 +55,6 @@ allOf:
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 25m osc
|
||||
@ -66,8 +64,6 @@ allOf:
|
||||
- description: ext3 clock input
|
||||
- description: ext4 clock input
|
||||
clock-names:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
items:
|
||||
- const: ckil
|
||||
- const: osc_25m
|
||||
|
||||
@ -101,14 +101,3 @@ examples:
|
||||
"sdhc0_lpcg_ahb_clk";
|
||||
power-domains = <&pd IMX_SC_R_SDHC_0>;
|
||||
};
|
||||
|
||||
mmc@5b010000 {
|
||||
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
|
||||
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x5b010000 0x10000>;
|
||||
clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
|
||||
<&sdhc0_lpcg IMX_LPCG_CLK_5>,
|
||||
<&sdhc0_lpcg IMX_LPCG_CLK_0>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
power-domains = <&pd IMX_SC_R_SDHC_0>;
|
||||
};
|
||||
|
||||
62
Bindings/clock/imx93-clock.yaml
Normal file
62
Bindings/clock/imx93-clock.yaml
Normal file
@ -0,0 +1,62 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx93-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX93 Clock Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
|
||||
description: |
|
||||
i.MX93 clock control module is an integrated clock controller, which
|
||||
includes clock generator, clock gate and supplies to all modules.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx93-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
description:
|
||||
specify the external clocks used by the CCM module.
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 24m osc
|
||||
- description: ext1 clock input
|
||||
|
||||
clock-names:
|
||||
description:
|
||||
specify the external clocks names used by the CCM module.
|
||||
items:
|
||||
- const: osc_32k
|
||||
- const: osc_24m
|
||||
- const: clk_ext1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
See include/dt-bindings/clock/imx93-clock.h for the full list of
|
||||
i.MX93 clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
clock-controller@44450000 {
|
||||
compatible = "fsl,imx93-ccm";
|
||||
reg = <0x44450000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
59
Bindings/clock/imxrt1050-clock.yaml
Normal file
59
Bindings/clock/imxrt1050-clock.yaml
Normal file
@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imxrt1050-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MXRT
|
||||
|
||||
maintainers:
|
||||
- Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||
- Jesse Taube <Mr.Bossman075@gmail.com>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imxrt*-clock.h
|
||||
for the full list of i.MXRT clock IDs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imxrt1050-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
description: 24m osc
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: osc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imxrt1050-clock.h>
|
||||
|
||||
clks: clock-controller@400fc000 {
|
||||
compatible = "fsl,imxrt1050-ccm";
|
||||
reg = <0x400fc000 0x4000>;
|
||||
interrupts = <95>, <96>;
|
||||
clocks = <&osc>;
|
||||
clock-names = "osc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
35
Bindings/clock/intel,stratix10.yaml
Normal file
35
Bindings/clock/intel,stratix10.yaml
Normal file
@ -0,0 +1,35 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Intel SoCFPGA Stratix10 platform clock controller binding
|
||||
|
||||
maintainers:
|
||||
- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: intel,stratix10-clkmgr
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@ffd10000 {
|
||||
compatible = "intel,stratix10-clkmgr";
|
||||
reg = <0xffd10000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
59
Bindings/clock/marvell,armada-3700-uart-clock.yaml
Normal file
59
Bindings/clock/marvell,armada-3700-uart-clock.yaml
Normal file
@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Marvell Armada 3720 UART clocks
|
||||
|
||||
maintainers:
|
||||
- Pali Rohár <pali@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,armada-3700-uart-clock
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: UART Clock Control Register
|
||||
- description: UART 2 Baud Rate Divisor Register
|
||||
|
||||
clocks:
|
||||
description: |
|
||||
List of parent clocks suitable for UART from following set:
|
||||
"TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
|
||||
UART clock can use one from this set and when more are provided
|
||||
then kernel would choose and configure the most suitable one.
|
||||
It is suggest to specify at least one TBG clock to achieve
|
||||
baudrates above 230400 and also to specify clock which bootloader
|
||||
used for UART (most probably xtal) for smooth boot log on UART.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: TBG-A-P
|
||||
- const: TBG-B-P
|
||||
- const: TBG-A-S
|
||||
- const: TBG-B-S
|
||||
- const: xtal
|
||||
minItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
uartclk: clock-controller@12010 {
|
||||
compatible = "marvell,armada-3700-uart-clock";
|
||||
reg = <0x12010 0x4>, <0x12210 0x4>;
|
||||
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>;
|
||||
clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -22,6 +22,11 @@ description: |
|
||||
|
||||
The clocks are provided inside a system controller node.
|
||||
|
||||
This node is also a reset provider for all the peripherals.
|
||||
|
||||
Reset related bits are defined in:
|
||||
[2]: <include/dt-bindings/reset/mt7621-reset.h>.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
@ -37,6 +42,12 @@ properties:
|
||||
clocks.
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
description:
|
||||
The first cell indicates the reset bit within the register, see
|
||||
[2] for available resets.
|
||||
const: 1
|
||||
|
||||
ralink,memctl:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
@ -61,6 +72,7 @@ examples:
|
||||
compatible = "mediatek,mt7621-sysc", "syscon";
|
||||
reg = <0x0 0x100>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
ralink,memctl = <&memc>;
|
||||
clock-output-names = "xtal", "cpu", "bus",
|
||||
"50m", "125m", "150m",
|
||||
|
||||
67
Bindings/clock/microchip,mpfs.yaml
Normal file
67
Bindings/clock/microchip,mpfs.yaml
Normal file
@ -0,0 +1,67 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip PolarFire Clock Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Daire McNamara <daire.mcnamara@microchip.com>
|
||||
|
||||
description: |
|
||||
Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
|
||||
which gates and enables all peripheral clocks.
|
||||
|
||||
This device tree binding describes 33 gate clocks. Clocks are referenced by
|
||||
user nodes by the CLKCFG node phandle and the clock index in the group, from
|
||||
0 to 32.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: microchip,mpfs-clkcfg
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: |
|
||||
clock config registers:
|
||||
These registers contain enable, reset & divider tables for the, cpu,
|
||||
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
|
||||
for the peripheral clocks.
|
||||
- description: |
|
||||
mss pll dri registers:
|
||||
Block of registers responsible for dynamic reconfiguration of the mss
|
||||
pll
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
|
||||
for the full list of PolarFire clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock Config node:
|
||||
- |
|
||||
#include <dt-bindings/clock/microchip,mpfs-clock.h>
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
clkcfg: clock-controller@20002000 {
|
||||
compatible = "microchip,mpfs-clkcfg";
|
||||
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
|
||||
clocks = <&ref>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
45
Bindings/clock/mstar,msc313-cpupll.yaml
Normal file
45
Bindings/clock/mstar,msc313-cpupll.yaml
Normal file
@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MStar/Sigmastar MSC313 CPU PLL
|
||||
|
||||
maintainers:
|
||||
- Daniel Palmer <daniel@thingy.jp>
|
||||
|
||||
description: |
|
||||
The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable
|
||||
PLL that can be used as the clock source for the CPU(s).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mstar,msc313-cpupll
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mstar-msc313-mpll.h>
|
||||
cpupll: cpupll@206400 {
|
||||
compatible = "mstar,msc313-cpupll";
|
||||
reg = <0x206400 0x200>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
|
||||
};
|
||||
@ -106,10 +106,3 @@ examples:
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
usb-controller@c5004000 {
|
||||
compatible = "nvidia,tegra20-ehci";
|
||||
reg = <0xc5004000 0x4000>;
|
||||
clocks = <&car TEGRA124_CLK_USB2>;
|
||||
resets = <&car TEGRA124_CLK_USB2>;
|
||||
};
|
||||
|
||||
@ -97,10 +97,3 @@ examples:
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
};
|
||||
|
||||
usb-controller@c5004000 {
|
||||
compatible = "nvidia,tegra20-ehci";
|
||||
reg = <0xc5004000 0x4000>;
|
||||
clocks = <&car TEGRA20_CLK_USB2>;
|
||||
resets = <&car TEGRA20_CLK_USB2>;
|
||||
};
|
||||
|
||||
@ -10,7 +10,7 @@ maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
|
||||
The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
|
||||
frequency clock to the CPU.
|
||||
|
||||
properties:
|
||||
|
||||
87
Bindings/clock/qcom,dispcc-sm6125.yaml
Normal file
87
Bindings/clock/qcom,dispcc-sm6125.yaml
Normal file
@ -0,0 +1,87 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock Controller Binding for SM6125
|
||||
|
||||
maintainers:
|
||||
- Martin Botka <martin.botka@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks and
|
||||
power domains on SM6125.
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/qcom,dispcc-sm6125.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm6125-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY1
|
||||
- description: Link clock from DP PHY
|
||||
- description: VCO DIV clock from DP PHY
|
||||
- description: AHB config clock from GCC
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: dsi0_phy_pll_out_byteclk
|
||||
- const: dsi0_phy_pll_out_dsiclk
|
||||
- const: dsi1_phy_pll_out_dsiclk
|
||||
- const: dp_phy_pll_link_clk
|
||||
- const: dp_phy_pll_vco_div_clk
|
||||
- const: cfg_ahb_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
|
||||
clock-controller@5f00000 {
|
||||
compatible = "qcom,sm6125-dispcc";
|
||||
reg = <0x5f00000 0x20000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>,
|
||||
<&gcc GCC_DISP_AHB_CLK>;
|
||||
clock-names = "bi_tcxo",
|
||||
"dsi0_phy_pll_out_byteclk",
|
||||
"dsi0_phy_pll_out_dsiclk",
|
||||
"dsi1_phy_pll_out_dsiclk",
|
||||
"dp_phy_pll_link_clk",
|
||||
"dp_phy_pll_vco_div_clk",
|
||||
"cfg_ahb_clk";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
86
Bindings/clock/qcom,dispcc-sm6350.yaml
Normal file
86
Bindings/clock/qcom,dispcc-sm6350.yaml
Normal file
@ -0,0 +1,86 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SM6350
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SM6350.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-sm6350.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6350-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: Byte clock from DSI PHY
|
||||
- description: Pixel clock from DSI PHY
|
||||
- description: Link clock from DP PHY
|
||||
- description: VCO DIV clock from DP PHY
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_disp_gpll0_clk
|
||||
- const: dsi0_phy_pll_out_byteclk
|
||||
- const: dsi0_phy_pll_out_dsiclk
|
||||
- const: dp_phy_pll_link_clk
|
||||
- const: dp_phy_pll_vco_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sm6350.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sm6350-dispcc";
|
||||
reg = <0x0af00000 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK>,
|
||||
<&dsi_phy 0>,
|
||||
<&dsi_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_disp_gpll0_clk",
|
||||
"dsi0_phy_pll_out_byteclk",
|
||||
"dsi0_phy_pll_out_dsiclk",
|
||||
"dp_phy_pll_link_clk",
|
||||
"dp_phy_pll_vco_div_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
@ -17,22 +20,12 @@ description: |
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8960.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8960.h
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-apq8064
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
const: qcom,gcc-apq8084
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
@ -53,21 +46,13 @@ properties:
|
||||
'#thermal-sensor-cells':
|
||||
const: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
- nvmem-cells
|
||||
- nvmem-cell-names
|
||||
- '#thermal-sensor-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
76
Bindings/clock/qcom,gcc-ipq8064.yaml
Normal file
76
Bindings/clock/qcom,gcc-ipq8064.yaml
Normal file
@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
maintainers:
|
||||
- Ansuel Smith <ansuelsmth@gmail.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on IPQ8064.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,gcc-ipq8064
|
||||
- const: syscon
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: PXO source
|
||||
- description: CXO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pxo
|
||||
- const: cxo
|
||||
|
||||
thermal-sensor:
|
||||
type: object
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/thermal/qcom-tsens.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
gcc: clock-controller@900000 {
|
||||
compatible = "qcom,gcc-ipq8064", "syscon";
|
||||
reg = <0x00900000 0x4000>;
|
||||
clocks = <&pxo_board>, <&cxo_board>;
|
||||
clock-names = "pxo", "cxo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
tsens: thermal-sensor {
|
||||
compatible = "qcom,ipq8064-tsens";
|
||||
|
||||
nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
|
||||
nvmem-cell-names = "calib", "calib_backup";
|
||||
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uplow";
|
||||
|
||||
#qcom,sensors = <11>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
70
Bindings/clock/qcom,gcc-other.yaml
Normal file
70
Bindings/clock/qcom,gcc-other.yaml
Normal file
@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/clock/qcom,gcc-mdm9607.h
|
||||
- dt-bindings/clock/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/reset/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,gcc.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-mdm9607
|
||||
- qcom,gcc-msm8226
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8939
|
||||
- qcom,gcc-msm8953
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
- qcom,gcc-mdm9615
|
||||
- qcom,gcc-sdm630
|
||||
- qcom,gcc-sdm660
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8960:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -4,57 +4,17 @@
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding
|
||||
title: Qualcomm Global Clock & Reset Controller Binding Common Bindings
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/clock/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8939.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/clock/qcom,gcc-mdm9607.h
|
||||
- dt-bindings/clock/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/reset/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
|
||||
Common bindings for Qualcomm global clock control module which supports
|
||||
the clocks, resets and power domains.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-apq8084
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-ipq8064
|
||||
- qcom,gcc-mdm9607
|
||||
- qcom,gcc-msm8226
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8939
|
||||
- qcom,gcc-msm8953
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
- qcom,gcc-mdm9615
|
||||
- qcom,gcc-sdm630
|
||||
- qcom,gcc-sdm660
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
@ -72,22 +32,11 @@ properties:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8960:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
||||
@ -17,6 +17,7 @@ description: |
|
||||
dt-bindings/clock/qcom,gpucc-sdm845.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7180.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7280.h
|
||||
dt-bindings/clock/qcom,gpucc-sm6350.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8150.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8250.h
|
||||
|
||||
@ -27,6 +28,7 @@ properties:
|
||||
- qcom,sc7180-gpucc
|
||||
- qcom,sc7280-gpucc
|
||||
- qcom,sc8180x-gpucc
|
||||
- qcom,sm6350-gpucc
|
||||
- qcom,sm8150-gpucc
|
||||
- qcom,sm8250-gpucc
|
||||
|
||||
|
||||
@ -19,6 +19,7 @@ properties:
|
||||
enum:
|
||||
- qcom,mmcc-apq8064
|
||||
- qcom,mmcc-apq8084
|
||||
- qcom,mmcc-msm8226
|
||||
- qcom,mmcc-msm8660
|
||||
- qcom,mmcc-msm8960
|
||||
- qcom,mmcc-msm8974
|
||||
|
||||
87
Bindings/clock/qcom,qcm2290-dispcc.yaml
Normal file
87
Bindings/clock/qcom,qcm2290-dispcc.yaml
Normal file
@ -0,0 +1,87 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for qcm2290
|
||||
|
||||
maintainers:
|
||||
- Loic Poulain <loic.poulain@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on qcm2290.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-qcm2290.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,qcm2290-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active-only XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: GPLL0 div source from GCC
|
||||
- description: Byte clock from DSI PHY
|
||||
- description: Pixel clock from DSI PHY
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: gcc_disp_gpll0_clk_src
|
||||
- const: gcc_disp_gpll0_div_clk_src
|
||||
- const: dsi0_phy_pll_out_byteclk
|
||||
- const: dsi0_phy_pll_out_dsiclk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
clock-controller@5f00000 {
|
||||
compatible = "qcom,qcm2290-dispcc";
|
||||
reg = <0x5f00000 0x20000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
"bi_tcxo_ao",
|
||||
"gcc_disp_gpll0_clk_src",
|
||||
"gcc_disp_gpll0_div_clk_src",
|
||||
"dsi0_phy_pll_out_byteclk",
|
||||
"dsi0_phy_pll_out_dsiclk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -20,6 +20,7 @@ properties:
|
||||
- qcom,sc7180-rpmh-clk
|
||||
- qcom,sc7280-rpmh-clk
|
||||
- qcom,sc8180x-rpmh-clk
|
||||
- qcom,sc8280xp-rpmh-clk
|
||||
- qcom,sdm845-rpmh-clk
|
||||
- qcom,sdx55-rpmh-clk
|
||||
- qcom,sdx65-rpmh-clk
|
||||
|
||||
65
Bindings/clock/qcom,sdm845-camcc.yaml
Normal file
65
Bindings/clock/qcom,sdm845-camcc.yaml
Normal file
@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller Binding for SDM845
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module which supports the clocks, resets and
|
||||
power domains on SDM845.
|
||||
|
||||
See also dt-bindings/clock/qcom,camcc-sm845.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-camcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@ad00000 {
|
||||
compatible = "qcom,sdm845-camcc";
|
||||
reg = <0x0ad00000 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
97
Bindings/clock/renesas,9series.yaml
Normal file
97
Bindings/clock/renesas,9series.yaml
Normal file
@ -0,0 +1,97 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,9series.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for Renesas 9-series I2C PCIe clock generators
|
||||
|
||||
description: |
|
||||
The Renesas 9-series are I2C PCIe clock generators providing
|
||||
from 1 to 20 output clocks.
|
||||
|
||||
When referencing the provided clock in the DT using phandle
|
||||
and clock specifier, the following mapping applies:
|
||||
|
||||
- 9FGV0241:
|
||||
0 -- DIF0
|
||||
1 -- DIF1
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,9fgv0241
|
||||
|
||||
reg:
|
||||
description: I2C device address
|
||||
enum: [ 0x68, 0x6a ]
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XTal input clock
|
||||
|
||||
renesas,out-amplitude-microvolt:
|
||||
enum: [ 600000, 700000, 800000, 900000 ]
|
||||
description: Output clock signal amplitude
|
||||
|
||||
renesas,out-spread-spectrum:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 100000, 99750, 99500 ]
|
||||
description: Output clock down spread in pcm (1/1000 of percent)
|
||||
|
||||
patternProperties:
|
||||
"^DIF[0-19]$":
|
||||
type: object
|
||||
description:
|
||||
Description of one of the outputs (DIF0..DIF19).
|
||||
|
||||
properties:
|
||||
renesas,slew-rate:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 2000000, 3000000 ]
|
||||
description: Output clock slew rate select in V/ns
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
/* 25MHz reference crystal */
|
||||
ref25: ref25m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
i2c@0 {
|
||||
reg = <0x0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rs9: clock-generator@6a {
|
||||
compatible = "renesas,9fgv0241";
|
||||
reg = <0x6a>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&ref25m>;
|
||||
|
||||
DIF0 {
|
||||
renesas,slew-rate = <3000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -51,6 +51,18 @@ additionalProperties: false
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a73a4-clock.h>
|
||||
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a73a4-cpg-clocks";
|
||||
reg = <0xe6150000 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0", "pll1", "pll2",
|
||||
"pll2s", "pll2h", "z", "z2",
|
||||
"i", "m3", "b", "m1", "m2",
|
||||
"zx", "zs", "hp";
|
||||
};
|
||||
|
||||
sdhi2_clk: sdhi2_clk@e615007c {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615007c 4>;
|
||||
|
||||
@ -4,13 +4,13 @@
|
||||
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
|
||||
title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description: |
|
||||
On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
|
||||
On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
|
||||
Standby Mode share the same register block.
|
||||
|
||||
They provide the following functionalities:
|
||||
@ -22,7 +22,9 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
|
||||
enum:
|
||||
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-cpg # RZ/V2L
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -40,9 +42,9 @@ properties:
|
||||
description: |
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/r9a07g044-cpg.h>
|
||||
<dt-bindings/clock/r9a07g*-cpg.h>
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
|
||||
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
|
||||
const: 2
|
||||
|
||||
'#power-domain-cells':
|
||||
@ -56,7 +58,7 @@ properties:
|
||||
'#reset-cells':
|
||||
description:
|
||||
The single reset specifier cell must be the module number, as defined in
|
||||
the <dt-bindings/clock/r9a07g044-cpg.h>.
|
||||
the <dt-bindings/clock/r9a07g0*-cpg.h>.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
|
||||
@ -8,7 +8,7 @@ title: Samsung Exynos SoC Audio SubSystem clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
@ -8,7 +8,7 @@ title: Samsung Exynos SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
@ -8,7 +8,7 @@ title: Samsung SoC external/osc/XXTI/XusbXTI clock
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
@ -8,7 +8,7 @@ title: Samsung Exynos4412 SoC ISP clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
@ -8,7 +8,7 @@ title: Samsung Exynos5260 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
@ -8,7 +8,7 @@ title: Samsung Exynos5410 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
@ -8,7 +8,7 @@ title: Samsung Exynos5433 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
@ -8,7 +8,7 @@ title: Samsung Exynos7 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
@ -9,7 +9,7 @@ title: Samsung Exynos7885 SoC clock controller
|
||||
maintainers:
|
||||
- Dávid Virág <virag.david003@gmail.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
@ -9,7 +9,7 @@ title: Samsung Exynos850 SoC clock controller
|
||||
maintainers:
|
||||
- Sam Protsenko <semen.protsenko@linaro.org>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Samsung S2M and S5M family clock generator block
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description: |
|
||||
This is a part of device tree bindings for S2M and S5M family of Power
|
||||
|
||||
@ -8,7 +8,7 @@ title: Samsung S5Pv210 SoC Audio SubSystem clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
@ -8,7 +8,7 @@ title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
- Tomasz Figa <tomasz.figa@gmail.com>
|
||||
|
||||
|
||||
57
Bindings/clock/starfive,jh7100-audclk.yaml
Normal file
57
Bindings/clock/starfive,jh7100-audclk.yaml
Normal file
@ -0,0 +1,57 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive JH7100 Audio Clock Generator
|
||||
|
||||
maintainers:
|
||||
- Emil Renner Berthing <kernel@esmil.dk>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: starfive,jh7100-audclk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Audio source clock
|
||||
- description: External 12.288MHz clock
|
||||
- description: Domain 7 AHB bus clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: audio_src
|
||||
- const: audio_12288
|
||||
- const: dom7ahb_bus
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
See <dt-bindings/clock/starfive-jh7100-audio.h> for valid indices.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/starfive-jh7100.h>
|
||||
|
||||
clock-controller@10480000 {
|
||||
compatible = "starfive,jh7100-audclk";
|
||||
reg = <0x10480000 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
|
||||
<&clkgen JH7100_CLK_AUDIO_12288>,
|
||||
<&clkgen JH7100_CLK_DOM7AHB_BUS>;
|
||||
clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
198
Bindings/clock/tesla,fsd-clock.yaml
Normal file
198
Bindings/clock/tesla,fsd-clock.yaml
Normal file
@ -0,0 +1,198 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Tesla FSD (Full Self-Driving) SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Alim Akhtar <alim.akhtar@samsung.com>
|
||||
- linux-fsd@tesla.com
|
||||
|
||||
description: |
|
||||
FSD clock controller consist of several clock management unit
|
||||
(CMU), which generates clocks for various inteernal SoC blocks.
|
||||
The root clock comes from external OSC clock (24 MHz).
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
'dt-bindings/clock/fsd-clk.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- tesla,fsd-clock-cmu
|
||||
- tesla,fsd-clock-imem
|
||||
- tesla,fsd-clock-peric
|
||||
- tesla,fsd-clock-fsys0
|
||||
- tesla,fsd-clock-fsys1
|
||||
- tesla,fsd-clock-mfc
|
||||
- tesla,fsd-clock-cam_csi
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-cmu
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-imem
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
- description: IMEM TCU clock (from CMU_CMU)
|
||||
- description: IMEM bus clock (from CMU_CMU)
|
||||
- description: IMEM DMA clock (from CMU_CMU)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_cmu_imem_tcuclk
|
||||
- const: dout_cmu_imem_aclk
|
||||
- const: dout_cmu_imem_dmaclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-peric
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
- description: Shared0 PLL div4 clock (from CMU_CMU)
|
||||
- description: PERIC shared1 div36 clock (from CMU_CMU)
|
||||
- description: PERIC shared0 div3 TBU clock (from CMU_CMU)
|
||||
- description: PERIC shared0 div20 clock (from CMU_CMU)
|
||||
- description: PERIC shared1 div4 DMAclock (from CMU_CMU)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_cmu_pll_shared0_div4
|
||||
- const: dout_cmu_peric_shared1div36
|
||||
- const: dout_cmu_peric_shared0div3_tbuclk
|
||||
- const: dout_cmu_peric_shared0div20
|
||||
- const: dout_cmu_peric_shared1div4_dmaclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-fsys0
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
- description: Shared0 PLL div6 clock (from CMU_CMU)
|
||||
- description: FSYS0 shared1 div4 clock (from CMU_CMU)
|
||||
- description: FSYS0 shared0 div4 clock (from CMU_CMU)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_cmu_pll_shared0_div6
|
||||
- const: dout_cmu_fsys0_shared1div4
|
||||
- const: dout_cmu_fsys0_shared0div4
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-fsys1
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
- description: FSYS1 shared0 div8 clock (from CMU_CMU)
|
||||
- description: FSYS1 shared0 div4 clock (from CMU_CMU)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
- const: dout_cmu_fsys1_shared0div8
|
||||
- const: dout_cmu_fsys1_shared0div4
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-mfc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: tesla,fsd-clock-cam_csi
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (24 MHz)
|
||||
clock-names:
|
||||
items:
|
||||
- const: fin_pll
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node for CMU_FSYS1
|
||||
- |
|
||||
#include <dt-bindings/clock/fsd-clk.h>
|
||||
|
||||
clock_fsys1: clock-controller@16810000 {
|
||||
compatible = "tesla,fsd-clock-fsys1";
|
||||
reg = <0x16810000 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&fin_pll>,
|
||||
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
|
||||
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
|
||||
clock-names = "fin_pll",
|
||||
"dout_cmu_fsys1_shared0div8",
|
||||
"dout_cmu_fsys1_shared0div4";
|
||||
};
|
||||
|
||||
...
|
||||
51
Bindings/clock/ti/ti,clksel.yaml
Normal file
51
Bindings/clock/ti/ti,clksel.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Binding for TI clksel clock
|
||||
|
||||
maintainers:
|
||||
- Tony Lindgren <tony@atomide.com>
|
||||
|
||||
description: |
|
||||
The TI CLKSEL clocks consist of consist of input clock mux bits, and in some
|
||||
cases also has divider, multiplier and gate bits.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,clksel
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: The CLKSEL register range
|
||||
|
||||
'#address-cells':
|
||||
enum: [ 0, 1, 2 ]
|
||||
|
||||
'#size-cells':
|
||||
enum: [ 0, 1, 2 ]
|
||||
|
||||
ranges: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
description: The CLKSEL register and bit offset
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
|
||||
examples:
|
||||
- |
|
||||
clksel_gfx_fclk: clock@52c {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x25c 0x4>;
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
...
|
||||
@ -104,8 +104,7 @@ properties:
|
||||
- "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB
|
||||
Type-C Cable and Connector specification, when Power Delivery is not
|
||||
supported.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/string
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
enum:
|
||||
- default
|
||||
- 1.5A
|
||||
|
||||
855
Bindings/cpu/idle-states.yaml
Normal file
855
Bindings/cpu/idle-states.yaml
Normal file
@ -0,0 +1,855 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpu/idle-states.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Idle states binding description
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
- Anup Patel <anup@brainfault.org>
|
||||
|
||||
description: |+
|
||||
==========================================
|
||||
1 - Introduction
|
||||
==========================================
|
||||
|
||||
ARM and RISC-V systems contain HW capable of managing power consumption
|
||||
dynamically, where cores can be put in different low-power states (ranging
|
||||
from simple wfi to power gating) according to OS PM policies. The CPU states
|
||||
representing the range of dynamic idle states that a processor can enter at
|
||||
run-time, can be specified through device tree bindings representing the
|
||||
parameters required to enter/exit specific idle states on a given processor.
|
||||
|
||||
==========================================
|
||||
2 - ARM idle states
|
||||
==========================================
|
||||
|
||||
According to the Server Base System Architecture document (SBSA, [3]), the
|
||||
power states an ARM CPU can be put into are identified by the following list:
|
||||
|
||||
- Running
|
||||
- Idle_standby
|
||||
- Idle_retention
|
||||
- Sleep
|
||||
- Off
|
||||
|
||||
The power states described in the SBSA document define the basic CPU states on
|
||||
top of which ARM platforms implement power management schemes that allow an OS
|
||||
PM implementation to put the processor in different idle states (which include
|
||||
states listed above; "off" state is not an idle state since it does not have
|
||||
wake-up capabilities, hence it is not considered in this document).
|
||||
|
||||
Idle state parameters (e.g. entry latency) are platform specific and need to
|
||||
be characterized with bindings that provide the required information to OS PM
|
||||
code so that it can build the required tables and use them at runtime.
|
||||
|
||||
The device tree binding definition for ARM idle states is the subject of this
|
||||
document.
|
||||
|
||||
==========================================
|
||||
3 - RISC-V idle states
|
||||
==========================================
|
||||
|
||||
On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
|
||||
suspend (or idle) states (ranging from simple WFI, power gating, etc). The
|
||||
RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
|
||||
standard mechanism for OS to request HART state transitions.
|
||||
|
||||
The platform specific suspend (or idle) states of a hart can be either
|
||||
retentive or non-rententive in nature. A retentive suspend state will
|
||||
preserve HART registers and CSR values for all privilege modes whereas
|
||||
a non-retentive suspend state will not preserve HART registers and CSR
|
||||
values.
|
||||
|
||||
===========================================
|
||||
4 - idle-states definitions
|
||||
===========================================
|
||||
|
||||
Idle states are characterized for a specific system through a set of
|
||||
timing and energy related properties, that underline the HW behaviour
|
||||
triggered upon idle states entry and exit.
|
||||
|
||||
The following diagram depicts the CPU execution phases and related timing
|
||||
properties required to enter and exit an idle state:
|
||||
|
||||
..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
|
||||
| | | | |
|
||||
|
||||
|<------ entry ------->|
|
||||
| latency |
|
||||
|<- exit ->|
|
||||
| latency |
|
||||
|<-------- min-residency -------->|
|
||||
|<------- wakeup-latency ------->|
|
||||
|
||||
Diagram 1: CPU idle state execution phases
|
||||
|
||||
EXEC: Normal CPU execution.
|
||||
|
||||
PREP: Preparation phase before committing the hardware to idle mode
|
||||
like cache flushing. This is abortable on pending wake-up
|
||||
event conditions. The abort latency is assumed to be negligible
|
||||
(i.e. less than the ENTRY + EXIT duration). If aborted, CPU
|
||||
goes back to EXEC. This phase is optional. If not abortable,
|
||||
this should be included in the ENTRY phase instead.
|
||||
|
||||
ENTRY: The hardware is committed to idle mode. This period must run
|
||||
to completion up to IDLE before anything else can happen.
|
||||
|
||||
IDLE: This is the actual energy-saving idle period. This may last
|
||||
between 0 and infinite time, until a wake-up event occurs.
|
||||
|
||||
EXIT: Period during which the CPU is brought back to operational
|
||||
mode (EXEC).
|
||||
|
||||
entry-latency: Worst case latency required to enter the idle state. The
|
||||
exit-latency may be guaranteed only after entry-latency has passed.
|
||||
|
||||
min-residency: Minimum period, including preparation and entry, for a given
|
||||
idle state to be worthwhile energywise.
|
||||
|
||||
wakeup-latency: Maximum delay between the signaling of a wake-up event and the
|
||||
CPU being able to execute normal code again. If not specified, this is assumed
|
||||
to be entry-latency + exit-latency.
|
||||
|
||||
These timing parameters can be used by an OS in different circumstances.
|
||||
|
||||
An idle CPU requires the expected min-residency time to select the most
|
||||
appropriate idle state based on the expected expiry time of the next IRQ
|
||||
(i.e. wake-up) that causes the CPU to return to the EXEC phase.
|
||||
|
||||
An operating system scheduler may need to compute the shortest wake-up delay
|
||||
for CPUs in the system by detecting how long will it take to get a CPU out
|
||||
of an idle state, e.g.:
|
||||
|
||||
wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
|
||||
|
||||
In other words, the scheduler can make its scheduling decision by selecting
|
||||
(e.g. waking-up) the CPU with the shortest wake-up delay.
|
||||
The wake-up delay must take into account the entry latency if that period
|
||||
has not expired. The abortable nature of the PREP period can be ignored
|
||||
if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
|
||||
the worst case since it depends on the CPU operating conditions, i.e. caches
|
||||
state).
|
||||
|
||||
An OS has to reliably probe the wakeup-latency since some devices can enforce
|
||||
latency constraint guarantees to work properly, so the OS has to detect the
|
||||
worst case wake-up latency it can incur if a CPU is allowed to enter an
|
||||
idle state, and possibly to prevent that to guarantee reliable device
|
||||
functioning.
|
||||
|
||||
The min-residency time parameter deserves further explanation since it is
|
||||
expressed in time units but must factor in energy consumption coefficients.
|
||||
|
||||
The energy consumption of a cpu when it enters a power state can be roughly
|
||||
characterised by the following graph:
|
||||
|
||||
|
|
||||
|
|
||||
|
|
||||
e |
|
||||
n | /---
|
||||
e | /------
|
||||
r | /------
|
||||
g | /-----
|
||||
y | /------
|
||||
| ----
|
||||
| /|
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
|/ |
|
||||
-----|-------+----------------------------------
|
||||
0| 1 time(ms)
|
||||
|
||||
Graph 1: Energy vs time example
|
||||
|
||||
The graph is split in two parts delimited by time 1ms on the X-axis.
|
||||
The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
|
||||
and denotes the energy costs incurred while entering and leaving the idle
|
||||
state.
|
||||
The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
|
||||
shallower slope and essentially represents the energy consumption of the idle
|
||||
state.
|
||||
|
||||
min-residency is defined for a given idle state as the minimum expected
|
||||
residency time for a state (inclusive of preparation and entry) after
|
||||
which choosing that state become the most energy efficient option. A good
|
||||
way to visualise this, is by taking the same graph above and comparing some
|
||||
states energy consumptions plots.
|
||||
|
||||
For sake of simplicity, let's consider a system with two idle states IDLE1,
|
||||
and IDLE2:
|
||||
|
||||
|
|
||||
|
|
||||
|
|
||||
| /-- IDLE1
|
||||
e | /---
|
||||
n | /----
|
||||
e | /---
|
||||
r | /-----/--------- IDLE2
|
||||
g | /-------/---------
|
||||
y | ------------ /---|
|
||||
| / /---- |
|
||||
| / /--- |
|
||||
| / /---- |
|
||||
| / /--- |
|
||||
| --- |
|
||||
| / |
|
||||
| / |
|
||||
|/ | time
|
||||
---/----------------------------+------------------------
|
||||
|IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
|
||||
|
|
||||
IDLE2-min-residency
|
||||
|
||||
Graph 2: idle states min-residency example
|
||||
|
||||
In graph 2 above, that takes into account idle states entry/exit energy
|
||||
costs, it is clear that if the idle state residency time (i.e. time till next
|
||||
wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
|
||||
choice energywise.
|
||||
|
||||
This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
|
||||
than IDLE2.
|
||||
|
||||
However, the lower power consumption (i.e. shallower energy curve slope) of
|
||||
idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
|
||||
efficient.
|
||||
|
||||
The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
|
||||
shallower states in a system with multiple idle states) is defined
|
||||
IDLE2-min-residency and corresponds to the time when energy consumption of
|
||||
IDLE1 and IDLE2 states breaks even.
|
||||
|
||||
The definitions provided in this section underpin the idle states
|
||||
properties specification that is the subject of the following sections.
|
||||
|
||||
===========================================
|
||||
5 - idle-states node
|
||||
===========================================
|
||||
|
||||
The processor idle states are defined within the idle-states node, which is
|
||||
a direct child of the cpus node [1] and provides a container where the
|
||||
processor idle states, defined as device tree nodes, are listed.
|
||||
|
||||
On ARM systems, it is a container of processor idle states nodes. If the
|
||||
system does not provide CPU power management capabilities, or the processor
|
||||
just supports idle_standby, an idle-states node is not required.
|
||||
|
||||
===========================================
|
||||
6 - References
|
||||
===========================================
|
||||
|
||||
[1] ARM Linux Kernel documentation - CPUs bindings
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml
|
||||
|
||||
[2] ARM Linux Kernel documentation - PSCI bindings
|
||||
Documentation/devicetree/bindings/arm/psci.yaml
|
||||
|
||||
[3] ARM Server Base System Architecture (SBSA)
|
||||
http://infocenter.arm.com/help/index.jsp
|
||||
|
||||
[4] ARM Architecture Reference Manuals
|
||||
http://infocenter.arm.com/help/index.jsp
|
||||
|
||||
[5] ARM Linux Kernel documentation - Booting AArch64 Linux
|
||||
Documentation/arm64/booting.rst
|
||||
|
||||
[6] RISC-V Linux Kernel documentation - CPUs bindings
|
||||
Documentation/devicetree/bindings/riscv/cpus.yaml
|
||||
|
||||
[7] RISC-V Supervisor Binary Interface (SBI)
|
||||
http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: idle-states
|
||||
|
||||
entry-method:
|
||||
description: |
|
||||
Usage and definition depend on ARM architecture version.
|
||||
|
||||
On ARM v8 64-bit this property is required.
|
||||
On ARM 32-bit systems this property is optional
|
||||
|
||||
This assumes that the "enable-method" property is set to "psci" in the cpu
|
||||
node[5] that is responsible for setting up CPU idle management in the OS
|
||||
implementation.
|
||||
const: psci
|
||||
|
||||
patternProperties:
|
||||
"^(cpu|cluster)-":
|
||||
type: object
|
||||
description: |
|
||||
Each state node represents an idle state description and must be defined
|
||||
as follows.
|
||||
|
||||
The idle state entered by executing the wfi instruction (idle_standby
|
||||
SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and
|
||||
therefore must not be listed.
|
||||
|
||||
In addition to the properties listed above, a state node may require
|
||||
additional properties specific to the entry-method defined in the
|
||||
idle-states node. Please refer to the entry-method bindings
|
||||
documentation for properties definitions.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- arm,idle-state
|
||||
- riscv,idle-state
|
||||
|
||||
arm,psci-suspend-param:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
power_state parameter to pass to the ARM PSCI suspend call.
|
||||
|
||||
Device tree nodes that require usage of PSCI CPU_SUSPEND function
|
||||
(i.e. idle states node with entry-method property is set to "psci")
|
||||
must specify this property.
|
||||
|
||||
riscv,sbi-suspend-param:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
suspend_type parameter to pass to the RISC-V SBI HSM suspend call.
|
||||
|
||||
This property is required in idle state nodes of device tree meant
|
||||
for RISC-V systems. For more details on the suspend_type parameter
|
||||
refer the SBI specifiation v0.3 (or higher) [7].
|
||||
|
||||
local-timer-stop:
|
||||
description:
|
||||
If present the CPU local timer control logic is
|
||||
lost on state entry, otherwise it is retained.
|
||||
type: boolean
|
||||
|
||||
entry-latency-us:
|
||||
description:
|
||||
Worst case latency in microseconds required to enter the idle state.
|
||||
|
||||
exit-latency-us:
|
||||
description:
|
||||
Worst case latency in microseconds required to exit the idle state.
|
||||
The exit-latency-us duration may be guaranteed only after
|
||||
entry-latency-us has passed.
|
||||
|
||||
min-residency-us:
|
||||
description:
|
||||
Minimum residency duration in microseconds, inclusive of preparation
|
||||
and entry, for this idle state to be considered worthwhile energy wise
|
||||
(refer to section 2 of this document for a complete description).
|
||||
|
||||
wakeup-latency-us:
|
||||
description: |
|
||||
Maximum delay between the signaling of a wake-up event and the CPU
|
||||
being able to execute normal code again. If omitted, this is assumed
|
||||
to be equal to:
|
||||
|
||||
entry-latency-us + exit-latency-us
|
||||
|
||||
It is important to supply this value on systems where the duration of
|
||||
PREP phase (see diagram 1, section 2) is non-neglibigle. In such
|
||||
systems entry-latency-us + exit-latency-us will exceed
|
||||
wakeup-latency-us by this duration.
|
||||
|
||||
idle-state-name:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description:
|
||||
A string used as a descriptive name for the idle state.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- entry-latency-us
|
||||
- exit-latency-us
|
||||
- min-residency-us
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <2>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
|
||||
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
|
||||
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
|
||||
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
|
||||
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
|
||||
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
|
||||
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
|
||||
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
|
||||
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@100000000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
|
||||
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100000001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
|
||||
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100000100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
|
||||
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100000101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
|
||||
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
|
||||
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
|
||||
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
|
||||
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
|
||||
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_RETENTION_0_0: cpu-retention-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <20>;
|
||||
exit-latency-us = <40>;
|
||||
min-residency-us = <80>;
|
||||
};
|
||||
|
||||
CLUSTER_RETENTION_0: cluster-retention-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <50>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <250>;
|
||||
wakeup-latency-us = <130>;
|
||||
};
|
||||
|
||||
CPU_SLEEP_0_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <250>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <950>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <600>;
|
||||
exit-latency-us = <1100>;
|
||||
min-residency-us = <2700>;
|
||||
wakeup-latency-us = <1500>;
|
||||
};
|
||||
|
||||
CPU_RETENTION_1_0: cpu-retention-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <20>;
|
||||
exit-latency-us = <40>;
|
||||
min-residency-us = <90>;
|
||||
};
|
||||
|
||||
CLUSTER_RETENTION_1: cluster-retention-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <50>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <270>;
|
||||
wakeup-latency-us = <100>;
|
||||
};
|
||||
|
||||
CPU_SLEEP_1_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <70>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <300>;
|
||||
wakeup-latency-us = <150>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_1: cluster-sleep-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <500>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <3500>;
|
||||
wakeup-latency-us = <1300>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 2 (ARM 32-bit, 8-cpu system, two clusters):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
|
||||
};
|
||||
|
||||
cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
|
||||
};
|
||||
|
||||
cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
cpu_sleep_0_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <200>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <400>;
|
||||
wakeup-latency-us = <250>;
|
||||
};
|
||||
|
||||
cluster_sleep_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <500>;
|
||||
exit-latency-us = <1500>;
|
||||
min-residency-us = <2500>;
|
||||
wakeup-latency-us = <1700>;
|
||||
};
|
||||
|
||||
cpu_sleep_1_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <900>;
|
||||
wakeup-latency-us = <600>;
|
||||
};
|
||||
|
||||
cluster_sleep_1: cluster-sleep-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <800>;
|
||||
exit-latency-us = <2000>;
|
||||
min-residency-us = <6500>;
|
||||
wakeup-latency-us = <2300>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "riscv";
|
||||
reg = <0x0>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
mmu-type = "riscv,sv48";
|
||||
cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
|
||||
<&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
|
||||
|
||||
cpu_intc0: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "riscv";
|
||||
reg = <0x1>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
mmu-type = "riscv,sv48";
|
||||
cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
|
||||
<&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
|
||||
|
||||
cpu_intc1: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu@10 {
|
||||
device_type = "cpu";
|
||||
compatible = "riscv";
|
||||
reg = <0x10>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
mmu-type = "riscv,sv48";
|
||||
cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
|
||||
<&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
|
||||
|
||||
cpu_intc10: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu@11 {
|
||||
device_type = "cpu";
|
||||
compatible = "riscv";
|
||||
reg = <0x11>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
mmu-type = "riscv,sv48";
|
||||
cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
|
||||
<&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
|
||||
|
||||
cpu_intc11: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
CPU_RET_0_0: cpu-retentive-0-0 {
|
||||
compatible = "riscv,idle-state";
|
||||
riscv,sbi-suspend-param = <0x10000000>;
|
||||
entry-latency-us = <20>;
|
||||
exit-latency-us = <40>;
|
||||
min-residency-us = <80>;
|
||||
};
|
||||
|
||||
CPU_NONRET_0_0: cpu-nonretentive-0-0 {
|
||||
compatible = "riscv,idle-state";
|
||||
riscv,sbi-suspend-param = <0x90000000>;
|
||||
entry-latency-us = <250>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <950>;
|
||||
};
|
||||
|
||||
CLUSTER_RET_0: cluster-retentive-0 {
|
||||
compatible = "riscv,idle-state";
|
||||
riscv,sbi-suspend-param = <0x11000000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <50>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <250>;
|
||||
wakeup-latency-us = <130>;
|
||||
};
|
||||
|
||||
CLUSTER_NONRET_0: cluster-nonretentive-0 {
|
||||
compatible = "riscv,idle-state";
|
||||
riscv,sbi-suspend-param = <0x91000000>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <600>;
|
||||
exit-latency-us = <1100>;
|
||||
min-residency-us = <2700>;
|
||||
wakeup-latency-us = <1500>;
|
||||
};
|
||||
|
||||
CPU_RET_1_0: cpu-retentive-1-0 {
|
||||
compatible = "riscv,idle-state";
|
||||
riscv,sbi-suspend-param = <0x10000010>;
|
||||
entry-latency-us = <20>;
|
||||
exit-latency-us = <40>;
|
||||
min-residency-us = <80>;
|
||||
};
|
||||
|
||||
CPU_NONRET_1_0: cpu-nonretentive-1-0 {
|
||||
compatible = "riscv,idle-state";
|
||||
riscv,sbi-suspend-param = <0x90000010>;
|
||||
entry-latency-us = <250>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <950>;
|
||||
};
|
||||
|
||||
CLUSTER_RET_1: cluster-retentive-1 {
|
||||
compatible = "riscv,idle-state";
|
||||
riscv,sbi-suspend-param = <0x11000010>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <50>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <250>;
|
||||
wakeup-latency-us = <130>;
|
||||
};
|
||||
|
||||
CLUSTER_NONRET_1: cluster-nonretentive-1 {
|
||||
compatible = "riscv,idle-state";
|
||||
riscv,sbi-suspend-param = <0x91000010>;
|
||||
local-timer-stop;
|
||||
entry-latency-us = <600>;
|
||||
exit-latency-us = <1100>;
|
||||
min-residency-us = <2700>;
|
||||
wakeup-latency-us = <1500>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
201
Bindings/cpufreq/cpufreq-qcom-hw.yaml
Normal file
201
Bindings/cpufreq/cpufreq-qcom-hw.yaml
Normal file
@ -0,0 +1,201 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. CPUFREQ
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description: |
|
||||
|
||||
CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
|
||||
SoCs to manage frequency in hardware. It is capable of controlling frequency
|
||||
for multiple clusters.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: v1 of CPUFREQ HW
|
||||
items:
|
||||
- const: qcom,cpufreq-hw
|
||||
|
||||
- description: v2 of CPUFREQ HW (EPSS)
|
||||
items:
|
||||
- enum:
|
||||
- qcom,sm8250-cpufreq-epss
|
||||
- const: qcom,cpufreq-epss
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: Frequency domain 0 register region
|
||||
- description: Frequency domain 1 register region
|
||||
- description: Frequency domain 2 register region
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: freq-domain0
|
||||
- const: freq-domain1
|
||||
- const: freq-domain2
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO Clock
|
||||
- description: GPLL0 Clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: alternate
|
||||
|
||||
'#freq-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#freq-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
// Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
|
||||
// switch DCVS state together.
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
L3_0: l3-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_100>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_100: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU2: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x200>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_200>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_200: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x300>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_300>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
L2_300: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU4: cpu@400 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x400>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_400>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_400: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU5: cpu@500 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x500>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_500>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_500: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU6: cpu@600 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x600>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_600>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_600: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU7: cpu@700 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo385";
|
||||
reg = <0x0 0x700>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&L2_700>;
|
||||
qcom,freq-domain = <&cpufreq_hw 1>;
|
||||
L2_700: l2-cache {
|
||||
compatible = "cache";
|
||||
next-level-cache = <&L3_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpufreq@17d43000 {
|
||||
compatible = "qcom,cpufreq-hw";
|
||||
reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
|
||||
reg-names = "freq-domain0", "freq-domain1";
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
|
||||
#freq-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
166
Bindings/cpufreq/qcom-cpufreq-nvmem.yaml
Normal file
166
Bindings/cpufreq/qcom-cpufreq-nvmem.yaml
Normal file
@ -0,0 +1,166 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings
|
||||
|
||||
maintainers:
|
||||
- Ilia Lin <ilia.lin@kernel.org>
|
||||
|
||||
description: |
|
||||
In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
|
||||
voltage is dynamically configured by Core Power Reduction (CPR) depending on
|
||||
current CPU frequency and efuse values.
|
||||
CPR provides a power domain with multiple levels that are selected depending
|
||||
on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
|
||||
according to the required OPPs defined in the CPU OPP tables.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,qcs404
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
cpus:
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
'cpu@[0-9a-f]+':
|
||||
type: object
|
||||
|
||||
properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: cpr
|
||||
|
||||
required:
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
|
||||
patternProperties:
|
||||
'^opp-table(-[a-z0-9]+)?$':
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
const: operating-points-v2-kryo-cpu
|
||||
then:
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
required:
|
||||
- required-opps
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. QCS404";
|
||||
compatible = "qcom,qcs404";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU1: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU2: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x102>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU3: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x103>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
};
|
||||
|
||||
cpu_opp_table: opp-table-cpu {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
opp-shared;
|
||||
|
||||
opp-1094400000 {
|
||||
opp-hz = /bits/ 64 <1094400000>;
|
||||
required-opps = <&cpr_opp1>;
|
||||
};
|
||||
opp-1248000000 {
|
||||
opp-hz = /bits/ 64 <1248000000>;
|
||||
required-opps = <&cpr_opp2>;
|
||||
};
|
||||
opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
required-opps = <&cpr_opp3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpr_opp_table: opp-table-cpr {
|
||||
compatible = "operating-points-v2-qcom-level";
|
||||
|
||||
cpr_opp1: opp1 {
|
||||
opp-level = <1>;
|
||||
qcom,opp-fuse-level = <1>;
|
||||
};
|
||||
cpr_opp2: opp2 {
|
||||
opp-level = <2>;
|
||||
qcom,opp-fuse-level = <2>;
|
||||
};
|
||||
cpr_opp3: opp3 {
|
||||
opp-level = <3>;
|
||||
qcom,opp-fuse-level = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
66
Bindings/crypto/atmel,at91sam9g46-aes.yaml
Normal file
66
Bindings/crypto/atmel,at91sam9g46-aes.yaml
Normal file
@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-aes.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator
|
||||
|
||||
maintainers:
|
||||
- Tudor Ambarus <tudor.ambarus@microchip.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,at91sam9g46-aes
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: aes_clk
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: TX DMA Channel
|
||||
- description: RX DMA Channel
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: tx
|
||||
- const: rx
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- dmas
|
||||
- dma-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
#include <dt-bindings/dma/at91.h>
|
||||
|
||||
aes: crypto@e1810000 {
|
||||
compatible = "atmel,at91sam9g46-aes";
|
||||
reg = <0xe1810000 0x100>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
|
||||
clock-names = "aes_clk";
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
|
||||
<&dma0 AT91_XDMAC_DT_PERID(2)>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
60
Bindings/crypto/atmel,at91sam9g46-sha.yaml
Normal file
60
Bindings/crypto/atmel,at91sam9g46-sha.yaml
Normal file
@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator
|
||||
|
||||
maintainers:
|
||||
- Tudor Ambarus <tudor.ambarus@microchip.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,at91sam9g46-sha
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: sha_clk
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
description: TX DMA Channel
|
||||
|
||||
dma-names:
|
||||
const: tx
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
#include <dt-bindings/dma/at91.h>
|
||||
|
||||
sha: crypto@e1814000 {
|
||||
compatible = "atmel,at91sam9g46-sha";
|
||||
reg = <0xe1814000 0x100>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
|
||||
clock-names = "sha_clk";
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
64
Bindings/crypto/atmel,at91sam9g46-tdes.yaml
Normal file
64
Bindings/crypto/atmel,at91sam9g46-tdes.yaml
Normal file
@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-tdes.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel Triple Data Encryption Standard (TDES) HW cryptographic accelerator
|
||||
|
||||
maintainers:
|
||||
- Tudor Ambarus <tudor.ambarus@microchip.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,at91sam9g46-tdes
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: tdes_clk
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: TX DMA Channel
|
||||
- description: RX DMA Channel
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: tx
|
||||
- const: rx
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/at91.h>
|
||||
#include <dt-bindings/dma/at91.h>
|
||||
|
||||
tdes: crypto@e2014000 {
|
||||
compatible = "atmel,at91sam9g46-tdes";
|
||||
reg = <0xe2014000 0x100>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
|
||||
clock-names = "tdes_clk";
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
|
||||
<&dma0 AT91_XDMAC_DT_PERID(53)>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user