Adapt libstand's setjmp/longjmp MIPS support to be portable across 32-bit
and 64-bit MIPS. Don't use the floating-point coprocessor in the libstand context for MIPS. Reviewed by: imp MFC after: 3 days Sponsored by: DARPA, AFRL
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=249553
@ -59,33 +59,20 @@
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LEAF(_setjmp)
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.set noreorder
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li v0, 0xACEDBADE # sigcontext magic number
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sw ra, (2 * 4)(a0) # sc_pc = return address
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sw v0, (3 * 4)(a0) # saved in sc_regs[0]
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sw s0, ((S0 + 3) * 4)(a0)
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sw s1, ((S1 + 3) * 4)(a0)
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sw s2, ((S2 + 3) * 4)(a0)
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sw s3, ((S3 + 3) * 4)(a0)
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sw s4, ((S4 + 3) * 4)(a0)
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sw s5, ((S5 + 3) * 4)(a0)
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sw s6, ((S6 + 3) * 4)(a0)
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sw s7, ((S7 + 3) * 4)(a0)
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sw sp, ((SP + 3) * 4)(a0)
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sw s8, ((S8 + 3) * 4)(a0)
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cfc1 v0, $31 # too bad cant check if FP used
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swc1 $f20, ((20 + 38) * 4)(a0)
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swc1 $f21, ((21 + 38) * 4)(a0)
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swc1 $f22, ((22 + 38) * 4)(a0)
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swc1 $f23, ((23 + 38) * 4)(a0)
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swc1 $f24, ((24 + 38) * 4)(a0)
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swc1 $f25, ((25 + 38) * 4)(a0)
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swc1 $f26, ((26 + 38) * 4)(a0)
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swc1 $f27, ((27 + 38) * 4)(a0)
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swc1 $f28, ((28 + 38) * 4)(a0)
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swc1 $f29, ((29 + 38) * 4)(a0)
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swc1 $f30, ((30 + 38) * 4)(a0)
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swc1 $f31, ((31 + 38) * 4)(a0)
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sw v0, ((32 + 38) * 4)(a0)
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REG_LI v0, 0xACEDBADE # sigcontext magic number
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REG_S ra, (2 * SZREG)(a0) # sc_pc = return address
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REG_S v0, (3 * SZREG)(a0) # saved in sc_regs[0]
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REG_S s0, ((S0 + 3) * SZREG)(a0)
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REG_S s1, ((S1 + 3) * SZREG)(a0)
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REG_S s2, ((S2 + 3) * SZREG)(a0)
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REG_S s3, ((S3 + 3) * SZREG)(a0)
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REG_S s4, ((S4 + 3) * SZREG)(a0)
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REG_S s5, ((S5 + 3) * SZREG)(a0)
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REG_S s6, ((S6 + 3) * SZREG)(a0)
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REG_S s7, ((S7 + 3) * SZREG)(a0)
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REG_S sp, ((SP + 3) * SZREG)(a0)
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REG_S s8, ((S8 + 3) * SZREG)(a0)
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REG_S v0, ((32 + 38) * SZREG)(a0)
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j ra
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move v0, zero
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END(_setjmp)
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@ -96,38 +83,22 @@ LEAF(_longjmp)
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.cprestore 16
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#endif
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.set noreorder
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lw v0, (3 * 4)(a0) # get magic number
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lw ra, (2 * 4)(a0)
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REG_L v0, (3 * SZREG)(a0) # get magic number
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REG_L ra, (2 * SZREG)(a0)
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bne v0, 0xACEDBADE, botch # jump if error
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addu sp, sp, 32 # does not matter, sanity
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lw s0, ((S0 + 3) * 4)(a0)
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lw s1, ((S1 + 3) * 4)(a0)
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lw s2, ((S2 + 3) * 4)(a0)
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lw s3, ((S3 + 3) * 4)(a0)
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lw s4, ((S4 + 3) * 4)(a0)
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lw s5, ((S5 + 3) * 4)(a0)
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lw s6, ((S6 + 3) * 4)(a0)
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lw s7, ((S7 + 3) * 4)(a0)
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lw v0, ((32 + 38) * 4)(a0) # get fpu status
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lw sp, ((SP + 3) * 4)(a0)
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lw s8, ((S8 + 3) * 4)(a0)
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/* Octeon does not have an FPU */
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#if !defined(_MIPS_ARCH_OCTEON)
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ctc1 v0, $31
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lwc1 $f20, ((20 + 38) * 4)(a0)
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lwc1 $f21, ((21 + 38) * 4)(a0)
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lwc1 $f22, ((22 + 38) * 4)(a0)
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lwc1 $f23, ((23 + 38) * 4)(a0)
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lwc1 $f24, ((24 + 38) * 4)(a0)
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lwc1 $f25, ((25 + 38) * 4)(a0)
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lwc1 $f26, ((26 + 38) * 4)(a0)
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lwc1 $f27, ((27 + 38) * 4)(a0)
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lwc1 $f28, ((28 + 38) * 4)(a0)
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lwc1 $f29, ((29 + 38) * 4)(a0)
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lwc1 $f30, ((30 + 38) * 4)(a0)
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lwc1 $f31, ((31 + 38) * 4)(a0)
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#endif /* _MIPS_ARCH_OCTEON */
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REG_L s0, ((S0 + 3) * SZREG)(a0)
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REG_L s1, ((S1 + 3) * SZREG)(a0)
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REG_L s2, ((S2 + 3) * SZREG)(a0)
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REG_L s3, ((S3 + 3) * SZREG)(a0)
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REG_L s4, ((S4 + 3) * SZREG)(a0)
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REG_L s5, ((S5 + 3) * SZREG)(a0)
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REG_L s6, ((S6 + 3) * SZREG)(a0)
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REG_L s7, ((S7 + 3) * SZREG)(a0)
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REG_L v0, ((32 + 38) * SZREG)(a0) # get fpu status
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REG_L sp, ((SP + 3) * SZREG)(a0)
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REG_L s8, ((S8 + 3) * SZREG)(a0)
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j ra
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move v0, a1
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