From 92d8df2f371180f8b5e8def13831024d136bd682 Mon Sep 17 00:00:00 2001 From: Konstantin Belousov Date: Thu, 2 Jul 2020 10:44:45 +0000 Subject: [PATCH] mlx5_core: remove unneccessary LFENCE instruction. Use fence instead of barrier, which is optimized to take advantage of the x86 TSO memory model. Reviewed by: hselasky Sponsored by: Mellanox Technologies MFC after: 1 week --- sys/dev/mlx5/mlx5_core/mlx5_eq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/dev/mlx5/mlx5_core/mlx5_eq.c b/sys/dev/mlx5/mlx5_core/mlx5_eq.c index 7c4d2323d37a..144496c9d3a2 100644 --- a/sys/dev/mlx5/mlx5_core/mlx5_eq.c +++ b/sys/dev/mlx5/mlx5_core/mlx5_eq.c @@ -240,7 +240,7 @@ static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) * Make sure we read EQ entry contents after we've * checked the ownership bit. */ - rmb(); + atomic_thread_fence_acq(); mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", eq->eqn, eqe_type_str(eqe->type));