Remove arm1136 support. We don't have any configs that use it, and I don't
expect us to add support for any more arm11 SoCs.
This commit is contained in:
parent
9a25f3e847
commit
930798f3a1
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=280824
@ -557,69 +557,6 @@ struct cpu_functions fa526_cpufuncs = {
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};
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#endif /* CPU_FA526 || CPU_FA626TE */
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#if defined(CPU_ARM1136)
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struct cpu_functions arm1136_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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cpufunc_nullop, /* cpwait */
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/* MMU functions */
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cpufunc_control, /* control */
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cpufunc_domains, /* Domain */
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arm11x6_setttb, /* Setttb */
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cpufunc_faultstatus, /* Faultstatus */
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cpufunc_faultaddress, /* Faultaddress */
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/* TLB functions */
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arm11_tlb_flushID, /* tlb_flushID */
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arm11_tlb_flushID_SE, /* tlb_flushID_SE */
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arm11_tlb_flushI, /* tlb_flushI */
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arm11_tlb_flushI_SE, /* tlb_flushI_SE */
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arm11_tlb_flushD, /* tlb_flushD */
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arm11_tlb_flushD_SE, /* tlb_flushD_SE */
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/* Cache operations */
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arm11x6_icache_sync_all, /* icache_sync_all */
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arm11x6_icache_sync_range, /* icache_sync_range */
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arm11x6_dcache_wbinv_all, /* dcache_wbinv_all */
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armv6_dcache_wbinv_range, /* dcache_wbinv_range */
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armv6_dcache_inv_range, /* dcache_inv_range */
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armv6_dcache_wb_range, /* dcache_wb_range */
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armv6_idcache_inv_all, /* idcache_inv_all */
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arm11x6_idcache_wbinv_all, /* idcache_wbinv_all */
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arm11x6_idcache_wbinv_range, /* idcache_wbinv_range */
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(void *)cpufunc_nullop, /* l2cache_wbinv_all */
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(void *)cpufunc_nullop, /* l2cache_wbinv_range */
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(void *)cpufunc_nullop, /* l2cache_inv_range */
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(void *)cpufunc_nullop, /* l2cache_wb_range */
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(void *)cpufunc_nullop, /* l2cache_drain_writebuf */
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/* Other functions */
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arm11x6_flush_prefetchbuf, /* flush_prefetchbuf */
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arm11_drain_writebuf, /* drain_writebuf */
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cpufunc_nullop, /* flush_brnchtgt_C */
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(void *)cpufunc_nullop, /* flush_brnchtgt_E */
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arm11_sleep, /* sleep */
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/* Soft functions */
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cpufunc_null_fixup, /* dataabt_fixup */
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cpufunc_null_fixup, /* prefetchabt_fixup */
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arm11_context_switch, /* context_switch */
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arm11x6_setup /* cpu setup */
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};
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#endif /* CPU_ARM1136 */
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#if defined(CPU_ARM1176)
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struct cpu_functions arm1176_cpufuncs = {
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/* CPU functions */
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@ -765,7 +702,7 @@ u_int cputype;
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u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
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#if defined(CPU_ARM9) || \
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defined (CPU_ARM9E) || defined (CPU_ARM1136) || \
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defined (CPU_ARM9E) || \
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defined(CPU_ARM1176) || defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
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defined(CPU_FA526) || defined(CPU_FA626TE) || defined(CPU_MV_PJ4B) || \
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@ -959,19 +896,8 @@ set_cpufuncs()
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goto out;
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}
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#endif /* CPU_ARM9E */
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
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if (cputype == CPU_ID_ARM1136JS
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|| cputype == CPU_ID_ARM1136JSR1
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|| cputype == CPU_ID_ARM1176JZS) {
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#ifdef CPU_ARM1136
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if (cputype == CPU_ID_ARM1136JS
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|| cputype == CPU_ID_ARM1136JSR1)
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cpufuncs = arm1136_cpufuncs;
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#endif
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#ifdef CPU_ARM1176
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if (cputype == CPU_ID_ARM1176JZS)
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cpufuncs = arm1176_cpufuncs;
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#endif
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#if defined(CPU_ARM1176)
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if (cputype == CPU_ID_ARM1176JZS) {
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cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
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get_cachetype_cp15();
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@ -979,7 +905,7 @@ set_cpufuncs()
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goto out;
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}
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#endif /* CPU_ARM1136 || CPU_ARM1176 */
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#endif /* CPU_ARM1176 */
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#if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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if (cputype == CPU_ID_CORTEXA5 ||
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cputype == CPU_ID_CORTEXA7 ||
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@ -1238,7 +1164,7 @@ arm10_setup(void)
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}
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#endif /* CPU_ARM9E || CPU_ARM10 */
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176) \
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#if defined(CPU_ARM1176) \
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|| defined(CPU_MV_PJ4B) \
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|| defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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static __inline void
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@ -1250,7 +1176,7 @@ cpu_scc_setup_ccnt(void)
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* you want!
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*/
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#ifdef _PMC_USER_READ_WRITE_
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
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#if defined(CPU_ARM1176)
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/* Use the Secure User and Non-secure Access Validation Control Register
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* to allow userland access
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*/
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@ -1264,7 +1190,7 @@ cpu_scc_setup_ccnt(void)
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: "r"(0x00000001));
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#endif
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#endif
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
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#if defined(CPU_ARM1176)
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/* Set PMCR[2,0] to enable counters and reset CCNT */
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__asm volatile ("mcr p15, 0, %0, c15, c12, 0\n\t"
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:
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@ -1285,7 +1211,7 @@ cpu_scc_setup_ccnt(void)
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}
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#endif
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
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#if defined(CPU_ARM1176)
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void
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arm11x6_setup(void)
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{
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@ -1331,20 +1257,6 @@ arm11x6_setup(void)
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auxctrl = 0;
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auxctrl_wax = ~0;
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/*
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* This options enables the workaround for the 364296 ARM1136
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* r0pX errata (possible cache data corruption with
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* hit-under-miss enabled). It sets the undocumented bit 31 in
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* the auxiliary control register and the FI bit in the control
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* register, thus disabling hit-under-miss without putting the
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* processor into full low interrupt latency mode. ARM11MPCore
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* is not affected.
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*/
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if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1136JS) { /* ARM1136JSr0pX */
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cpuctrl |= CPU_CONTROL_FI_ENABLE;
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auxctrl = ARM1136_AUXCTL_PFI;
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auxctrl_wax = ~ARM1136_AUXCTL_PFI;
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}
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/*
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* Enable an errata workaround
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@ -1380,7 +1292,7 @@ arm11x6_setup(void)
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cpu_scc_setup_ccnt();
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}
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#endif /* CPU_ARM1136 || CPU_ARM1176 */
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#endif /* CPU_ARM1176 */
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#ifdef CPU_MV_PJ4B
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void
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@ -65,7 +65,7 @@ extern void fa526_idcache_wbinv_all(void);
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#elif defined(CPU_ARM9E)
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#define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all
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extern void armv5_ec_idcache_wbinv_all(void);
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#elif defined(CPU_ARM1136) || defined(CPU_ARM1176)
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#elif defined(CPU_ARM1176)
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#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
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#elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
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@ -52,8 +52,6 @@
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*/
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#define CPU_NTYPES (defined(CPU_ARM9) + \
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defined(CPU_ARM9E) + \
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defined(CPU_ARM10) + \
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defined(CPU_ARM1136) + \
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defined(CPU_ARM1176) + \
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defined(CPU_XSCALE_80200) + \
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defined(CPU_XSCALE_80321) + \
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@ -85,7 +83,7 @@
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#endif
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#if !defined(ARM_ARCH_6)
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
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#if defined(CPU_ARM1176)
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#define ARM_ARCH_6 1
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#else
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#define ARM_ARCH_6 0
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@ -158,7 +156,7 @@
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#define ARM_MMU_GENERIC 0
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#endif
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
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#if defined(CPU_ARM1176)
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#define ARM_MMU_V6 1
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#else
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#define ARM_MMU_V6 0
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@ -386,7 +386,7 @@ void armadaxp_idcache_wbinv_all (void);
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void cortexa_setup (void);
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#endif
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
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#if defined(CPU_ARM1176)
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void arm11_tlb_flushID (void);
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void arm11_tlb_flushID_SE (u_int);
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void arm11_tlb_flushI (void);
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@ -414,10 +414,6 @@ void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void arm11x6_setup (void);
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void arm11x6_sleep (int); /* no ref. for errata */
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#endif
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#if defined(CPU_ARM1136)
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void arm11_sleep (int);
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void arm1136_sleep_rev0 (int); /* for errata 336501 */
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#endif
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#if defined(CPU_ARM9E)
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void armv5_ec_setttb(u_int);
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@ -58,7 +58,7 @@
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#define NIRQ 1020
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#elif defined(CPU_KRAIT)
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#define NIRQ 288
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#elif defined(CPU_ARM1136) || defined(CPU_ARM1176)
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#elif defined(CPU_ARM1176)
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#define NIRQ 128
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#elif defined(SOC_MV_ARMADAXP)
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#define MAIN_IRQ_NUM 116
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@ -10,7 +10,6 @@ ARM_WANT_TP_ADDRESS opt_global.h
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COUNTS_PER_SEC opt_timer.h
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CPU_ARM9 opt_global.h
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CPU_ARM9E opt_global.h
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CPU_ARM1136 opt_global.h
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CPU_ARM1176 opt_global.h
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CPU_CORTEXA opt_global.h
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CPU_KRAIT opt_global.h
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