Import DTS files from Linux 5.6
This commit is contained in:
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/vendor/device-tree/dist/; revision=359928 svn path=/vendor/device-tree/5.6/; revision=359929; tag=vendor/device-tree/5.6
@ -59,6 +59,7 @@ properties:
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- friendlyarm,nanopi-k2
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- hardkernel,odroid-c2
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- nexbox,a95x
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- videostrong,kii-pro
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- wetek,hub
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- wetek,play2
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- const: amlogic,meson-gxbb
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@ -104,6 +105,7 @@ properties:
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- enum:
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- amlogic,p230
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- amlogic,p231
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- libretech,aml-s905d-pc
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- phicomm,n1
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- const: amlogic,s905d
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- const: amlogic,meson-gxl
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@ -115,6 +117,7 @@ properties:
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- amlogic,q201
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- khadas,vim2
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- kingnovel,r-box-pro
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- libretech,aml-s912-pc
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- nexbox,a1
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- tronsmart,vega-s96
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- const: amlogic,s912
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@ -102,7 +102,7 @@ Required sub-node properties:
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/power/power-domain.yaml
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[3] Documentation/devicetree/bindings/thermal/thermal.txt
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[4] Documentation/devicetree/bindings/sram/sram.txt
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[4] Documentation/devicetree/bindings/sram/sram.yaml
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[5] Documentation/devicetree/bindings/reset/reset.txt
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Example:
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@ -109,7 +109,7 @@ Required properties:
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[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/thermal/thermal.txt
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[3] Documentation/devicetree/bindings/sram/sram.txt
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[3] Documentation/devicetree/bindings/sram/sram.yaml
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[4] Documentation/devicetree/bindings/power/power-domain.yaml
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Example:
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@ -121,7 +121,7 @@ Required properties (in root node):
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Required nodes:
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- soc: some node of the RealView platforms must be the SoC
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node that contain the SoC-specific devices, withe the compatible
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node that contain the SoC-specific devices, with the compatible
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string set to one of these tuples:
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"arm,realview-eb-soc", "simple-bus"
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"arm,realview-pb1176-soc", "simple-bus"
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@ -35,6 +35,16 @@ properties:
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- atmel,at91sam9x60
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- const: atmel,at91sam9
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- items:
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- enum:
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- overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board
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- overkiz,kizboxmini-mb # Overkiz kizbox Mini Mother Board
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- overkiz,kizboxmini-rd # Overkiz kizbox Mini RailDIN
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- overkiz,smartkiz # Overkiz SmartKiz Board
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- const: atmel,at91sam9g25
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- const: atmel,at91sam9x5
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- const: atmel,at91sam9
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- items:
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- enum:
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- atmel,at91sam9g15
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@ -52,11 +62,32 @@ properties:
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- const: atmel,sama5d2
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- const: atmel,sama5
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- description: Microchip SAMA5D27 WLSOM1
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items:
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- const: microchip,sama5d27-wlsom1
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- const: atmel,sama5d27
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- const: atmel,sama5d2
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- const: atmel,sama5
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- description: Microchip SAMA5D27 WLSOM1 Evaluation Kit
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items:
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- const: microchip,sama5d27-wlsom1-ek
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- const: microchip,sama5d27-wlsom1
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- const: atmel,sama5d27
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- const: atmel,sama5d2
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- const: atmel,sama5
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- items:
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- const: atmel,sama5d27
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- const: atmel,sama5d2
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- const: atmel,sama5
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- description: SAM9X60-EK board
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items:
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- const: microchip,sam9x60ek
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- const: microchip,sam9x60
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- const: atmel,at91sam9
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- description: Nattis v2 board with Natte v2 power board
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items:
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- const: axentia,nattis-2
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@ -10,6 +10,12 @@ PIT Timer required properties:
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- interrupts: Should contain interrupt for the PIT which is the IRQ line
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shared across all System Controller members.
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PIT64B Timer required properties:
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- compatible: Should be "microchip,sam9x60-pit64b"
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- reg: Should contain registers location and length
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- interrupts: Should contain interrupt for PIT64B timer
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- clocks: Should contain the available clock sources for PIT64B timer.
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System Timer (ST) required properties:
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- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
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- reg: Should contain registers location and length
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@ -39,6 +45,7 @@ RAMC SDRAM/DDR Controller required properties:
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"atmel,at91sam9260-sdramc",
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"atmel,at91sam9g45-ddramc",
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"atmel,sama5d3-ddramc",
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"microchip,sam9x60-ddramc"
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- reg: Should contain registers location and length
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Examples:
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@ -62,7 +62,7 @@ Timer node:
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Syscon reboot node:
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See Documentation/devicetree/bindings/power/reset/syscon-reboot.txt for the
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See Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the
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detailed list of properties, the two values defined below are specific to the
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BCM6328-style timer:
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@ -216,7 +216,7 @@ properties:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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description: |
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List of phandles to idle state nodes supported
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by this cpu (see ./idle-states.txt).
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by this cpu (see ./idle-states.yaml).
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capacity-dmips-mhz:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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@ -242,6 +242,21 @@ properties:
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where voltage is in V, frequency is in MHz.
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power-domains:
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$ref: '/schemas/types.yaml#/definitions/phandle-array'
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description:
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List of phandles and PM domain specifiers, as defined by bindings of the
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PM domain provider (see also ../power_domain.txt).
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power-domain-names:
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$ref: '/schemas/types.yaml#/definitions/string-array'
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description:
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A list of power domain name strings sorted in the same order as the
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power-domains property.
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For PSCI based platforms, the name corresponding to the index of the PSCI
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PM domain provider, must be "psci".
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qcom,saw:
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$ref: '/schemas/types.yaml#/definitions/phandle'
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description: |
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/arm/fsl.yaml#
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$id: http://devicetree.org/schemas/arm/fsl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX Platforms Device Tree Bindings
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@ -128,6 +128,27 @@ properties:
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- variscite,dt6customboard
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- const: fsl,imx6q
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- description: i.MX6Q Gateworks Ventana Boards
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items:
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- enum:
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- gw,imx6q-gw51xx
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- gw,imx6q-gw52xx
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- gw,imx6q-gw53xx
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- gw,imx6q-gw5400-a
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- gw,imx6q-gw54xx
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- gw,imx6q-gw551x
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- gw,imx6q-gw552x
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- gw,imx6q-gw553x
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- gw,imx6q-gw560x
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- gw,imx6q-gw5903
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- gw,imx6q-gw5904
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- gw,imx6q-gw5907
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- gw,imx6q-gw5910
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- gw,imx6q-gw5912
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- gw,imx6q-gw5913
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- const: gw,ventana
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- const: fsl,imx6q
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- description: i.MX6QP based Boards
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items:
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- enum:
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@ -139,7 +160,7 @@ properties:
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items:
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- enum:
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- armadeus,imx6dl-apf6 # APF6 (Solo) SoM
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- armadeus,imx6dl-apf6dldev # APF6 (Solo) SoM on APF6Dev board
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- armadeus,imx6dl-apf6dev # APF6 (Solo) SoM on APF6Dev board
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- eckelmann,imx6dl-ci4x10
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- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM
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- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base
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@ -154,10 +175,31 @@ properties:
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- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
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- const: fsl,imx6dl
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- description: i.MX6DL Gateworks Ventana Boards
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items:
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- enum:
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- gw,imx6dl-gw51xx
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- gw,imx6dl-gw52xx
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- gw,imx6dl-gw53xx
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- gw,imx6dl-gw54xx
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- gw,imx6dl-gw551x
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- gw,imx6dl-gw552x
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- gw,imx6dl-gw553x
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- gw,imx6dl-gw560x
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- gw,imx6dl-gw5903
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- gw,imx6dl-gw5904
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- gw,imx6dl-gw5907
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- gw,imx6dl-gw5910
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- gw,imx6dl-gw5912
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- gw,imx6dl-gw5913
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- const: gw,ventana
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- const: fsl,imx6dl
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- description: i.MX6SL based Boards
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items:
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- enum:
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- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
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- kobo,tolino-shine3
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- const: fsl,imx6sl
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- description: i.MX6SLL based Boards
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@ -172,6 +214,7 @@ properties:
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- enum:
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- fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board
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- fsl,imx6sx-sdb # i.MX6 SoloX SDB Board
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- fsl,imx6sx-sdb-reva # i.MX6 SoloX SDB Rev-A Board
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- const: fsl,imx6sx
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- description: i.MX6UL based Boards
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@ -239,6 +282,7 @@ properties:
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items:
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- enum:
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- fsl,imx7d-sdb # i.MX7 SabreSD Board
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- fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board
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- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
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- toradex,colibri-imx7d # Colibri iMX7 Dual Module
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- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
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@ -263,6 +307,7 @@ properties:
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- description: i.MX7ULP based Boards
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items:
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- enum:
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- ea,imx7ulp-com # i.MX7ULP Embedded Artists COM Board
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- fsl,imx7ulp-evk # i.MX7ULP Evaluation Kit
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- const: fsl,imx7ulp
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@ -283,7 +328,9 @@ properties:
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items:
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- enum:
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- boundary,imx8mq-nitrogen8m # i.MX8MQ NITROGEN Board
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- einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board
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- fsl,imx8mq-evk # i.MX8MQ EVK Board
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- google,imx8mq-phanbell # Google Coral Edge TPU
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- purism,librem5-devkit # Purism Librem5 devkit
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- solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse
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- technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
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@ -385,6 +432,13 @@ properties:
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- fsl,ls2088a-rdb
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- const: fsl,ls2088a
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- description: LX2160A based Boards
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items:
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- enum:
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- fsl,lx2160a-qds
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- fsl,lx2160a-rdb
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- const: fsl,lx2160a
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- description: S32V234 based Boards
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items:
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- enum:
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@ -1,7 +1,7 @@
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* Hisilicon Hi3519 System Controller Block
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This bindings use the following binding:
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Documentation/devicetree/bindings/mfd/syscon.txt
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Documentation/devicetree/bindings/mfd/syscon.yaml
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Required properties:
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- compatible: "hisilicon,hi3519-sysctrl".
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|
@ -1,706 +0,0 @@
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==========================================
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ARM idle states binding description
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==========================================
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==========================================
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1 - Introduction
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==========================================
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ARM systems contain HW capable of managing power consumption dynamically,
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where cores can be put in different low-power states (ranging from simple
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wfi to power gating) according to OS PM policies. The CPU states representing
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the range of dynamic idle states that a processor can enter at run-time, can be
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specified through device tree bindings representing the parameters required
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to enter/exit specific idle states on a given processor.
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According to the Server Base System Architecture document (SBSA, [3]), the
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power states an ARM CPU can be put into are identified by the following list:
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- Running
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- Idle_standby
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- Idle_retention
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- Sleep
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- Off
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The power states described in the SBSA document define the basic CPU states on
|
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top of which ARM platforms implement power management schemes that allow an OS
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PM implementation to put the processor in different idle states (which include
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states listed above; "off" state is not an idle state since it does not have
|
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wake-up capabilities, hence it is not considered in this document).
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Idle state parameters (e.g. entry latency) are platform specific and need to be
|
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characterized with bindings that provide the required information to OS PM
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code so that it can build the required tables and use them at runtime.
|
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The device tree binding definition for ARM idle states is the subject of this
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document.
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===========================================
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2 - idle-states definitions
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===========================================
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Idle states are characterized for a specific system through a set of
|
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timing and energy related properties, that underline the HW behaviour
|
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triggered upon idle states entry and exit.
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The following diagram depicts the CPU execution phases and related timing
|
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properties required to enter and exit an idle state:
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..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
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| | | | |
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||||
|
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|<------ entry ------->|
|
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| latency |
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|<- exit ->|
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| latency |
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|<-------- min-residency -------->|
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|<------- wakeup-latency ------->|
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|
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Diagram 1: CPU idle state execution phases
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EXEC: Normal CPU execution.
|
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|
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PREP: Preparation phase before committing the hardware to idle mode
|
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like cache flushing. This is abortable on pending wake-up
|
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event conditions. The abort latency is assumed to be negligible
|
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(i.e. less than the ENTRY + EXIT duration). If aborted, CPU
|
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goes back to EXEC. This phase is optional. If not abortable,
|
||||
this should be included in the ENTRY phase instead.
|
||||
|
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ENTRY: The hardware is committed to idle mode. This period must run
|
||||
to completion up to IDLE before anything else can happen.
|
||||
|
||||
IDLE: This is the actual energy-saving idle period. This may last
|
||||
between 0 and infinite time, until a wake-up event occurs.
|
||||
|
||||
EXIT: Period during which the CPU is brought back to operational
|
||||
mode (EXEC).
|
||||
|
||||
entry-latency: Worst case latency required to enter the idle state. The
|
||||
exit-latency may be guaranteed only after entry-latency has passed.
|
||||
|
||||
min-residency: Minimum period, including preparation and entry, for a given
|
||||
idle state to be worthwhile energywise.
|
||||
|
||||
wakeup-latency: Maximum delay between the signaling of a wake-up event and the
|
||||
CPU being able to execute normal code again. If not specified, this is assumed
|
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to be entry-latency + exit-latency.
|
||||
|
||||
These timing parameters can be used by an OS in different circumstances.
|
||||
|
||||
An idle CPU requires the expected min-residency time to select the most
|
||||
appropriate idle state based on the expected expiry time of the next IRQ
|
||||
(i.e. wake-up) that causes the CPU to return to the EXEC phase.
|
||||
|
||||
An operating system scheduler may need to compute the shortest wake-up delay
|
||||
for CPUs in the system by detecting how long will it take to get a CPU out
|
||||
of an idle state, e.g.:
|
||||
|
||||
wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
|
||||
|
||||
In other words, the scheduler can make its scheduling decision by selecting
|
||||
(e.g. waking-up) the CPU with the shortest wake-up delay.
|
||||
The wake-up delay must take into account the entry latency if that period
|
||||
has not expired. The abortable nature of the PREP period can be ignored
|
||||
if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
|
||||
the worst case since it depends on the CPU operating conditions, i.e. caches
|
||||
state).
|
||||
|
||||
An OS has to reliably probe the wakeup-latency since some devices can enforce
|
||||
latency constraint guarantees to work properly, so the OS has to detect the
|
||||
worst case wake-up latency it can incur if a CPU is allowed to enter an
|
||||
idle state, and possibly to prevent that to guarantee reliable device
|
||||
functioning.
|
||||
|
||||
The min-residency time parameter deserves further explanation since it is
|
||||
expressed in time units but must factor in energy consumption coefficients.
|
||||
|
||||
The energy consumption of a cpu when it enters a power state can be roughly
|
||||
characterised by the following graph:
|
||||
|
||||
|
|
||||
|
|
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|
|
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e |
|
||||
n | /---
|
||||
e | /------
|
||||
r | /------
|
||||
g | /-----
|
||||
y | /------
|
||||
| ----
|
||||
| /|
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
|/ |
|
||||
-----|-------+----------------------------------
|
||||
0| 1 time(ms)
|
||||
|
||||
Graph 1: Energy vs time example
|
||||
|
||||
The graph is split in two parts delimited by time 1ms on the X-axis.
|
||||
The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
|
||||
and denotes the energy costs incurred while entering and leaving the idle
|
||||
state.
|
||||
The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
|
||||
shallower slope and essentially represents the energy consumption of the idle
|
||||
state.
|
||||
|
||||
min-residency is defined for a given idle state as the minimum expected
|
||||
residency time for a state (inclusive of preparation and entry) after
|
||||
which choosing that state become the most energy efficient option. A good
|
||||
way to visualise this, is by taking the same graph above and comparing some
|
||||
states energy consumptions plots.
|
||||
|
||||
For sake of simplicity, let's consider a system with two idle states IDLE1,
|
||||
and IDLE2:
|
||||
|
||||
|
|
||||
|
|
||||
|
|
||||
| /-- IDLE1
|
||||
e | /---
|
||||
n | /----
|
||||
e | /---
|
||||
r | /-----/--------- IDLE2
|
||||
g | /-------/---------
|
||||
y | ------------ /---|
|
||||
| / /---- |
|
||||
| / /--- |
|
||||
| / /---- |
|
||||
| / /--- |
|
||||
| --- |
|
||||
| / |
|
||||
| / |
|
||||
|/ | time
|
||||
---/----------------------------+------------------------
|
||||
|IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
|
||||
|
|
||||
IDLE2-min-residency
|
||||
|
||||
Graph 2: idle states min-residency example
|
||||
|
||||
In graph 2 above, that takes into account idle states entry/exit energy
|
||||
costs, it is clear that if the idle state residency time (i.e. time till next
|
||||
wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
|
||||
choice energywise.
|
||||
|
||||
This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
|
||||
than IDLE2.
|
||||
|
||||
However, the lower power consumption (i.e. shallower energy curve slope) of
|
||||
idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
|
||||
efficient.
|
||||
|
||||
The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
|
||||
shallower states in a system with multiple idle states) is defined
|
||||
IDLE2-min-residency and corresponds to the time when energy consumption of
|
||||
IDLE1 and IDLE2 states breaks even.
|
||||
|
||||
The definitions provided in this section underpin the idle states
|
||||
properties specification that is the subject of the following sections.
|
||||
|
||||
===========================================
|
||||
3 - idle-states node
|
||||
===========================================
|
||||
|
||||
ARM processor idle states are defined within the idle-states node, which is
|
||||
a direct child of the cpus node [1] and provides a container where the
|
||||
processor idle states, defined as device tree nodes, are listed.
|
||||
|
||||
- idle-states node
|
||||
|
||||
Usage: Optional - On ARM systems, it is a container of processor idle
|
||||
states nodes. If the system does not provide CPU
|
||||
power management capabilities, or the processor just
|
||||
supports idle_standby, an idle-states node is not
|
||||
required.
|
||||
|
||||
Description: idle-states node is a container node, where its
|
||||
subnodes describe the CPU idle states.
|
||||
|
||||
Node name must be "idle-states".
|
||||
|
||||
The idle-states node's parent node must be the cpus node.
|
||||
|
||||
The idle-states node's child nodes can be:
|
||||
|
||||
- one or more state nodes
|
||||
|
||||
Any other configuration is considered invalid.
|
||||
|
||||
An idle-states node defines the following properties:
|
||||
|
||||
- entry-method
|
||||
Value type: <stringlist>
|
||||
Usage and definition depend on ARM architecture version.
|
||||
# On ARM v8 64-bit this property is required and must
|
||||
be:
|
||||
- "psci"
|
||||
# On ARM 32-bit systems this property is optional
|
||||
|
||||
This assumes that the "enable-method" property is set to "psci" in the cpu
|
||||
node[6] that is responsible for setting up CPU idle management in the OS
|
||||
implementation.
|
||||
|
||||
The nodes describing the idle states (state) can only be defined
|
||||
within the idle-states node, any other configuration is considered invalid
|
||||
and therefore must be ignored.
|
||||
|
||||
===========================================
|
||||
4 - state node
|
||||
===========================================
|
||||
|
||||
A state node represents an idle state description and must be defined as
|
||||
follows:
|
||||
|
||||
- state node
|
||||
|
||||
Description: must be child of the idle-states node
|
||||
|
||||
The state node name shall follow standard device tree naming
|
||||
rules ([5], 2.2.1 "Node names"), in particular state nodes which
|
||||
are siblings within a single common parent must be given a unique name.
|
||||
|
||||
The idle state entered by executing the wfi instruction (idle_standby
|
||||
SBSA,[3][4]) is considered standard on all ARM platforms and therefore
|
||||
must not be listed.
|
||||
|
||||
With the definitions provided above, the following list represents
|
||||
the valid properties for a state node:
|
||||
|
||||
- compatible
|
||||
Usage: Required
|
||||
Value type: <stringlist>
|
||||
Definition: Must be "arm,idle-state".
|
||||
|
||||
- local-timer-stop
|
||||
Usage: See definition
|
||||
Value type: <none>
|
||||
Definition: if present the CPU local timer control logic is
|
||||
lost on state entry, otherwise it is retained.
|
||||
|
||||
- entry-latency-us
|
||||
Usage: Required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: u32 value representing worst case latency in
|
||||
microseconds required to enter the idle state.
|
||||
|
||||
- exit-latency-us
|
||||
Usage: Required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: u32 value representing worst case latency
|
||||
in microseconds required to exit the idle state.
|
||||
The exit-latency-us duration may be guaranteed
|
||||
only after entry-latency-us has passed.
|
||||
|
||||
- min-residency-us
|
||||
Usage: Required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: u32 value representing minimum residency duration
|
||||
in microseconds, inclusive of preparation and
|
||||
entry, for this idle state to be considered
|
||||
worthwhile energy wise (refer to section 2 of
|
||||
this document for a complete description).
|
||||
|
||||
- wakeup-latency-us:
|
||||
Usage: Optional
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: u32 value representing maximum delay between the
|
||||
signaling of a wake-up event and the CPU being
|
||||
able to execute normal code again. If omitted,
|
||||
this is assumed to be equal to:
|
||||
|
||||
entry-latency-us + exit-latency-us
|
||||
|
||||
It is important to supply this value on systems
|
||||
where the duration of PREP phase (see diagram 1,
|
||||
section 2) is non-neglibigle.
|
||||
In such systems entry-latency-us + exit-latency-us
|
||||
will exceed wakeup-latency-us by this duration.
|
||||
|
||||
- status:
|
||||
Usage: Optional
|
||||
Value type: <string>
|
||||
Definition: A standard device tree property [5] that indicates
|
||||
the operational status of an idle-state.
|
||||
If present, it shall be:
|
||||
"okay": to indicate that the idle state is
|
||||
operational.
|
||||
"disabled": to indicate that the idle state has
|
||||
been disabled in firmware so it is not
|
||||
operational.
|
||||
If the property is not present the idle-state must
|
||||
be considered operational.
|
||||
|
||||
- idle-state-name:
|
||||
Usage: Optional
|
||||
Value type: <string>
|
||||
Definition: A string used as a descriptive name for the idle
|
||||
state.
|
||||
|
||||
In addition to the properties listed above, a state node may require
|
||||
additional properties specific to the entry-method defined in the
|
||||
idle-states node. Please refer to the entry-method bindings
|
||||
documentation for properties definitions.
|
||||
|
||||
===========================================
|
||||
4 - Examples
|
||||
===========================================
|
||||
|
||||
Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <2>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU4: cpu@10000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU5: cpu@10001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU6: cpu@10100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU7: cpu@10101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU8: cpu@100000000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU9: cpu@100000001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU10: cpu@100000100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU11: cpu@100000101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU12: cpu@100010000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU13: cpu@100010001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU14: cpu@100010100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU15: cpu@100010101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_RETENTION_0_0: cpu-retention-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <20>;
|
||||
exit-latency-us = <40>;
|
||||
min-residency-us = <80>;
|
||||
};
|
||||
|
||||
CLUSTER_RETENTION_0: cluster-retention-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <50>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <250>;
|
||||
wakeup-latency-us = <130>;
|
||||
};
|
||||
|
||||
CPU_SLEEP_0_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <250>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <950>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <600>;
|
||||
exit-latency-us = <1100>;
|
||||
min-residency-us = <2700>;
|
||||
wakeup-latency-us = <1500>;
|
||||
};
|
||||
|
||||
CPU_RETENTION_1_0: cpu-retention-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <20>;
|
||||
exit-latency-us = <40>;
|
||||
min-residency-us = <90>;
|
||||
};
|
||||
|
||||
CLUSTER_RETENTION_1: cluster-retention-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <50>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <270>;
|
||||
wakeup-latency-us = <100>;
|
||||
};
|
||||
|
||||
CPU_SLEEP_1_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <70>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <300>;
|
||||
wakeup-latency-us = <150>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_1: cluster-sleep-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <500>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <3500>;
|
||||
wakeup-latency-us = <1300>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
Example 2 (ARM 32-bit, 8-cpu system, two clusters):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
CPU4: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU5: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU6: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
CPU7: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
CPU_SLEEP_0_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <200>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <400>;
|
||||
wakeup-latency-us = <250>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <500>;
|
||||
exit-latency-us = <1500>;
|
||||
min-residency-us = <2500>;
|
||||
wakeup-latency-us = <1700>;
|
||||
};
|
||||
|
||||
CPU_SLEEP_1_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <900>;
|
||||
wakeup-latency-us = <600>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_1: cluster-sleep-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <800>;
|
||||
exit-latency-us = <2000>;
|
||||
min-residency-us = <6500>;
|
||||
wakeup-latency-us = <2300>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
===========================================
|
||||
5 - References
|
||||
===========================================
|
||||
|
||||
[1] ARM Linux Kernel documentation - CPUs bindings
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml
|
||||
|
||||
[2] ARM Linux Kernel documentation - PSCI bindings
|
||||
Documentation/devicetree/bindings/arm/psci.yaml
|
||||
|
||||
[3] ARM Server Base System Architecture (SBSA)
|
||||
http://infocenter.arm.com/help/index.jsp
|
||||
|
||||
[4] ARM Architecture Reference Manuals
|
||||
http://infocenter.arm.com/help/index.jsp
|
||||
|
||||
[5] Devicetree Specification
|
||||
https://www.devicetree.org/specifications/
|
||||
|
||||
[6] ARM Linux Kernel documentation - Booting AArch64 Linux
|
||||
Documentation/arm64/booting.rst
|
661
Bindings/arm/idle-states.yaml
Normal file
661
Bindings/arm/idle-states.yaml
Normal file
@ -0,0 +1,661 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/idle-states.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM idle states binding description
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
|
||||
description: |+
|
||||
==========================================
|
||||
1 - Introduction
|
||||
==========================================
|
||||
|
||||
ARM systems contain HW capable of managing power consumption dynamically,
|
||||
where cores can be put in different low-power states (ranging from simple wfi
|
||||
to power gating) according to OS PM policies. The CPU states representing the
|
||||
range of dynamic idle states that a processor can enter at run-time, can be
|
||||
specified through device tree bindings representing the parameters required to
|
||||
enter/exit specific idle states on a given processor.
|
||||
|
||||
According to the Server Base System Architecture document (SBSA, [3]), the
|
||||
power states an ARM CPU can be put into are identified by the following list:
|
||||
|
||||
- Running
|
||||
- Idle_standby
|
||||
- Idle_retention
|
||||
- Sleep
|
||||
- Off
|
||||
|
||||
The power states described in the SBSA document define the basic CPU states on
|
||||
top of which ARM platforms implement power management schemes that allow an OS
|
||||
PM implementation to put the processor in different idle states (which include
|
||||
states listed above; "off" state is not an idle state since it does not have
|
||||
wake-up capabilities, hence it is not considered in this document).
|
||||
|
||||
Idle state parameters (e.g. entry latency) are platform specific and need to
|
||||
be characterized with bindings that provide the required information to OS PM
|
||||
code so that it can build the required tables and use them at runtime.
|
||||
|
||||
The device tree binding definition for ARM idle states is the subject of this
|
||||
document.
|
||||
|
||||
===========================================
|
||||
2 - idle-states definitions
|
||||
===========================================
|
||||
|
||||
Idle states are characterized for a specific system through a set of
|
||||
timing and energy related properties, that underline the HW behaviour
|
||||
triggered upon idle states entry and exit.
|
||||
|
||||
The following diagram depicts the CPU execution phases and related timing
|
||||
properties required to enter and exit an idle state:
|
||||
|
||||
..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
|
||||
| | | | |
|
||||
|
||||
|<------ entry ------->|
|
||||
| latency |
|
||||
|<- exit ->|
|
||||
| latency |
|
||||
|<-------- min-residency -------->|
|
||||
|<------- wakeup-latency ------->|
|
||||
|
||||
Diagram 1: CPU idle state execution phases
|
||||
|
||||
EXEC: Normal CPU execution.
|
||||
|
||||
PREP: Preparation phase before committing the hardware to idle mode
|
||||
like cache flushing. This is abortable on pending wake-up
|
||||
event conditions. The abort latency is assumed to be negligible
|
||||
(i.e. less than the ENTRY + EXIT duration). If aborted, CPU
|
||||
goes back to EXEC. This phase is optional. If not abortable,
|
||||
this should be included in the ENTRY phase instead.
|
||||
|
||||
ENTRY: The hardware is committed to idle mode. This period must run
|
||||
to completion up to IDLE before anything else can happen.
|
||||
|
||||
IDLE: This is the actual energy-saving idle period. This may last
|
||||
between 0 and infinite time, until a wake-up event occurs.
|
||||
|
||||
EXIT: Period during which the CPU is brought back to operational
|
||||
mode (EXEC).
|
||||
|
||||
entry-latency: Worst case latency required to enter the idle state. The
|
||||
exit-latency may be guaranteed only after entry-latency has passed.
|
||||
|
||||
min-residency: Minimum period, including preparation and entry, for a given
|
||||
idle state to be worthwhile energywise.
|
||||
|
||||
wakeup-latency: Maximum delay between the signaling of a wake-up event and the
|
||||
CPU being able to execute normal code again. If not specified, this is assumed
|
||||
to be entry-latency + exit-latency.
|
||||
|
||||
These timing parameters can be used by an OS in different circumstances.
|
||||
|
||||
An idle CPU requires the expected min-residency time to select the most
|
||||
appropriate idle state based on the expected expiry time of the next IRQ
|
||||
(i.e. wake-up) that causes the CPU to return to the EXEC phase.
|
||||
|
||||
An operating system scheduler may need to compute the shortest wake-up delay
|
||||
for CPUs in the system by detecting how long will it take to get a CPU out
|
||||
of an idle state, e.g.:
|
||||
|
||||
wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
|
||||
|
||||
In other words, the scheduler can make its scheduling decision by selecting
|
||||
(e.g. waking-up) the CPU with the shortest wake-up delay.
|
||||
The wake-up delay must take into account the entry latency if that period
|
||||
has not expired. The abortable nature of the PREP period can be ignored
|
||||
if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
|
||||
the worst case since it depends on the CPU operating conditions, i.e. caches
|
||||
state).
|
||||
|
||||
An OS has to reliably probe the wakeup-latency since some devices can enforce
|
||||
latency constraint guarantees to work properly, so the OS has to detect the
|
||||
worst case wake-up latency it can incur if a CPU is allowed to enter an
|
||||
idle state, and possibly to prevent that to guarantee reliable device
|
||||
functioning.
|
||||
|
||||
The min-residency time parameter deserves further explanation since it is
|
||||
expressed in time units but must factor in energy consumption coefficients.
|
||||
|
||||
The energy consumption of a cpu when it enters a power state can be roughly
|
||||
characterised by the following graph:
|
||||
|
||||
|
|
||||
|
|
||||
|
|
||||
e |
|
||||
n | /---
|
||||
e | /------
|
||||
r | /------
|
||||
g | /-----
|
||||
y | /------
|
||||
| ----
|
||||
| /|
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
| / |
|
||||
|/ |
|
||||
-----|-------+----------------------------------
|
||||
0| 1 time(ms)
|
||||
|
||||
Graph 1: Energy vs time example
|
||||
|
||||
The graph is split in two parts delimited by time 1ms on the X-axis.
|
||||
The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
|
||||
and denotes the energy costs incurred while entering and leaving the idle
|
||||
state.
|
||||
The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
|
||||
shallower slope and essentially represents the energy consumption of the idle
|
||||
state.
|
||||
|
||||
min-residency is defined for a given idle state as the minimum expected
|
||||
residency time for a state (inclusive of preparation and entry) after
|
||||
which choosing that state become the most energy efficient option. A good
|
||||
way to visualise this, is by taking the same graph above and comparing some
|
||||
states energy consumptions plots.
|
||||
|
||||
For sake of simplicity, let's consider a system with two idle states IDLE1,
|
||||
and IDLE2:
|
||||
|
||||
|
|
||||
|
|
||||
|
|
||||
| /-- IDLE1
|
||||
e | /---
|
||||
n | /----
|
||||
e | /---
|
||||
r | /-----/--------- IDLE2
|
||||
g | /-------/---------
|
||||
y | ------------ /---|
|
||||
| / /---- |
|
||||
| / /--- |
|
||||
| / /---- |
|
||||
| / /--- |
|
||||
| --- |
|
||||
| / |
|
||||
| / |
|
||||
|/ | time
|
||||
---/----------------------------+------------------------
|
||||
|IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
|
||||
|
|
||||
IDLE2-min-residency
|
||||
|
||||
Graph 2: idle states min-residency example
|
||||
|
||||
In graph 2 above, that takes into account idle states entry/exit energy
|
||||
costs, it is clear that if the idle state residency time (i.e. time till next
|
||||
wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
|
||||
choice energywise.
|
||||
|
||||
This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
|
||||
than IDLE2.
|
||||
|
||||
However, the lower power consumption (i.e. shallower energy curve slope) of
|
||||
idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
|
||||
efficient.
|
||||
|
||||
The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
|
||||
shallower states in a system with multiple idle states) is defined
|
||||
IDLE2-min-residency and corresponds to the time when energy consumption of
|
||||
IDLE1 and IDLE2 states breaks even.
|
||||
|
||||
The definitions provided in this section underpin the idle states
|
||||
properties specification that is the subject of the following sections.
|
||||
|
||||
===========================================
|
||||
3 - idle-states node
|
||||
===========================================
|
||||
|
||||
ARM processor idle states are defined within the idle-states node, which is
|
||||
a direct child of the cpus node [1] and provides a container where the
|
||||
processor idle states, defined as device tree nodes, are listed.
|
||||
|
||||
On ARM systems, it is a container of processor idle states nodes. If the
|
||||
system does not provide CPU power management capabilities, or the processor
|
||||
just supports idle_standby, an idle-states node is not required.
|
||||
|
||||
===========================================
|
||||
4 - References
|
||||
===========================================
|
||||
|
||||
[1] ARM Linux Kernel documentation - CPUs bindings
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml
|
||||
|
||||
[2] ARM Linux Kernel documentation - PSCI bindings
|
||||
Documentation/devicetree/bindings/arm/psci.yaml
|
||||
|
||||
[3] ARM Server Base System Architecture (SBSA)
|
||||
http://infocenter.arm.com/help/index.jsp
|
||||
|
||||
[4] ARM Architecture Reference Manuals
|
||||
http://infocenter.arm.com/help/index.jsp
|
||||
|
||||
[6] ARM Linux Kernel documentation - Booting AArch64 Linux
|
||||
Documentation/arm64/booting.rst
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: idle-states
|
||||
|
||||
entry-method:
|
||||
description: |
|
||||
Usage and definition depend on ARM architecture version.
|
||||
|
||||
On ARM v8 64-bit this property is required.
|
||||
On ARM 32-bit systems this property is optional
|
||||
|
||||
This assumes that the "enable-method" property is set to "psci" in the cpu
|
||||
node[6] that is responsible for setting up CPU idle management in the OS
|
||||
implementation.
|
||||
const: psci
|
||||
|
||||
patternProperties:
|
||||
"^(cpu|cluster)-":
|
||||
type: object
|
||||
description: |
|
||||
Each state node represents an idle state description and must be defined
|
||||
as follows.
|
||||
|
||||
The idle state entered by executing the wfi instruction (idle_standby
|
||||
SBSA,[3][4]) is considered standard on all ARM platforms and therefore
|
||||
must not be listed.
|
||||
|
||||
In addition to the properties listed above, a state node may require
|
||||
additional properties specific to the entry-method defined in the
|
||||
idle-states node. Please refer to the entry-method bindings
|
||||
documentation for properties definitions.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,idle-state
|
||||
|
||||
local-timer-stop:
|
||||
description:
|
||||
If present the CPU local timer control logic is
|
||||
lost on state entry, otherwise it is retained.
|
||||
type: boolean
|
||||
|
||||
entry-latency-us:
|
||||
description:
|
||||
Worst case latency in microseconds required to enter the idle state.
|
||||
|
||||
exit-latency-us:
|
||||
description:
|
||||
Worst case latency in microseconds required to exit the idle state.
|
||||
The exit-latency-us duration may be guaranteed only after
|
||||
entry-latency-us has passed.
|
||||
|
||||
min-residency-us:
|
||||
description:
|
||||
Minimum residency duration in microseconds, inclusive of preparation
|
||||
and entry, for this idle state to be considered worthwhile energy wise
|
||||
(refer to section 2 of this document for a complete description).
|
||||
|
||||
wakeup-latency-us:
|
||||
description: |
|
||||
Maximum delay between the signaling of a wake-up event and the CPU
|
||||
being able to execute normal code again. If omitted, this is assumed
|
||||
to be equal to:
|
||||
|
||||
entry-latency-us + exit-latency-us
|
||||
|
||||
It is important to supply this value on systems where the duration of
|
||||
PREP phase (see diagram 1, section 2) is non-neglibigle. In such
|
||||
systems entry-latency-us + exit-latency-us will exceed
|
||||
wakeup-latency-us by this duration.
|
||||
|
||||
idle-state-name:
|
||||
$ref: /schemas/types.yaml#definitions/string
|
||||
description:
|
||||
A string used as a descriptive name for the idle state.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- entry-latency-us
|
||||
- exit-latency-us
|
||||
- min-residency-us
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <2>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@10101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
|
||||
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
|
||||
};
|
||||
|
||||
cpu@100000000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100000001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100000100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100000101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10000>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10001>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
cpu@100010101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1 0x10101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
|
||||
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
entry-method = "psci";
|
||||
|
||||
CPU_RETENTION_0_0: cpu-retention-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <20>;
|
||||
exit-latency-us = <40>;
|
||||
min-residency-us = <80>;
|
||||
};
|
||||
|
||||
CLUSTER_RETENTION_0: cluster-retention-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <50>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <250>;
|
||||
wakeup-latency-us = <130>;
|
||||
};
|
||||
|
||||
CPU_SLEEP_0_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <250>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <950>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <600>;
|
||||
exit-latency-us = <1100>;
|
||||
min-residency-us = <2700>;
|
||||
wakeup-latency-us = <1500>;
|
||||
};
|
||||
|
||||
CPU_RETENTION_1_0: cpu-retention-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <20>;
|
||||
exit-latency-us = <40>;
|
||||
min-residency-us = <90>;
|
||||
};
|
||||
|
||||
CLUSTER_RETENTION_1: cluster-retention-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <50>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <270>;
|
||||
wakeup-latency-us = <100>;
|
||||
};
|
||||
|
||||
CPU_SLEEP_1_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x0010000>;
|
||||
entry-latency-us = <70>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <300>;
|
||||
wakeup-latency-us = <150>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP_1: cluster-sleep-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x1010000>;
|
||||
entry-latency-us = <500>;
|
||||
exit-latency-us = <1200>;
|
||||
min-residency-us = <3500>;
|
||||
wakeup-latency-us = <1300>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 2 (ARM 32-bit, 8-cpu system, two clusters):
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x2>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x3>;
|
||||
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
|
||||
};
|
||||
|
||||
cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x102>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
|
||||
};
|
||||
|
||||
cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x103>;
|
||||
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
cpu_sleep_0_0: cpu-sleep-0-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <200>;
|
||||
exit-latency-us = <100>;
|
||||
min-residency-us = <400>;
|
||||
wakeup-latency-us = <250>;
|
||||
};
|
||||
|
||||
cluster_sleep_0: cluster-sleep-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <500>;
|
||||
exit-latency-us = <1500>;
|
||||
min-residency-us = <2500>;
|
||||
wakeup-latency-us = <1700>;
|
||||
};
|
||||
|
||||
cpu_sleep_1_0: cpu-sleep-1-0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <300>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <900>;
|
||||
wakeup-latency-us = <600>;
|
||||
};
|
||||
|
||||
cluster_sleep_1: cluster-sleep-1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
entry-latency-us = <800>;
|
||||
exit-latency-us = <2000>;
|
||||
min-residency-us = <6500>;
|
||||
wakeup-latency-us = <2300>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
@ -81,4 +81,4 @@ Example:
|
||||
};
|
||||
};
|
||||
|
||||
[1]. Documentation/devicetree/bindings/arm/idle-states.txt
|
||||
[1]. Documentation/devicetree/bindings/arm/idle-states.yaml
|
||||
|
@ -47,7 +47,7 @@ examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
cache-controller@1100000 {
|
||||
system-cache-controller@1100000 {
|
||||
compatible = "qcom,sdm845-llcc";
|
||||
reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
|
||||
reg-names = "llcc_base", "llcc_broadcast_base";
|
||||
|
@ -17,7 +17,7 @@ am335x and am437x only:
|
||||
- pm-sram: Phandles to ocmcram nodes to be used for power management.
|
||||
First should be type 'protect-exec' for the driver to use to copy
|
||||
and run PM functions, second should be regular pool to be used for
|
||||
data region for code. See Documentation/devicetree/bindings/sram/sram.txt
|
||||
data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
|
||||
for more details.
|
||||
|
||||
Examples:
|
||||
|
@ -100,8 +100,31 @@ properties:
|
||||
bindings in [1]) must specify this property.
|
||||
|
||||
[1] Kernel documentation - ARM idle states bindings
|
||||
Documentation/devicetree/bindings/arm/idle-states.txt
|
||||
Documentation/devicetree/bindings/arm/idle-states.yaml
|
||||
|
||||
patternProperties:
|
||||
"^power-domain-":
|
||||
allOf:
|
||||
- $ref: "../power/power-domain.yaml#"
|
||||
type: object
|
||||
description: |
|
||||
ARM systems can have multiple cores, sometimes in an hierarchical
|
||||
arrangement. This often, but not always, maps directly to the processor
|
||||
power topology of the system. Individual nodes in a topology have their
|
||||
own specific power states and can be better represented hierarchically.
|
||||
|
||||
For these cases, the definitions of the idle states for the CPUs and the
|
||||
CPU topology, must conform to the binding in [3]. The idle states
|
||||
themselves must conform to the binding in [4] and must specify the
|
||||
arm,psci-suspend-param property.
|
||||
|
||||
It should also be noted that, in PSCI firmware v1.0 the OS-Initiated
|
||||
(OSI) CPU suspend mode is introduced. Using a hierarchical representation
|
||||
helps to implement support for OSI mode and OS implementations may choose
|
||||
to mandate it.
|
||||
|
||||
[3] Documentation/devicetree/bindings/power/power-domain.yaml
|
||||
[4] Documentation/devicetree/bindings/power/domain-idle-state.yaml
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -160,4 +183,83 @@ examples:
|
||||
cpu_on = <0x95c10002>;
|
||||
cpu_off = <0x95c10001>;
|
||||
};
|
||||
|
||||
- |+
|
||||
|
||||
// Case 4: CPUs and CPU idle states described using the hierarchical model.
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
power-domains = <&CPU_PD0>;
|
||||
power-domain-names = "psci";
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
power-domains = <&CPU_PD1>;
|
||||
power-domain-names = "psci";
|
||||
};
|
||||
|
||||
idle-states {
|
||||
|
||||
CPU_PWRDN: cpu-power-down {
|
||||
compatible = "arm,idle-state";
|
||||
arm,psci-suspend-param = <0x0000001>;
|
||||
entry-latency-us = <10>;
|
||||
exit-latency-us = <10>;
|
||||
min-residency-us = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
domain-idle-states {
|
||||
|
||||
CLUSTER_RET: cluster-retention {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x1000011>;
|
||||
entry-latency-us = <500>;
|
||||
exit-latency-us = <500>;
|
||||
min-residency-us = <2000>;
|
||||
};
|
||||
|
||||
CLUSTER_PWRDN: cluster-power-down {
|
||||
compatible = "domain-idle-state";
|
||||
arm,psci-suspend-param = <0x1000031>;
|
||||
entry-latency-us = <2000>;
|
||||
exit-latency-us = <2000>;
|
||||
min-residency-us = <6000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
|
||||
CPU_PD0: power-domain-cpu0 {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CPU_PWRDN>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
};
|
||||
|
||||
CPU_PD1: power-domain-cpu1 {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CPU_PWRDN>;
|
||||
power-domains = <&CLUSTER_PD>;
|
||||
};
|
||||
|
||||
CLUSTER_PD: power-domain-cluster {
|
||||
#power-domain-cells = <0>;
|
||||
domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/arm/qcom.yaml#
|
||||
$id: http://devicetree.org/schemas/arm/qcom.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: QCOM device tree bindings
|
||||
@ -24,28 +24,30 @@ description: |
|
||||
|
||||
The 'SoC' element must be one of the following strings:
|
||||
|
||||
apq8016
|
||||
apq8074
|
||||
apq8084
|
||||
apq8096
|
||||
msm8916
|
||||
msm8974
|
||||
msm8992
|
||||
msm8994
|
||||
msm8996
|
||||
mdm9615
|
||||
ipq8074
|
||||
sdm845
|
||||
apq8016
|
||||
apq8074
|
||||
apq8084
|
||||
apq8096
|
||||
ipq8074
|
||||
mdm9615
|
||||
msm8916
|
||||
msm8974
|
||||
msm8992
|
||||
msm8994
|
||||
msm8996
|
||||
sc7180
|
||||
sdm845
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
cdp
|
||||
liquid
|
||||
dragonboard
|
||||
mtp
|
||||
sbc
|
||||
hk01
|
||||
qrd
|
||||
cdp
|
||||
dragonboard
|
||||
hk01
|
||||
idp
|
||||
liquid
|
||||
mtp
|
||||
qrd
|
||||
sbc
|
||||
|
||||
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
|
||||
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
|
||||
@ -144,4 +146,8 @@ properties:
|
||||
- qcom,ipq8074-hk01
|
||||
- const: qcom,ipq8074
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sc7180-idp
|
||||
- const: qcom,sc7180
|
||||
...
|
||||
|
@ -409,6 +409,9 @@ properties:
|
||||
|
||||
- description: Pine64 RockPro64
|
||||
items:
|
||||
- enum:
|
||||
- pine64,rockpro64-v2.1
|
||||
- pine64,rockpro64-v2.0
|
||||
- const: pine64,rockpro64
|
||||
- const: rockchip,rk3399
|
||||
|
||||
@ -422,6 +425,12 @@ properties:
|
||||
- const: radxa,rockpi4
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Radxa ROCK Pi N10
|
||||
items:
|
||||
- const: radxa,rockpi-n10
|
||||
- const: vamrs,rk3399pro-vmarc-som
|
||||
- const: rockchip,rk3399pro
|
||||
|
||||
- description: Radxa Rock2 Square
|
||||
items:
|
||||
- const: radxa,rock2-square
|
||||
|
@ -2,7 +2,7 @@
|
||||
# Copyright 2019 Unisoc Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/sprd.yaml#
|
||||
$id: http://devicetree.org/schemas/arm/sprd/sprd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Unisoc platforms device tree bindings
|
@ -1,37 +0,0 @@
|
||||
ML-AHB interconnect bindings
|
||||
|
||||
These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
|
||||
a Cortex-M subsystem with dedicated memories.
|
||||
The MCU SRAM and RETRAM memory parts can be accessed through different addresses
|
||||
(see "RAM aliases" in [1]) using different buses (see [2]) : balancing the
|
||||
Cortex-M firmware accesses among those ports allows to tune the system
|
||||
performance.
|
||||
|
||||
[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf
|
||||
[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "simple-bus"
|
||||
- dma-ranges: describes memory addresses translation between the local CPU and
|
||||
the remote Cortex-M processor. Each memory region, is declared with
|
||||
3 parameters:
|
||||
- param 1: device base address (Cortex-M processor address)
|
||||
- param 2: physical base address (local CPU address)
|
||||
- param 3: size of the memory region.
|
||||
|
||||
The Cortex-M remote processor accessed via the mlahb interconnect is described
|
||||
by a child node.
|
||||
|
||||
Example:
|
||||
mlahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
dma-ranges = <0x00000000 0x38000000 0x10000>,
|
||||
<0x10000000 0x10000000 0x60000>,
|
||||
<0x30000000 0x30000000 0x60000>;
|
||||
|
||||
m4_rproc: m4@10000000 {
|
||||
...
|
||||
};
|
||||
};
|
70
Bindings/arm/stm32/st,mlahb.yaml
Normal file
70
Bindings/arm/stm32/st,mlahb.yaml
Normal file
@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: STMicroelectronics STM32 ML-AHB interconnect bindings
|
||||
|
||||
maintainers:
|
||||
- Fabien Dessenne <fabien.dessenne@st.com>
|
||||
- Arnaud Pouliquen <arnaud.pouliquen@st.com>
|
||||
|
||||
description: |
|
||||
These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
|
||||
a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
|
||||
parts can be accessed through different addresses (see "RAM aliases" in [1])
|
||||
using different buses (see [2]): balancing the Cortex-M firmware accesses
|
||||
among those ports allows to tune the system performance.
|
||||
[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf
|
||||
[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/simple-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- st,mlahb
|
||||
|
||||
dma-ranges:
|
||||
description: |
|
||||
Describe memory addresses translation between the local CPU and the
|
||||
remote Cortex-M processor. Each memory region, is declared with
|
||||
3 parameters:
|
||||
- param 1: device base address (Cortex-M processor address)
|
||||
- param 2: physical base address (local CPU address)
|
||||
- param 3: size of the memory region.
|
||||
maxItems: 3
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
- dma-ranges
|
||||
|
||||
examples:
|
||||
- |
|
||||
mlahb: ahb@38000000 {
|
||||
compatible = "st,mlahb", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x10000000 0x40000>;
|
||||
ranges;
|
||||
dma-ranges = <0x00000000 0x38000000 0x10000>,
|
||||
<0x10000000 0x10000000 0x60000>,
|
||||
<0x30000000 0x30000000 0x60000>;
|
||||
|
||||
m4_rproc: m4@10000000 {
|
||||
reg = <0x10000000 0x40000>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
41
Bindings/arm/stm32/st,stm32-syscon.yaml
Normal file
41
Bindings/arm/stm32/st,stm32-syscon.yaml
Normal file
@ -0,0 +1,41 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: STMicroelectronics STM32 Platforms System Controller bindings
|
||||
|
||||
maintainers:
|
||||
- Alexandre Torgue <alexandre.torgue@st.com>
|
||||
- Christophe Roullier <christophe.roullier@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32mp157-syscfg
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
syscfg: syscon@50020000 {
|
||||
compatible = "st,stm32mp157-syscfg", "syscon";
|
||||
reg = <0x50020000 0x400>;
|
||||
clocks = <&rcc SYSCFG>;
|
||||
};
|
||||
|
||||
...
|
@ -1,16 +0,0 @@
|
||||
STMicroelectronics STM32 Platforms System Controller
|
||||
|
||||
Properties:
|
||||
- compatible : should contain two values. First value must be :
|
||||
- " st,stm32mp157-syscfg " - for stm32mp157 based SoCs,
|
||||
second value must be always "syscon".
|
||||
- reg : offset and length of the register set.
|
||||
- clocks: phandle to the syscfg clock
|
||||
|
||||
Example:
|
||||
syscfg: syscon@50020000 {
|
||||
compatible = "st,stm32mp157-syscfg", "syscon";
|
||||
reg = <0x50020000 0x400>;
|
||||
clocks = <&rcc SYSCFG>;
|
||||
};
|
||||
|
@ -342,6 +342,16 @@ properties:
|
||||
- const: libretech,all-h3-cc-h5
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Libre Computer Board ALL-H3-IT H5
|
||||
items:
|
||||
- const: libretech,all-h3-it-h5
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Libre Computer Board ALL-H5-CC H5
|
||||
items:
|
||||
- const: libretech,all-h5-cc-h5
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Lichee Pi One
|
||||
items:
|
||||
- const: licheepi,licheepi-one
|
||||
@ -470,6 +480,12 @@ properties:
|
||||
- const: emlid,neutis-n5
|
||||
- const: allwinner,sun50i-h5
|
||||
|
||||
- description: Emlid Neutis N5H3 Developper Board
|
||||
items:
|
||||
- const: emlid,neutis-n5h3-devboard
|
||||
- const: emlid,neutis-n5h3
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: NextThing Co. CHIP
|
||||
items:
|
||||
- const: nextthing,chip
|
||||
@ -599,11 +615,16 @@ properties:
|
||||
- const: pine64,pine64-plus
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PineH64
|
||||
- description: Pine64 PineH64 model A
|
||||
items:
|
||||
- const: pine64,pine-h64
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: Pine64 PineH64 model B
|
||||
items:
|
||||
- const: pine64,pine-h64-model-b
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: Pine64 LTS
|
||||
items:
|
||||
- const: pine64,pine64-lts
|
||||
|
65
Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
Normal file
65
Bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
Normal file
@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner Memory Bus (MBUS) controller
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
description: |
|
||||
The MBUS controller drives the MBUS that other devices in the SoC
|
||||
will use to perform DMA. It also has a register interface that
|
||||
allows to monitor and control the bandwidth and priorities for
|
||||
masters on that bus.
|
||||
|
||||
Each device having to perform their DMA through the MBUS must have
|
||||
the interconnects and interconnect-names properties set to the MBUS
|
||||
controller and with "dma-mem" as the interconnect name.
|
||||
|
||||
properties:
|
||||
"#interconnect-cells":
|
||||
const: 1
|
||||
description:
|
||||
The content of the cell is the MBUS ID.
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun5i-a13-mbus
|
||||
- allwinner,sun8i-h3-mbus
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
dma-ranges:
|
||||
description:
|
||||
See section 2.3.9 of the DeviceTree Specification.
|
||||
|
||||
required:
|
||||
- "#interconnect-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- dma-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/sun5i-ccu.h>
|
||||
|
||||
mbus: dram-controller@1c01000 {
|
||||
compatible = "allwinner,sun5i-a13-mbus";
|
||||
reg = <0x01c01000 0x1000>;
|
||||
clocks = <&ccu CLK_MBUS>;
|
||||
dma-ranges = <0x00000000 0x40000000 0x20000000>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
@ -1,37 +0,0 @@
|
||||
Allwinner Memory Bus (MBUS) controller
|
||||
|
||||
The MBUS controller drives the MBUS that other devices in the SoC will
|
||||
use to perform DMA. It also has a register interface that allows to
|
||||
monitor and control the bandwidth and priorities for masters on that
|
||||
bus.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be one of:
|
||||
- allwinner,sun5i-a13-mbus
|
||||
- allwinner,sun8i-h3-mbus
|
||||
- reg: Offset and length of the register set for the controller
|
||||
- clocks: phandle to the clock driving the controller
|
||||
- dma-ranges: See section 2.3.9 of the DeviceTree Specification
|
||||
- #interconnect-cells: Must be one, with the argument being the MBUS
|
||||
port ID
|
||||
|
||||
Each device having to perform their DMA through the MBUS must have the
|
||||
interconnects and interconnect-names properties set to the MBUS
|
||||
controller and with "dma-mem" as the interconnect name.
|
||||
|
||||
Example:
|
||||
|
||||
mbus: dram-controller@1c01000 {
|
||||
compatible = "allwinner,sun5i-a13-mbus";
|
||||
reg = <0x01c01000 0x1000>;
|
||||
clocks = <&ccu CLK_MBUS>;
|
||||
dma-ranges = <0x00000000 0x40000000 0x20000000>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
fe0: display-frontend@1e00000 {
|
||||
compatible = "allwinner,sun5i-a13-display-frontend";
|
||||
...
|
||||
interconnects = <&mbus 19>;
|
||||
interconnect-names = "dma-mem";
|
||||
};
|
36
Bindings/arm/ux500.yaml
Normal file
36
Bindings/arm/ux500.yaml
Normal file
@ -0,0 +1,36 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/ux500.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Ux500 platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
|
||||
- description: ST-Ericsson HREF (pre-v60)
|
||||
items:
|
||||
- const: st-ericsson,mop500
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: ST-Ericsson HREF (v60+)
|
||||
items:
|
||||
- const: st-ericsson,hrefv60+
|
||||
- const: st-ericsson,u8500
|
||||
|
||||
- description: Calao Systems Snowball
|
||||
items:
|
||||
- const: calaosystems,snowball-a9500
|
||||
- const: st-ericsson,u9500
|
||||
|
||||
- description: Samsung Galaxy S III mini (GT-I8190)
|
||||
items:
|
||||
- const: samsung,golden
|
||||
- const: st-ericsson,u8500
|
@ -9,8 +9,6 @@ PHYs.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible string, one of:
|
||||
- "allwinner,sun4i-a10-ahci"
|
||||
- "allwinner,sun8i-r40-ahci"
|
||||
- "brcm,iproc-ahci"
|
||||
- "hisilicon,hisi-ahci"
|
||||
- "cavium,octeon-7130-ahci"
|
||||
@ -45,8 +43,6 @@ Required properties when using sub-nodes:
|
||||
- #address-cells : number of cells to encode an address
|
||||
- #size-cells : number of cells representing the size of an address
|
||||
|
||||
For allwinner,sun8i-r40-ahci, the reset property must be present.
|
||||
|
||||
Sub-nodes required properties:
|
||||
- reg : the port number
|
||||
And at least one of the following properties:
|
||||
@ -60,14 +56,6 @@ Examples:
|
||||
interrupts = <115>;
|
||||
};
|
||||
|
||||
ahci: sata@1c18000 {
|
||||
compatible = "allwinner,sun4i-a10-ahci";
|
||||
reg = <0x01c18000 0x1000>;
|
||||
interrupts = <56>;
|
||||
clocks = <&pll6 0>, <&ahb_gates 25>;
|
||||
target-supply = <®_ahci_5v>;
|
||||
};
|
||||
|
||||
With sub-nodes:
|
||||
sata@f7e90000 {
|
||||
compatible = "marvell,berlin2q-achi", "generic-ahci";
|
||||
|
47
Bindings/ata/allwinner,sun4i-a10-ahci.yaml
Normal file
47
Bindings/ata/allwinner,sun4i-a10-ahci.yaml
Normal file
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/allwinner,sun4i-a10-ahci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 AHCI SATA Controller bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-ahci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AHCI Bus Clock
|
||||
- description: AHCI Module Clock
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
target-supply:
|
||||
description: Regulator for SATA target power
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ahci: sata@1c18000 {
|
||||
compatible = "allwinner,sun4i-a10-ahci";
|
||||
reg = <0x01c18000 0x1000>;
|
||||
interrupts = <56>;
|
||||
clocks = <&pll6 0>, <&ahb_gates 25>;
|
||||
target-supply = <®_ahci_5v>;
|
||||
};
|
67
Bindings/ata/allwinner,sun8i-r40-ahci.yaml
Normal file
67
Bindings/ata/allwinner,sun8i-r40-ahci.yaml
Normal file
@ -0,0 +1,67 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner R40 AHCI SATA Controller bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: allwinner,sun8i-r40-ahci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AHCI Bus Clock
|
||||
- description: AHCI Module Clock
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
const: ahci
|
||||
|
||||
ahci-supply:
|
||||
description: Regulator for the AHCI controller
|
||||
|
||||
phy-supply:
|
||||
description: Regulator for the SATA PHY power
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/sun8i-r40-ccu.h>
|
||||
#include <dt-bindings/reset/sun8i-r40-ccu.h>
|
||||
|
||||
ahci: sata@1c18000 {
|
||||
compatible = "allwinner,sun8i-r40-ahci";
|
||||
reg = <0x01c18000 0x1000>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
|
||||
resets = <&ccu RST_BUS_SATA>;
|
||||
reset-names = "ahci";
|
||||
ahci-supply = <®_dldo4>;
|
||||
phy-supply = <®_eldo3>;
|
||||
};
|
||||
|
||||
...
|
@ -5,6 +5,7 @@ Each SATA controller should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be one or more of
|
||||
"brcm,bcm7216-ahci"
|
||||
"brcm,bcm7425-ahci"
|
||||
"brcm,bcm7445-ahci"
|
||||
"brcm,bcm-nsp-ahci"
|
||||
@ -14,6 +15,12 @@ Required properties:
|
||||
- reg-names : "ahci" and "top-ctrl"
|
||||
- interrupts : interrupt mapping for SATA IRQ
|
||||
|
||||
Optional properties:
|
||||
|
||||
- reset: for "brcm,bcm7216-ahci" must be a valid reset phandle
|
||||
pointing to the RESCAL reset controller provider node.
|
||||
- reset-names: for "brcm,bcm7216-ahci", must be "rescal".
|
||||
|
||||
Also see ahci-platform.txt.
|
||||
|
||||
Example:
|
||||
|
@ -1,38 +0,0 @@
|
||||
* Faraday Technology FTIDE010 PATA controller
|
||||
|
||||
This controller is the first Faraday IDE interface block, used in the
|
||||
StorLink SL2312 and SL3516, later known as the Cortina Systems Gemini
|
||||
platform. The controller can do PIO modes 0 through 4, Multi-word DMA
|
||||
(MWDM)modes 0 through 2 and Ultra DMA modes 0 through 6.
|
||||
|
||||
On the Gemini platform, this PATA block is accompanied by a PATA to
|
||||
SATA bridge in order to support SATA. This is why a phandle to that
|
||||
controller is compulsory on that platform.
|
||||
|
||||
The timing properties are unique per-SoC, not per-board.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of
|
||||
"cortina,gemini-pata", "faraday,ftide010"
|
||||
"faraday,ftide010"
|
||||
- interrupts: interrupt for the block
|
||||
- reg: registers and size for the block
|
||||
|
||||
Optional properties:
|
||||
- clocks: a SoC clock running the peripheral.
|
||||
- clock-names: should be set to "PCLK" for the peripheral clock.
|
||||
|
||||
Required properties for "cortina,gemini-pata" compatible:
|
||||
- sata: a phande to the Gemini PATA to SATA bridge, see
|
||||
cortina,gemini-sata-bridge.txt for details.
|
||||
|
||||
Example:
|
||||
|
||||
ata@63000000 {
|
||||
compatible = "cortina,gemini-pata", "faraday,ftide010";
|
||||
reg = <0x63000000 0x100>;
|
||||
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&gcc GEMINI_CLK_GATE_IDE>;
|
||||
clock-names = "PCLK";
|
||||
sata = <&sata>;
|
||||
};
|
89
Bindings/ata/faraday,ftide010.yaml
Normal file
89
Bindings/ata/faraday,ftide010.yaml
Normal file
@ -0,0 +1,89 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/faraday,ftide010.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Faraday Technology FTIDE010 PATA controller
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |
|
||||
This controller is the first Faraday IDE interface block, used in the
|
||||
StorLink SL3512 and SL3516, later known as the Cortina Systems Gemini
|
||||
platform. The controller can do PIO modes 0 through 4, Multi-word DMA
|
||||
(MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6.
|
||||
|
||||
On the Gemini platform, this PATA block is accompanied by a PATA to
|
||||
SATA bridge in order to support SATA. This is why a phandle to that
|
||||
controller is compulsory on that platform.
|
||||
|
||||
The timing properties are unique per-SoC, not per-board.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: faraday,ftide010
|
||||
- items:
|
||||
- const: cortina,gemini-pata
|
||||
- const: faraday,ftide010
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
|
||||
clock-names:
|
||||
const: PCLK
|
||||
|
||||
sata:
|
||||
description:
|
||||
phandle to the Gemini PATA to SATA bridge, if available
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
allOf:
|
||||
- $ref: pata-common.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: cortina,gemini-pata
|
||||
|
||||
then:
|
||||
required:
|
||||
- sata
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/cortina,gemini-clock.h>
|
||||
|
||||
ide@63000000 {
|
||||
compatible = "cortina,gemini-pata", "faraday,ftide010";
|
||||
reg = <0x63000000 0x100>;
|
||||
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&gcc GEMINI_CLK_GATE_IDE>;
|
||||
clock-names = "PCLK";
|
||||
sata = <&sata>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ide-port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
ide-port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
50
Bindings/ata/pata-common.yaml
Normal file
50
Bindings/ata/pata-common.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/pata-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Common Properties for Parallel AT attachment (PATA) controllers
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |
|
||||
This document defines device tree properties common to most Parallel
|
||||
ATA (PATA, also known as IDE) AT attachment storage devices.
|
||||
It doesn't constitue a device tree binding specification by itself but is
|
||||
meant to be referenced by device tree bindings.
|
||||
|
||||
The PATA (IDE) controller-specific device tree bindings are responsible for
|
||||
defining whether each property is required or optional.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^ide(@.*)?$"
|
||||
description:
|
||||
Specifies the host controller node. PATA host controller nodes are named
|
||||
"ide".
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^ide-port@[0-1]$":
|
||||
description: |
|
||||
DT nodes for ports connected on the PATA host. The master drive will have
|
||||
ID number 0 and the slave drive will have ID number 1. The PATA port
|
||||
nodes will be named "ide-port".
|
||||
type: object
|
||||
|
||||
properties:
|
||||
reg:
|
||||
minimum: 0
|
||||
maximum: 1
|
||||
description:
|
||||
The ID number of the drive port, 0 for the master port and 1 for the
|
||||
slave port.
|
||||
|
||||
...
|
50
Bindings/ata/sata-common.yaml
Normal file
50
Bindings/ata/sata-common.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/sata-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Common Properties for Serial AT attachment (SATA) controllers
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
description: |
|
||||
This document defines device tree properties common to most Serial
|
||||
AT attachment (SATA) storage devices. It doesn't constitute a device tree
|
||||
binding specification by itself but is meant to be referenced by device
|
||||
tree bindings.
|
||||
|
||||
The SATA controller-specific device tree bindings are responsible for
|
||||
defining whether each property is required or optional.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^sata(@.*)?$"
|
||||
description:
|
||||
Specifies the host controller node. SATA host controller nodes are named
|
||||
"sata"
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^sata-port@[0-9a-e]$":
|
||||
description: |
|
||||
DT nodes for ports connected on the SATA host. The SATA port
|
||||
nodes will be named "sata-port".
|
||||
type: object
|
||||
|
||||
properties:
|
||||
reg:
|
||||
minimum: 0
|
||||
maximum: 14
|
||||
description:
|
||||
The ID number of the drive port SATA can potentially use a port
|
||||
multiplier making it possible to connect up to 15 disks to a single
|
||||
SATA port.
|
||||
|
||||
...
|
@ -70,7 +70,6 @@ examples:
|
||||
#size-cells = <0>;
|
||||
|
||||
pmic@3e3 {
|
||||
compatible = "...";
|
||||
reg = <0x3e3>;
|
||||
|
||||
/* ... */
|
||||
|
108
Bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml
Normal file
108
Bindings/clock/allwinner,sun4i-a10-ahb-clk.yaml
Normal file
@ -0,0 +1,108 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 AHB Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun4i-a10-ahb-clk
|
||||
- allwinner,sun6i-a31-ahb1-clk
|
||||
- allwinner,sun8i-h3-ahb2-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun4i-a10-ahb-clk
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun6i-a31-ahb1-clk
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 4
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun8i-h3-ahb2-clk
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
examples:
|
||||
- |
|
||||
ahb@1c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-ahb-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&axi>;
|
||||
clock-output-names = "ahb";
|
||||
};
|
||||
|
||||
- |
|
||||
ahb1@1c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun6i-a31-ahb1-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
|
||||
clock-output-names = "ahb1";
|
||||
};
|
||||
|
||||
- |
|
||||
ahb2_clk@1c2005c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun8i-h3-ahb2-clk";
|
||||
reg = <0x01c2005c 0x4>;
|
||||
clocks = <&ahb1>, <&pll6d2>;
|
||||
clock-output-names = "ahb2";
|
||||
};
|
||||
|
||||
...
|
50
Bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml
Normal file
50
Bindings/clock/allwinner,sun4i-a10-apb0-clk.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb0-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 APB0 Bus Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-apb0-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
apb0@1c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb0-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&ahb>;
|
||||
clock-output-names = "apb0";
|
||||
};
|
||||
|
||||
...
|
52
Bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml
Normal file
52
Bindings/clock/allwinner,sun4i-a10-apb1-clk.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-apb1-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 APB1 Bus Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-apb1-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
|
||||
clock-output-names = "apb1";
|
||||
};
|
||||
|
||||
...
|
61
Bindings/clock/allwinner,sun4i-a10-axi-clk.yaml
Normal file
61
Bindings/clock/allwinner,sun4i-a10-axi-clk.yaml
Normal file
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 AXI Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun4i-a10-axi-clk
|
||||
- allwinner,sun8i-a23-axi-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
axi@1c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-axi-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&cpu>;
|
||||
clock-output-names = "axi";
|
||||
};
|
||||
|
||||
- |
|
||||
axi_clk@1c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun8i-a23-axi-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clocks = <&cpu>;
|
||||
clock-output-names = "axi";
|
||||
};
|
||||
|
||||
...
|
52
Bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml
Normal file
52
Bindings/clock/allwinner,sun4i-a10-cpu-clk.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-cpu-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 CPU Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-cpu-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cpu@1c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
|
||||
clock-output-names = "cpu";
|
||||
};
|
||||
|
||||
...
|
57
Bindings/clock/allwinner,sun4i-a10-display-clk.yaml
Normal file
57
Bindings/clock/allwinner,sun4i-a10-display-clk.yaml
Normal file
@ -0,0 +1,57 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-display-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 Display Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
"#reset-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-display-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20104 {
|
||||
#clock-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-display-clk";
|
||||
reg = <0x01c20104 0x4>;
|
||||
clocks = <&pll3>, <&pll7>, <&pll5 1>;
|
||||
clock-output-names = "de-be";
|
||||
};
|
||||
|
||||
...
|
152
Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml
Normal file
152
Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml
Normal file
@ -0,0 +1,152 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 Bus Gates Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: >
|
||||
This additional argument passed to that clock is the offset of
|
||||
the bit controlling this particular gate in the register.
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: allwinner,sun4i-a10-gates-clk
|
||||
- const: allwinner,sun4i-a10-axi-gates-clk
|
||||
- const: allwinner,sun4i-a10-ahb-gates-clk
|
||||
- const: allwinner,sun5i-a10s-ahb-gates-clk
|
||||
- const: allwinner,sun5i-a13-ahb-gates-clk
|
||||
- const: allwinner,sun7i-a20-ahb-gates-clk
|
||||
- const: allwinner,sun6i-a31-ahb1-gates-clk
|
||||
- const: allwinner,sun8i-a23-ahb1-gates-clk
|
||||
- const: allwinner,sun9i-a80-ahb0-gates-clk
|
||||
- const: allwinner,sun9i-a80-ahb1-gates-clk
|
||||
- const: allwinner,sun9i-a80-ahb2-gates-clk
|
||||
- const: allwinner,sun4i-a10-apb0-gates-clk
|
||||
- const: allwinner,sun5i-a10s-apb0-gates-clk
|
||||
- const: allwinner,sun5i-a13-apb0-gates-clk
|
||||
- const: allwinner,sun7i-a20-apb0-gates-clk
|
||||
- const: allwinner,sun9i-a80-apb0-gates-clk
|
||||
- const: allwinner,sun8i-a83t-apb0-gates-clk
|
||||
- const: allwinner,sun4i-a10-apb1-gates-clk
|
||||
- const: allwinner,sun5i-a13-apb1-gates-clk
|
||||
- const: allwinner,sun5i-a10s-apb1-gates-clk
|
||||
- const: allwinner,sun6i-a31-apb1-gates-clk
|
||||
- const: allwinner,sun7i-a20-apb1-gates-clk
|
||||
- const: allwinner,sun8i-a23-apb1-gates-clk
|
||||
- const: allwinner,sun9i-a80-apb1-gates-clk
|
||||
- const: allwinner,sun6i-a31-apb2-gates-clk
|
||||
- const: allwinner,sun8i-a23-apb2-gates-clk
|
||||
- const: allwinner,sun8i-a83t-bus-gates-clk
|
||||
- const: allwinner,sun9i-a80-apbs-gates-clk
|
||||
- const: allwinner,sun4i-a10-dram-gates-clk
|
||||
|
||||
- items:
|
||||
- const: allwinner,sun5i-a13-dram-gates-clk
|
||||
- const: allwinner,sun4i-a10-gates-clk
|
||||
|
||||
- items:
|
||||
- const: allwinner,sun8i-h3-apb0-gates-clk
|
||||
- const: allwinner,sun4i-a10-gates-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-indices:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
clock-output-names:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-indices
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c2005c {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-axi-gates-clk";
|
||||
reg = <0x01c2005c 0x4>;
|
||||
clocks = <&axi>;
|
||||
clock-indices = <0>;
|
||||
clock-output-names = "axi_dram";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@1c20060 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-ahb-gates-clk";
|
||||
reg = <0x01c20060 0x8>;
|
||||
clocks = <&ahb>;
|
||||
clock-indices = <0>, <1>,
|
||||
<2>, <3>,
|
||||
<4>, <5>, <6>,
|
||||
<7>, <8>, <9>,
|
||||
<10>, <11>, <12>,
|
||||
<13>, <14>, <16>,
|
||||
<17>, <18>, <20>,
|
||||
<21>, <22>, <23>,
|
||||
<24>, <25>, <26>,
|
||||
<32>, <33>, <34>,
|
||||
<35>, <36>, <37>,
|
||||
<40>, <41>, <43>,
|
||||
<44>, <45>,
|
||||
<46>, <47>,
|
||||
<50>, <52>;
|
||||
clock-output-names = "ahb_usb0", "ahb_ehci0",
|
||||
"ahb_ohci0", "ahb_ehci1",
|
||||
"ahb_ohci1", "ahb_ss", "ahb_dma",
|
||||
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
|
||||
"ahb_mmc2", "ahb_mmc3", "ahb_ms",
|
||||
"ahb_nand", "ahb_sdram", "ahb_ace",
|
||||
"ahb_emac", "ahb_ts", "ahb_spi0",
|
||||
"ahb_spi1", "ahb_spi2", "ahb_spi3",
|
||||
"ahb_pata", "ahb_sata", "ahb_gps",
|
||||
"ahb_ve", "ahb_tvd", "ahb_tve0",
|
||||
"ahb_tve1", "ahb_lcd0", "ahb_lcd1",
|
||||
"ahb_csi0", "ahb_csi1", "ahb_hdmi",
|
||||
"ahb_de_be0", "ahb_de_be1",
|
||||
"ahb_de_fe0", "ahb_de_fe1",
|
||||
"ahb_mp", "ahb_mali400";
|
||||
};
|
||||
|
||||
|
||||
- |
|
||||
clk@1c20068 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-apb0-gates-clk";
|
||||
reg = <0x01c20068 0x4>;
|
||||
clocks = <&apb0>;
|
||||
clock-indices = <0>, <1>,
|
||||
<2>, <3>,
|
||||
<5>, <6>,
|
||||
<7>, <10>;
|
||||
clock-output-names = "apb0_codec", "apb0_spdif",
|
||||
"apb0_ac97", "apb0_iis",
|
||||
"apb0_pio", "apb0_ir0",
|
||||
"apb0_ir1", "apb0_keypad";
|
||||
};
|
||||
|
||||
...
|
63
Bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml
Normal file
63
Bindings/clock/allwinner,sun4i-a10-mbus-clk.yaml
Normal file
@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mbus-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 MBUS Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun5i-a13-mbus-clk
|
||||
- allwinner,sun8i-a23-mbus-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c2015c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun5i-a13-mbus-clk";
|
||||
reg = <0x01c2015c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mbus";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@1c2015c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun8i-a23-mbus-clk";
|
||||
reg = <0x01c2015c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5>;
|
||||
clock-output-names = "mbus";
|
||||
};
|
||||
|
||||
...
|
87
Bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml
Normal file
87
Bindings/clock/allwinner,sun4i-a10-mmc-clk.yaml
Normal file
@ -0,0 +1,87 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mmc-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 Module 1 Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: >
|
||||
There is three different outputs: the main clock, with the ID 0,
|
||||
and the output and sample clocks, with the IDs 1 and 2,
|
||||
respectively.
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun4i-a10-mmc-clk
|
||||
- allwinner,sun9i-a80-mmc-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 3
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun4i-a10-mmc-clk
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 3
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20088 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-mmc-clk";
|
||||
reg = <0x01c20088 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc0",
|
||||
"mmc0_output",
|
||||
"mmc0_sample";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@6000410 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun9i-a80-mmc-clk";
|
||||
reg = <0x06000410 0x4>;
|
||||
clocks = <&osc24M>, <&pll4>;
|
||||
clock-output-names = "mmc0", "mmc0_output",
|
||||
"mmc0_sample";
|
||||
};
|
||||
|
||||
...
|
80
Bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml
Normal file
80
Bindings/clock/allwinner,sun4i-a10-mod0-clk.yaml
Normal file
@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod0-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 Module 0 Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- allwinner,sun4i-a10-mod0-clk
|
||||
- allwinner,sun9i-a80-mod0-clk
|
||||
|
||||
# The PRCM on the A31 and A23 will have the reg property missing,
|
||||
# since it's set at the upper level node, and will be validated by
|
||||
# PRCM's schema. Make sure we only validate standalone nodes.
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun4i-a10-mod0-clk
|
||||
- allwinner,sun9i-a80-mod0-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
# On the A80, the PRCM mod0 clocks have 2 parents.
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20080 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x01c20080 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@8001454 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
reg = <0x08001454 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>;
|
||||
clock-output-names = "r_ir";
|
||||
};
|
||||
|
||||
...
|
57
Bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml
Normal file
57
Bindings/clock/allwinner,sun4i-a10-mod1-clk.yaml
Normal file
@ -0,0 +1,57 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod1-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 Module 1 Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-mod1-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/sun4i-a10-pll2.h>
|
||||
|
||||
clk@1c200c0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod1-clk";
|
||||
reg = <0x01c200c0 0x4>;
|
||||
clocks = <&pll2 SUN4I_A10_PLL2_8X>,
|
||||
<&pll2 SUN4I_A10_PLL2_4X>,
|
||||
<&pll2 SUN4I_A10_PLL2_2X>,
|
||||
<&pll2 SUN4I_A10_PLL2_1X>;
|
||||
clock-output-names = "spdif";
|
||||
};
|
||||
|
||||
...
|
51
Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml
Normal file
51
Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 Gatable Oscillator Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-osc-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clock-frequency:
|
||||
description: >
|
||||
Frequency of the main oscillator.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clock-frequency
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
osc24M: clk@1c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-osc-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc24M";
|
||||
};
|
||||
|
||||
...
|
71
Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml
Normal file
71
Bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml
Normal file
@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 CPU PLL Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun4i-a10-pll1-clk
|
||||
- allwinner,sun6i-a31-pll1-clk
|
||||
- allwinner,sun8i-a23-pll1-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-pll1";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "osc24M";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@1c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun6i-a31-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll1";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@1c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun8i-a23-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll1";
|
||||
};
|
||||
|
||||
...
|
50
Bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml
Normal file
50
Bindings/clock/allwinner,sun4i-a10-pll3-clk.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 Video PLL Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-pll3-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20010 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-pll3-clk";
|
||||
reg = <0x01c20010 0x4>;
|
||||
clocks = <&osc3M>;
|
||||
clock-output-names = "pll3";
|
||||
};
|
||||
|
||||
...
|
53
Bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml
Normal file
53
Bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml
Normal file
@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 DRAM PLL Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: >
|
||||
The first output is the DRAM clock output, the second is meant
|
||||
for peripherals on the SoC.
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-pll5-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20020 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-pll5-clk";
|
||||
reg = <0x01c20020 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll5_ddr", "pll5_other";
|
||||
};
|
||||
|
||||
...
|
53
Bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml
Normal file
53
Bindings/clock/allwinner,sun4i-a10-pll6-clk.yaml
Normal file
@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 Peripheral PLL Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: >
|
||||
The first output is the SATA clock output, the second is the
|
||||
regular PLL output, the third is a PLL output at twice the rate.
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-pll6-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 3
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20028 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-pll6-clk";
|
||||
reg = <0x01c20028 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll6_sata", "pll6_other", "pll6";
|
||||
};
|
||||
|
||||
...
|
77
Bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml
Normal file
77
Bindings/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml
Normal file
@ -0,0 +1,77 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 TCON Channel 0 Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun4i-a10-tcon-ch0-clk
|
||||
- allwinner,sun4i-a10-tcon-ch1-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun4i-a10-tcon-ch0-clk
|
||||
|
||||
then:
|
||||
required:
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20118 {
|
||||
#clock-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
|
||||
reg = <0x01c20118 0x4>;
|
||||
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
|
||||
clock-output-names = "tcon-ch0-sclk";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@1c2012c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
|
||||
reg = <0x01c2012c 0x4>;
|
||||
clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
|
||||
clock-output-names = "tcon-ch1-sclk";
|
||||
};
|
||||
|
||||
...
|
166
Bindings/clock/allwinner,sun4i-a10-usb-clk.yaml
Normal file
166
Bindings/clock/allwinner,sun4i-a10-usb-clk.yaml
Normal file
@ -0,0 +1,166 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-usb-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 USB Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: >
|
||||
The additional ID argument passed to the clock shall refer to
|
||||
the index of the output.
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun4i-a10-usb-clk
|
||||
- allwinner,sun5i-a13-usb-clk
|
||||
- allwinner,sun6i-a31-usb-clk
|
||||
- allwinner,sun8i-a23-usb-clk
|
||||
- allwinner,sun8i-h3-usb-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
minItems: 2
|
||||
maxItems: 8
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun4i-a10-usb-clk
|
||||
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
maxItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun5i-a13-usb-clk
|
||||
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
maxItems: 2
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun6i-a31-usb-clk
|
||||
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
maxItems: 6
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun8i-a23-usb-clk
|
||||
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
maxItems: 5
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun8i-h3-usb-clk
|
||||
|
||||
then:
|
||||
properties:
|
||||
clock-output-names:
|
||||
maxItems: 8
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c200cc {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-usb-clk";
|
||||
reg = <0x01c200cc 0x4>;
|
||||
clocks = <&pll6 1>;
|
||||
clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@1c200cc {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun5i-a13-usb-clk";
|
||||
reg = <0x01c200cc 0x4>;
|
||||
clocks = <&pll6 1>;
|
||||
clock-output-names = "usb_ohci0", "usb_phy";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@1c200cc {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-usb-clk";
|
||||
reg = <0x01c200cc 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
|
||||
"usb_ohci0", "usb_ohci1",
|
||||
"usb_ohci2";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@1c200cc {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun8i-a23-usb-clk";
|
||||
reg = <0x01c200cc 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
|
||||
"usb_hsic_12M", "usb_ohci0";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@1c200cc {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun8i-h3-usb-clk";
|
||||
reg = <0x01c200cc 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "usb_phy0", "usb_phy1",
|
||||
"usb_phy2", "usb_phy3",
|
||||
"usb_ohci0", "usb_ohci1",
|
||||
"usb_ohci2", "usb_ohci3";
|
||||
};
|
||||
|
||||
...
|
55
Bindings/clock/allwinner,sun4i-a10-ve-clk.yaml
Normal file
55
Bindings/clock/allwinner,sun4i-a10-ve-clk.yaml
Normal file
@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ve-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 Video Engine Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
"#reset-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun4i-a10-ve-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c2013c {
|
||||
#clock-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-ve-clk";
|
||||
reg = <0x01c2013c 0x4>;
|
||||
clocks = <&pll4>;
|
||||
clock-output-names = "ve";
|
||||
};
|
||||
|
||||
...
|
52
Bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml
Normal file
52
Bindings/clock/allwinner,sun5i-a13-ahb-clk.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A13 AHB Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun5i-a13-ahb-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ahb@1c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun5i-a13-ahb-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&axi>, <&cpu>, <&pll6 1>;
|
||||
clock-output-names = "ahb";
|
||||
};
|
||||
|
||||
...
|
53
Bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml
Normal file
53
Bindings/clock/allwinner,sun6i-a31-pll6-clk.yaml
Normal file
@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A31 Peripheral PLL Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: >
|
||||
The first output is the regular PLL output, the second is a PLL
|
||||
output at twice the rate.
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun6i-a31-pll6-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20028 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-pll6-clk";
|
||||
reg = <0x01c20028 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll6", "pll6x2";
|
||||
};
|
||||
|
||||
...
|
51
Bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml
Normal file
51
Bindings/clock/allwinner,sun7i-a20-gmac-clk.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-gmac-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A20 GMAC TX Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun7i-a20-gmac-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
description: >
|
||||
The parent clocks shall be fixed rate dummy clocks at 25 MHz and
|
||||
125 MHz, respectively.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20164 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun7i-a20-gmac-clk";
|
||||
reg = <0x01c20164 0x4>;
|
||||
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
|
||||
clock-output-names = "gmac_tx";
|
||||
};
|
||||
|
||||
...
|
52
Bindings/clock/allwinner,sun7i-a20-out-clk.yaml
Normal file
52
Bindings/clock/allwinner,sun7i-a20-out-clk.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun7i-a20-out-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A20 Output Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun7i-a20-out-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c201f0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun7i-a20-out-clk";
|
||||
reg = <0x01c201f0 0x4>;
|
||||
clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
|
||||
clock-output-names = "clk_out_a";
|
||||
};
|
||||
|
||||
...
|
76
Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
Normal file
76
Bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
Normal file
@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun8i-a83t-de2-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A83t Display Engine 2/3 Clock Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: allwinner,sun8i-a83t-de2-clk
|
||||
- const: allwinner,sun8i-h3-de2-clk
|
||||
- const: allwinner,sun8i-v3s-de2-clk
|
||||
- const: allwinner,sun50i-a64-de2-clk
|
||||
- const: allwinner,sun50i-h5-de2-clk
|
||||
- const: allwinner,sun50i-h6-de2-clk
|
||||
- items:
|
||||
- const: allwinner,sun8i-r40-de2-clk
|
||||
- const: allwinner,sun8i-h3-de2-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Bus Clock
|
||||
- description: Module Clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: mod
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/sun8i-h3-ccu.h>
|
||||
#include <dt-bindings/reset/sun8i-h3-ccu.h>
|
||||
|
||||
de2_clocks: clock@1000000 {
|
||||
compatible = "allwinner,sun8i-h3-de2-clk";
|
||||
reg = <0x01000000 0x100000>;
|
||||
clocks = <&ccu CLK_BUS_DE>,
|
||||
<&ccu CLK_DE>;
|
||||
clock-names = "bus",
|
||||
"mod";
|
||||
resets = <&ccu RST_BUS_DE>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
103
Bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml
Normal file
103
Bindings/clock/allwinner,sun8i-h3-bus-gates-clk.yaml
Normal file
@ -0,0 +1,103 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 Bus Gates Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: >
|
||||
This additional argument passed to that clock is the offset of
|
||||
the bit controlling this particular gate in the register.
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun8i-h3-bus-gates-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
maxItems: 4
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-indices:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
clock-output-names:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-indices
|
||||
- clock-names
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c20060 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun8i-h3-bus-gates-clk";
|
||||
reg = <0x01c20060 0x14>;
|
||||
clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
|
||||
clock-names = "ahb1", "ahb2", "apb1", "apb2";
|
||||
clock-indices = <5>, <6>, <8>,
|
||||
<9>, <10>, <13>,
|
||||
<14>, <17>, <18>,
|
||||
<19>, <20>,
|
||||
<21>, <23>,
|
||||
<24>, <25>,
|
||||
<26>, <27>,
|
||||
<28>, <29>,
|
||||
<30>, <31>, <32>,
|
||||
<35>, <36>, <37>,
|
||||
<40>, <41>, <43>,
|
||||
<44>, <52>, <53>,
|
||||
<54>, <64>,
|
||||
<65>, <69>, <72>,
|
||||
<76>, <77>, <78>,
|
||||
<96>, <97>, <98>,
|
||||
<112>, <113>,
|
||||
<114>, <115>,
|
||||
<116>, <128>, <135>;
|
||||
clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
|
||||
"bus_mmc1", "bus_mmc2", "bus_nand",
|
||||
"bus_sdram", "bus_gmac", "bus_ts",
|
||||
"bus_hstimer", "bus_spi0",
|
||||
"bus_spi1", "bus_otg",
|
||||
"bus_otg_ehci0", "bus_ehci1",
|
||||
"bus_ehci2", "bus_ehci3",
|
||||
"bus_otg_ohci0", "bus_ohci1",
|
||||
"bus_ohci2", "bus_ohci3", "bus_ve",
|
||||
"bus_lcd0", "bus_lcd1", "bus_deint",
|
||||
"bus_csi", "bus_tve", "bus_hdmi",
|
||||
"bus_de", "bus_gpu", "bus_msgbox",
|
||||
"bus_spinlock", "bus_codec",
|
||||
"bus_spdif", "bus_pio", "bus_ths",
|
||||
"bus_i2s0", "bus_i2s1", "bus_i2s2",
|
||||
"bus_i2c0", "bus_i2c1", "bus_i2c2",
|
||||
"bus_uart0", "bus_uart1",
|
||||
"bus_uart2", "bus_uart3",
|
||||
"bus_scr", "bus_ephy", "bus_dbg";
|
||||
};
|
||||
|
||||
...
|
52
Bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml
Normal file
52
Bindings/clock/allwinner,sun9i-a80-ahb-clk.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 AHB Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun9i-a80-ahb-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@6000060 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun9i-a80-ahb-clk";
|
||||
reg = <0x06000060 0x4>;
|
||||
clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
|
||||
clock-output-names = "ahb0";
|
||||
};
|
||||
|
||||
...
|
63
Bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml
Normal file
63
Bindings/clock/allwinner,sun9i-a80-apb0-clk.yaml
Normal file
@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 APB0 Bus Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun9i-a80-apb0-clk
|
||||
- allwinner,sun9i-a80-apb1-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@6000070 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun9i-a80-apb0-clk";
|
||||
reg = <0x06000070 0x4>;
|
||||
clocks = <&osc24M>, <&pll4>;
|
||||
clock-output-names = "apb0";
|
||||
};
|
||||
|
||||
- |
|
||||
clk@6000074 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun9i-a80-apb1-clk";
|
||||
reg = <0x06000074 0x4>;
|
||||
clocks = <&osc24M>, <&pll4>;
|
||||
clock-output-names = "apb1";
|
||||
};
|
||||
|
||||
...
|
52
Bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml
Normal file
52
Bindings/clock/allwinner,sun9i-a80-cpus-clk.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-cpus-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 CPUS Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun9i-a80-cpus-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@8001410 {
|
||||
compatible = "allwinner,sun9i-a80-cpus-clk";
|
||||
reg = <0x08001410 0x4>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
|
||||
clock-output-names = "cpus";
|
||||
};
|
||||
|
||||
...
|
67
Bindings/clock/allwinner,sun9i-a80-de-clks.yaml
Normal file
67
Bindings/clock/allwinner,sun9i-a80-de-clks.yaml
Normal file
@ -0,0 +1,67 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-de-clks.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 Display Engine Clock Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun9i-a80-de-clks
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Bus Clock
|
||||
- description: RAM Bus Clock
|
||||
- description: Module Clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: mod
|
||||
- const: dram
|
||||
- const: bus
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/sun9i-a80-ccu.h>
|
||||
#include <dt-bindings/reset/sun9i-a80-ccu.h>
|
||||
|
||||
de_clocks: clock@3000000 {
|
||||
compatible = "allwinner,sun9i-a80-de-clks";
|
||||
reg = <0x03000000 0x30>;
|
||||
clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
|
||||
clock-names = "mod", "dram", "bus";
|
||||
resets = <&ccu RST_BUS_DE>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
52
Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml
Normal file
52
Bindings/clock/allwinner,sun9i-a80-gt-clk.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-gt-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 GT Bus Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun9i-a80-gt-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
description: >
|
||||
The parent order must match the hardware programming order.
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@600005c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun9i-a80-gt-clk";
|
||||
reg = <0x0600005c 0x4>;
|
||||
clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
|
||||
clock-output-names = "gt";
|
||||
};
|
||||
|
||||
...
|
68
Bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml
Normal file
68
Bindings/clock/allwinner,sun9i-a80-mmc-config-clk.yaml
Normal file
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-mmc-config-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 MMC Configuration Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
description: >
|
||||
There is one clock/reset output per mmc controller. The number of
|
||||
outputs is determined by the size of the address block, which is
|
||||
related to the overall mmc block.
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: >
|
||||
The additional ID argument passed to the clock shall refer to
|
||||
the index of the output.
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun9i-a80-mmc-config-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 4
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@1c13000 {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun9i-a80-mmc-config-clk";
|
||||
reg = <0x01c13000 0x10>;
|
||||
clocks = <&ahb0_gates 8>;
|
||||
resets = <&ahb0_resets 8>;
|
||||
clock-output-names = "mmc0_config", "mmc1_config",
|
||||
"mmc2_config", "mmc3_config";
|
||||
};
|
||||
|
||||
...
|
50
Bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml
Normal file
50
Bindings/clock/allwinner,sun9i-a80-pll4-clk.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 Peripheral PLL Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun9i-a80-pll4-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@600000c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun9i-a80-pll4-clk";
|
||||
reg = <0x0600000c 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll4";
|
||||
};
|
||||
|
||||
...
|
59
Bindings/clock/allwinner,sun9i-a80-usb-clocks.yaml
Normal file
59
Bindings/clock/allwinner,sun9i-a80-usb-clocks.yaml
Normal file
@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-clocks.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 USB Clock Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun9i-a80-usb-clocks
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Bus Clock
|
||||
- description: High Frequency Oscillator
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: hosc
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/sun9i-a80-ccu.h>
|
||||
|
||||
usb_clocks: clock@a08000 {
|
||||
compatible = "allwinner,sun9i-a80-usb-clks";
|
||||
reg = <0x00a08000 0x8>;
|
||||
clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
|
||||
clock-names = "bus", "hosc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
60
Bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml
Normal file
60
Bindings/clock/allwinner,sun9i-a80-usb-mod-clk.yaml
Normal file
@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-mod-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 USB Module Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: >
|
||||
The additional ID argument passed to the clock shall refer to
|
||||
the index of the output.
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun9i-a80-usb-mod-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 6
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@a08000 {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun9i-a80-usb-mod-clk";
|
||||
reg = <0x00a08000 0x4>;
|
||||
clocks = <&ahb1_gates 1>;
|
||||
clock-output-names = "usb0_ahb", "usb_ohci0",
|
||||
"usb1_ahb", "usb_ohci1",
|
||||
"usb2_ahb", "usb_ohci2";
|
||||
};
|
||||
|
||||
...
|
60
Bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml
Normal file
60
Bindings/clock/allwinner,sun9i-a80-usb-phy-clk.yaml
Normal file
@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-usb-phy-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A80 USB PHY Clock Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
deprecated: true
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description: >
|
||||
The additional ID argument passed to the clock shall refer to
|
||||
the index of the output.
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
const: allwinner,sun9i-a80-usb-phy-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 6
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk@a08004 {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun9i-a80-usb-phy-clk";
|
||||
reg = <0x00a08004 0x4>;
|
||||
clocks = <&ahb1_gates 1>;
|
||||
clock-output-names = "usb_phy0", "usb_hsic1_480M",
|
||||
"usb_phy1", "usb_hsic2_480M",
|
||||
"usb_phy2", "usb_hsic_12M";
|
||||
};
|
||||
|
||||
...
|
50
Bindings/clock/amlogic,meson8-ddr-clkc.yaml
Normal file
50
Bindings/clock/amlogic,meson8-ddr-clkc.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic DDR Clock Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson8-ddr-clkc
|
||||
- amlogic,meson8b-ddr-clkc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xtal
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ddr_clkc: clock-controller@400 {
|
||||
compatible = "amlogic,meson8-ddr-clkc";
|
||||
reg = <0x400 0x20>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "xtal";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
@ -11,6 +11,11 @@ Required Properties:
|
||||
- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
- clocks: list of clock phandles, one for each entry in clock-names
|
||||
- clock-names: should contain the following:
|
||||
* "xtal": the 24MHz system oscillator
|
||||
* "ddr_pll": the DDR PLL clock
|
||||
* "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"
|
||||
|
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/bitmain,bm1880-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Bitmain BM1880 Clock Controller
|
||||
|
54
Bindings/clock/fsl,plldig.yaml
Normal file
54
Bindings/clock/fsl,plldig.yaml
Normal file
@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
|
||||
|
||||
maintainers:
|
||||
- Wen He <wen.he_1@nxp.com>
|
||||
|
||||
description: |
|
||||
NXP LS1028A has a clock domain PXLCLK0 used for the Display output
|
||||
interface in the display core, as implemented in TSMC CLN28HPM PLL.
|
||||
which generate and offers pixel clocks to Display.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,ls1028a-plldig
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
fsl,vco-hz:
|
||||
description: Optional for VCO frequency of the PLL in Hertz.
|
||||
The VCO frequency of this PLL cannot be changed during runtime
|
||||
only at startup. Therefore, the output frequencies are very
|
||||
limited and might not even closely match the requested frequency.
|
||||
To work around this restriction the user may specify its own
|
||||
desired VCO frequency for the PLL.
|
||||
minimum: 650000000
|
||||
maximum: 1300000000
|
||||
default: 1188000000
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Display PIXEL Clock node:
|
||||
- |
|
||||
dpclk: clock-display@f1f0000 {
|
||||
compatible = "fsl,ls1028a-plldig";
|
||||
reg = <0x0 0xf1f0000 0x0 0xffff>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&osc_27m>;
|
||||
};
|
||||
|
||||
...
|
55
Bindings/clock/fsl,sai-clock.yaml
Normal file
55
Bindings/clock/fsl,sai-clock.yaml
Normal file
@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale SAI bitclock-as-a-clock binding
|
||||
|
||||
maintainers:
|
||||
- Michael Walle <michael@walle.cc>
|
||||
|
||||
description: |
|
||||
It is possible to use the BCLK pin of a SAI module as a generic clock
|
||||
output. Some SoC are very constrained in their pin multiplexer
|
||||
configuration. Eg. pins can only be changed groups. For example, on the
|
||||
LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
|
||||
the second pins are wasted. Using this binding it is possible to use the
|
||||
clock of the second SAI as a MCLK clock for an audio codec, for example.
|
||||
|
||||
This is a composite of a gated clock and a divider clock.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,vf610-sai-clock
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
mclk: clock-mclk@f130080 {
|
||||
compatible = "fsl,vf610-sai-clock";
|
||||
reg = <0x0 0xf130080 0x0 0x80>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&parentclk>;
|
||||
};
|
||||
};
|
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/imx8mn-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8M Nano Clock Control Module Binding
|
||||
|
68
Bindings/clock/imx8mp-clock.yaml
Normal file
68
Bindings/clock/imx8mp-clock.yaml
Normal file
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx8mp-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8M Plus Clock Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description:
|
||||
NXP i.MX8M Plus clock control module is an integrated clock controller, which
|
||||
generates and supplies to all modules.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mp-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 24m osc
|
||||
- description: ext1 clock input
|
||||
- description: ext2 clock input
|
||||
- description: ext3 clock input
|
||||
- description: ext4 clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: osc_32k
|
||||
- const: osc_24m
|
||||
- const: clk_ext1
|
||||
- const: clk_ext2
|
||||
- const: clk_ext3
|
||||
- const: clk_ext4
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
|
||||
for the full list of i.MX8M Plus clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mp-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
|
||||
<&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1",
|
||||
"clk_ext2", "clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
...
|
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/clock/milbeaut-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/milbeaut-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Milbeaut SoCs Clock Controller Binding
|
||||
|
@ -1,19 +0,0 @@
|
||||
Qualcomm Technologies, Inc. Display Clock Controller Binding
|
||||
------------------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
|
||||
- compatible : shall contain "qcom,sdm845-dispcc"
|
||||
- reg : shall contain base register location and length.
|
||||
- #clock-cells : from common clock binding, shall contain 1.
|
||||
- #reset-cells : from common reset binding, shall contain 1.
|
||||
- #power-domain-cells : from generic power domain binding, shall contain 1.
|
||||
|
||||
Example:
|
||||
dispcc: clock-controller@af00000 {
|
||||
compatible = "qcom,sdm845-dispcc";
|
||||
reg = <0xaf00000 0x100000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
83
Bindings/clock/qcom,gcc-apq8064.yaml
Normal file
83
Bindings/clock/qcom,gcc-apq8064.yaml
Normal file
@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on APQ8064.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8960.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8960.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-apq8064
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
Qualcomm TSENS (thermal sensor device) on some devices can
|
||||
be part of GCC and hence the TSENS properties can also be part
|
||||
of the GCC/clock-controller node.
|
||||
For more details on the TSENS properties please refer
|
||||
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
|
||||
|
||||
nvmem-cell-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: calib
|
||||
- const: calib_backup
|
||||
|
||||
'#thermal-sensor-cells':
|
||||
const: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
- nvmem-cells
|
||||
- nvmem-cell-names
|
||||
- '#thermal-sensor-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-apq8064";
|
||||
reg = <0x00900000 0x4000>;
|
||||
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
nvmem-cell-names = "calib", "calib_backup";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
...
|
51
Bindings/clock/qcom,gcc-ipq8074.yaml
Normal file
51
Bindings/clock/qcom,gcc-ipq8074.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Bindingfor IPQ8074
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on IPQ8074.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-ipq8074.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-ipq8074
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
compatible = "qcom,gcc-ipq8074";
|
||||
reg = <0x01800000 0x80000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
68
Bindings/clock/qcom,gcc-msm8996.yaml
Normal file
68
Bindings/clock/qcom,gcc-msm8996.yaml
Normal file
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8996
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8996.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8996.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-msm8996
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Second XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: cxo
|
||||
- const: cxo2
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@300000 {
|
||||
compatible = "qcom,gcc-msm8996";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x300000 0x90000>;
|
||||
};
|
||||
...
|
93
Bindings/clock/qcom,gcc-msm8998.yaml
Normal file
93
Bindings/clock/qcom,gcc-msm8998.yaml
Normal file
@ -0,0 +1,93 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8998
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8998.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8998.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-msm8998
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: USB 3.0 phy pipe clock
|
||||
- description: UFS phy rx symbol clock for pipe 0
|
||||
- description: UFS phy rx symbol clock for pipe 1
|
||||
- description: UFS phy tx symbol clock
|
||||
- description: PCIE phy pipe clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
- const: usb3_pipe
|
||||
- const: ufs_rx_symbol0
|
||||
- const: ufs_rx_symbol1
|
||||
- const: ufs_tx_symbol0
|
||||
- const: pcie0_pipe
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-msm8998";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x00100000 0xb0000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&sleep>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<0>;
|
||||
clock-names = "xo",
|
||||
"sleep_clk",
|
||||
"usb3_pipe",
|
||||
"ufs_rx_symbol0",
|
||||
"ufs_rx_symbol1",
|
||||
"ufs_tx_symbol0",
|
||||
"pcie0_pipe";
|
||||
};
|
||||
...
|
51
Bindings/clock/qcom,gcc-qcs404.yaml
Normal file
51
Bindings/clock/qcom,gcc-qcs404.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Bindingfor QCS404
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on QCS404.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-qcs404.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-qcs404
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@1800000 {
|
||||
compatible = "qcom,gcc-qcs404";
|
||||
reg = <0x01800000 0x80000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
75
Bindings/clock/qcom,gcc-sc7180.yaml
Normal file
75
Bindings/clock/qcom,gcc-sc7180.yaml
Normal file
@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sc7180.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sc7180
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc7180";
|
||||
reg = <0 0x00100000 0 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
72
Bindings/clock/qcom,gcc-sm8150.yaml
Normal file
72
Bindings/clock/qcom,gcc-sm8150.yaml
Normal file
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8150
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8150.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8150.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm8150
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8150";
|
||||
reg = <0 0x00100000 0 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/clock/qcom,gcc.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding
|
||||
@ -14,46 +14,42 @@ description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8974.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8974.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8994.h
|
||||
- dt-bindings/clock/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/reset/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
|
||||
- dt-bindings/clock/qcom,gcc-sdm845.h
|
||||
|
||||
properties:
|
||||
compatible :
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-apq8064
|
||||
- qcom,gcc-apq8084
|
||||
- qcom,gcc-ipq8064
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq8074
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
- qcom,gcc-msm8994
|
||||
- qcom,gcc-msm8996
|
||||
- qcom,gcc-msm8998
|
||||
- qcom,gcc-mdm9615
|
||||
- qcom,gcc-qcs404
|
||||
- qcom,gcc-sc7180
|
||||
- qcom,gcc-sdm630
|
||||
- qcom,gcc-sdm660
|
||||
- qcom,gcc-sdm845
|
||||
- qcom,gcc-sm8150
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
- qcom,gcc-apq8084
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-ipq8064
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
- qcom,gcc-msm8994
|
||||
- qcom,gcc-mdm9615
|
||||
- qcom,gcc-sdm630
|
||||
- qcom,gcc-sdm660
|
||||
- qcom,gcc-sdm845
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
@ -67,31 +63,9 @@ properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
Qualcomm TSENS (thermal sensor device) on some devices can
|
||||
be part of GCC and hence the TSENS properties can also be part
|
||||
of the GCC/clock-controller node.
|
||||
For more details on the TSENS properties please refer
|
||||
Documentation/devicetree/bindings/thermal/qcom-tsens.txt
|
||||
|
||||
nvmem-cell-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
Names for each nvmem-cells specified.
|
||||
items:
|
||||
- const: calib
|
||||
- const: calib_backup
|
||||
|
||||
'thermal-sensor-cells':
|
||||
const: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -100,32 +74,6 @@ required:
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,gcc-apq8064
|
||||
|
||||
then:
|
||||
required:
|
||||
- nvmem-cells
|
||||
- nvmem-cell-names
|
||||
- '#thermal-sensor-cells'
|
||||
|
||||
else:
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,gcc-sm8150
|
||||
- qcom,gcc-sc7180
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8960:
|
||||
- |
|
||||
@ -136,53 +84,4 @@ examples:
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
# Example of GCC with TSENS properties:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-apq8064";
|
||||
reg = <0x00900000 0x4000>;
|
||||
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
nvmem-cell-names = "calib", "calib_backup";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
# Example of GCC with protected-clocks properties:
|
||||
- |
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sdm845";
|
||||
reg = <0x100000 0x1f0000>;
|
||||
protected-clocks = <187>, <188>, <189>, <190>, <191>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
# Example of GCC with clock node properties for SM8150:
|
||||
- |
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8150";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc 0>, <&rpmhcc 1>, <&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
# Example of GCC with clock nodes properties for SC7180:
|
||||
- |
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc7180";
|
||||
reg = <0x100000 0x1f0000>;
|
||||
clocks = <&rpmhcc 0>, <&rpmhcc 1>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
@ -1,24 +0,0 @@
|
||||
Qualcomm Graphics Clock & Reset Controller Binding
|
||||
--------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc"
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : from common clock binding, shall contain 1
|
||||
- #reset-cells : from common reset binding, shall contain 1
|
||||
- #power-domain-cells : from generic power domain binding, shall contain 1
|
||||
- clocks : shall contain the XO clock
|
||||
shall contain the gpll0 out main clock (msm8998)
|
||||
- clock-names : shall be "xo"
|
||||
shall be "gpll0" (msm8998)
|
||||
|
||||
Example:
|
||||
gpucc: clock-controller@5090000 {
|
||||
compatible = "qcom,sdm845-gpucc";
|
||||
reg = <0x5090000 0x9000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "xo";
|
||||
};
|
@ -1,28 +0,0 @@
|
||||
Qualcomm Multimedia Clock & Reset Controller Binding
|
||||
----------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following:
|
||||
|
||||
"qcom,mmcc-apq8064"
|
||||
"qcom,mmcc-apq8084"
|
||||
"qcom,mmcc-msm8660"
|
||||
"qcom,mmcc-msm8960"
|
||||
"qcom,mmcc-msm8974"
|
||||
"qcom,mmcc-msm8996"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
- #reset-cells : shall contain 1
|
||||
|
||||
Optional properties :
|
||||
- #power-domain-cells : shall contain 1
|
||||
|
||||
Example:
|
||||
clock-controller@4000000 {
|
||||
compatible = "qcom,mmcc-msm8960";
|
||||
reg = <0x4000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
98
Bindings/clock/qcom,mmcc.yaml
Normal file
98
Bindings/clock/qcom,mmcc.yaml
Normal file
@ -0,0 +1,98 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Multimedia Clock & Reset Controller Binding
|
||||
|
||||
maintainers:
|
||||
- Jeffrey Hugo <jhugo@codeaurora.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm multimedia clock control module which supports the clocks, resets and
|
||||
power domains.
|
||||
|
||||
properties:
|
||||
compatible :
|
||||
enum:
|
||||
- qcom,mmcc-apq8064
|
||||
- qcom,mmcc-apq8084
|
||||
- qcom,mmcc-msm8660
|
||||
- qcom,mmcc-msm8960
|
||||
- qcom,mmcc-msm8974
|
||||
- qcom,mmcc-msm8996
|
||||
- qcom,mmcc-msm8998
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board sleep source
|
||||
- description: Global PLL 0 clock
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
- description: DSI phy instance 1 dsi clock
|
||||
- description: DSI phy instance 1 byte clock
|
||||
- description: HDMI phy PLL clock
|
||||
- description: DisplayPort phy PLL vco clock
|
||||
- description: DisplayPort phy PLL link clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep
|
||||
- const: gpll0
|
||||
- const: dsi0dsi
|
||||
- const: dsi0byte
|
||||
- const: dsi1dsi
|
||||
- const: dsi1byte
|
||||
- const: hdmipll
|
||||
- const: dpvco
|
||||
- const: dplink
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,mmcc-msm8998
|
||||
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
# Example for MMCC for MSM8960:
|
||||
- |
|
||||
clock-controller@4000000 {
|
||||
compatible = "qcom,mmcc-msm8960";
|
||||
reg = <0x4000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
66
Bindings/clock/qcom,msm8998-gpucc.yaml
Normal file
66
Bindings/clock/qcom,msm8998-gpucc.yaml
Normal file
@ -0,0 +1,66 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on MSM8998.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-msm8998.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,msm8998-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: gpll0
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
clock-controller@5065000 {
|
||||
compatible = "qcom,msm8998-gpucc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0x05065000 0x9000>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0_OUT_MAIN>;
|
||||
clock-names = "xo", "gpll0";
|
||||
};
|
||||
...
|
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/clock/qcom,rpmhcc.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/qcom,rpmhcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. RPMh Clocks Bindings
|
||||
|
84
Bindings/clock/qcom,sc7180-dispcc.yaml
Normal file
84
Bindings/clock/qcom,sc7180-dispcc.yaml
Normal file
@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-sc7180.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: Byte clock from DSI PHY
|
||||
- description: Pixel clock from DSI PHY
|
||||
- description: Link clock from DP PHY
|
||||
- description: VCO DIV clock from DP PHY
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_disp_gpll0_clk_src
|
||||
- const: dsi0_phy_pll_out_byteclk
|
||||
- const: dsi0_phy_pll_out_dsiclk
|
||||
- const: dp_phy_pll_link_clk
|
||||
- const: dp_phy_pll_vco_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sc7180-dispcc";
|
||||
reg = <0 0x0af00000 0 0x200000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
|
||||
<&dsi_phy 0>,
|
||||
<&dsi_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_disp_gpll0_clk_src",
|
||||
"dsi0_phy_pll_out_byteclk",
|
||||
"dsi0_phy_pll_out_dsiclk",
|
||||
"dp_phy_pll_link_clk",
|
||||
"dp_phy_pll_vco_div_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
72
Bindings/clock/qcom,sc7180-gpucc.yaml
Normal file
72
Bindings/clock/qcom,sc7180-gpucc.yaml
Normal file
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-sc7180.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_gpu_gpll0_clk_src
|
||||
- const: gcc_gpu_gpll0_div_clk_src
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@5090000 {
|
||||
compatible = "qcom,sc7180-gpucc";
|
||||
reg = <0 0x05090000 0 0x9000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_gpu_gpll0_clk_src",
|
||||
"gcc_gpu_gpll0_div_clk_src";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
63
Bindings/clock/qcom,sc7180-videocc.yaml
Normal file
63
Bindings/clock/qcom,sc7180-videocc.yaml
Normal file
@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-videocc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Video Clock & Reset Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
|
||||
See also dt-bindings/clock/qcom,videocc-sc7180.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-videocc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@ab00000 {
|
||||
compatible = "qcom,sc7180-videocc";
|
||||
reg = <0 0x0ab00000 0 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
99
Bindings/clock/qcom,sdm845-dispcc.yaml
Normal file
99
Bindings/clock/qcom,sdm845-dispcc.yaml
Normal file
@ -0,0 +1,99 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SDM845
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SDM845.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-sdm845.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-dispcc
|
||||
|
||||
# NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
|
||||
# The code had to use hardcoded mechanisms to find the input clocks.
|
||||
# New dts files should have these clocks.
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: GPLL0 div source from GCC
|
||||
- description: Byte clock from DSI PHY0
|
||||
- description: Pixel clock from DSI PHY0
|
||||
- description: Byte clock from DSI PHY1
|
||||
- description: Pixel clock from DSI PHY1
|
||||
- description: Link clock from DP PHY
|
||||
- description: VCO DIV clock from DP PHY
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_disp_gpll0_clk_src
|
||||
- const: gcc_disp_gpll0_div_clk_src
|
||||
- const: dsi0_phy_pll_out_byteclk
|
||||
- const: dsi0_phy_pll_out_dsiclk
|
||||
- const: dsi1_phy_pll_out_byteclk
|
||||
- const: dsi1_phy_pll_out_dsiclk
|
||||
- const: dp_link_clk_divsel_ten
|
||||
- const: dp_vco_divided_clk_src_mux
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sdm845-dispcc";
|
||||
reg = <0 0x0af00000 0 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi1_phy 0>,
|
||||
<&dsi1_phy 1>,
|
||||
<&dp_phy 0>,
|
||||
<&dp_phy 1>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_disp_gpll0_clk_src",
|
||||
"gcc_disp_gpll0_div_clk_src",
|
||||
"dsi0_phy_pll_out_byteclk",
|
||||
"dsi0_phy_pll_out_dsiclk",
|
||||
"dsi1_phy_pll_out_byteclk",
|
||||
"dsi1_phy_pll_out_dsiclk",
|
||||
"dp_link_clk_divsel_ten",
|
||||
"dp_vco_divided_clk_src_mux";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
72
Bindings/clock/qcom,sdm845-gpucc.yaml
Normal file
72
Bindings/clock/qcom,sdm845-gpucc.yaml
Normal file
@ -0,0 +1,72 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for SDM845
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on SDM845.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-sdm845.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main branch source
|
||||
- description: GPLL0 div branch source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: gcc_gpu_gpll0_clk_src
|
||||
- const: gcc_gpu_gpll0_div_clk_src
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@5090000 {
|
||||
compatible = "qcom,sdm845-gpucc";
|
||||
reg = <0 0x05090000 0 0x9000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
||||
clock-names = "bi_tcxo",
|
||||
"gcc_gpu_gpll0_clk_src",
|
||||
"gcc_gpu_gpll0_div_clk_src";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
63
Bindings/clock/qcom,sdm845-videocc.yaml
Normal file
63
Bindings/clock/qcom,sdm845-videocc.yaml
Normal file
@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-videocc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Video Clock & Reset Controller Binding for SDM845
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module which supports the clocks, resets and
|
||||
power domains on SDM845.
|
||||
|
||||
See also dt-bindings/clock/qcom,videocc-sdm845.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-videocc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@ab00000 {
|
||||
compatible = "qcom,sdm845-videocc";
|
||||
reg = <0 0x0ab00000 0 0x10000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
@ -1,18 +0,0 @@
|
||||
Qualcomm Video Clock & Reset Controller Binding
|
||||
-----------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain "qcom,sdm845-videocc"
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : from common clock binding, shall contain 1.
|
||||
- #power-domain-cells : from generic power domain binding, shall contain 1.
|
||||
- #reset-cells : from common reset binding, shall contain 1.
|
||||
|
||||
Example:
|
||||
videocc: clock-controller@ab00000 {
|
||||
compatible = "qcom,sdm845-videocc";
|
||||
reg = <0xab00000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user