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Add __divdf3(), __divsf3() and __infinity[].

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Obtained from:	Intel (for the divide code)
This commit is contained in:
Doug Rabson 2001-10-20 15:17:31 +00:00
parent 0eb6ce3169
commit 9466885ca4
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=85228
4 changed files with 296 additions and 1 deletions
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3
lib/libc/ia64/gen/Makefile.inc
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@ -1,6 +1,7 @@
# $FreeBSD$
SRCS+= _setjmp.S fabs.S frexp.c isinf.c ldexp.c modf.c setjmp.S
SRCS+= _setjmp.S fabs.S frexp.c infinity.c isinf.c ldexp.c modf.c setjmp.S
SRCS+= sigsetjmp.S
SRCS+= __divdi3.S __divsi3.S __moddi3.S __modsi3.S
SRCS+= __udivdi3.S __udivsi3.S __umoddi3.S __umodsi3.S
SRCS+= __divdf3.S __divsf3.S

143
lib/libc/ia64/gen/__divdf3.S Normal file
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// $FreeBSD$
//
// Copyright (c) 2000, Intel Corporation
// All rights reserved.
//
// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
// Intel Corporation.
//
// WARRANTY DISCLAIMER
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Intel Corporation is the author of this code, and requests that all
// problem reports or change requests be submitted to it directly at
// http://developer.intel.com/opensource.
//
#include <machine/asm.h>
.section .text
ENTRY(__divdf3, 0)
{ .mfi
// a is in f8
// b is in f9
// predicate registers used: p6
// floating-point registers used: f6, f7, f8, f9, f10, f11
// load a, the first argument, in f6
nop.m 0
mov f6=f8
nop.i 0
} { .mfi
// load b, the second argument, in f7
nop.m 0
mov f7=f9
nop.i 0;;
} { .mfi
// BEGIN DOUBLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM
nop.m 0
// Step (1)
// y0 = 1 / b in f8
frcpa.s0 f8,p6=f6,f7
nop.i 0;;
} { .mfi
nop.m 0
// Step (2)
// q0 = a * y0 in f9
(p6) fma.s1 f9=f6,f8,f0
nop.i 0
} { .mfi
nop.m 0
// Step (3)
// e0 = 1 - b * y0 in f10
(p6) fnma.s1 f10=f7,f8,f1
nop.i 0;;
} { .mfi
nop.m 0
// Step (4)
// q1 = q0 + e0 * q0 in f9
(p6) fma.s1 f9=f10,f9,f9
nop.i 0
} { .mfi
nop.m 0
// Step (5)
// e1 = e0 * e0 in f11
(p6) fma.s1 f11=f10,f10,f0
nop.i 0
} { .mfi
nop.m 0
// Step (6)
// y1 = y0 + e0 * y0 in f8
(p6) fma.s1 f8=f10,f8,f8
nop.i 0;;
} { .mfi
nop.m 0
// Step (7)
// q2 = q1 + e1 * q1 in f9
(p6) fma.s1 f9=f11,f9,f9
nop.i 0
} { .mfi
nop.m 0
// Step (8)
// e2 = e1 * e1 in f10
(p6) fma.s1 f10=f11,f11,f0
nop.i 0
} { .mfi
nop.m 0
// Step (9)
// y2 = y1 + e1 * y1 in f8
(p6) fma.s1 f8=f11,f8,f8
nop.i 0;;
} { .mfi
nop.m 0
// Step (10)
// q3 = q2 + e2 * q2 in f9
(p6) fma.d.s1 f9=f10,f9,f9
nop.i 0;;
} { .mfi
nop.m 0
// Step (11)
// y3 = y2 + e2 * y2 in f8
(p6) fma.s1 f8=f10,f8,f8
nop.i 0;;
} { .mfi
nop.m 0
// Step (12)
// r0 = a - b * q3 in f6
(p6) fnma.d.s1 f6=f7,f9,f6
nop.i 0;;
} { .mfi
nop.m 0
// Step (13)
// q4 = q3 + r0 * y3 in f8
(p6) fma.d.s0 f8=f6,f8,f9
nop.i 0;;
// END DOUBLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM
} { .mib
nop.m 0
nop.i 0
// return
br.ret.sptk b0;;
}
END(__divdf3)

117
lib/libc/ia64/gen/__divsf3.S Normal file
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// $FreeBSD$
//
// Copyright (c) 2000, Intel Corporation
// All rights reserved.
//
// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
// Intel Corporation.
//
// WARRANTY DISCLAIMER
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Intel Corporation is the author of this code, and requests that all
// problem reports or change requests be submitted to it directly at
// http://developer.intel.com/opensource.
//
#include <machine/asm.h>
ENTRY(__divsf3, 0)
{ .mfi
// a is in f8
// b is in f9
// general registers used: r31, r32, r33, r34
// predicate registers used: p6
// floating-point registers used: f6, f7, f8
nop.m 0
// load a, the first argument, in f6
mov f6=f8
nop.i 0;;
} { .mfi
nop.m 0
// load b, the second argument, in f7
mov f7=f9
nop.i 0;;
} { .mfi
// BEGIN SINGLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM
nop.m 0
// Step (1)
// y0 = 1 / b in f8
frcpa.s0 f8,p6=f6,f7
nop.i 0;;
} { .mfi
nop.m 0
// Step (2)
// q0 = a * y0 in f6
(p6) fma.s1 f6=f6,f8,f0
nop.i 0
} { .mfi
nop.m 0
// Step (3)
// e0 = 1 - b * y0 in f7
(p6) fnma.s1 f7=f7,f8,f1
nop.i 0;;
} { .mfi
nop.m 0
// Step (4)
// q1 = q0 + e0 * q0 in f6
(p6) fma.s1 f6=f7,f6,f6
nop.i 0
} { .mfi
nop.m 0
// Step (5)
// e1 = e0 * e0 in f7
(p6) fma.s1 f7=f7,f7,f0
nop.i 0;;
} { .mfi
nop.m 0
// Step (6)
// q2 = q1 + e1 * q1 in f6
(p6) fma.s1 f6=f7,f6,f6
nop.i 0
} { .mfi
nop.m 0
// Step (7)
// e2 = e1 * e1 in f7
(p6) fma.s1 f7=f7,f7,f0
nop.i 0;;
} { .mfi
nop.m 0
// Step (8)
// q3 = q2 + e2 * q2 in f6
(p6) fma.d.s1 f6=f7,f6,f6
nop.i 0;;
} { .mfi
nop.m 0
// Step (9)
// q3' = q3 in f8
(p6) fma.s.s0 f8=f6,f1,f0
nop.i 0;;
// END SINGLE PRECISION LATENCY-OPTIMIZED DIVIDE ALGORITHM
} { .mmb
nop.m 0
nop.m 0
// return
br.ret.sptk b0;;
}
END(__divsf3)

34
lib/libc/ia64/gen/infinity.c Normal file
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/* $NetBSD: infinity.c,v 1.1 1995/02/10 17:50:23 cgd Exp $ */
/* $FreeBSD$ */
/*
* Copyright (c) 1994, 1995 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
#include <math.h>
/* bytes for +Infinity on an ia64 (IEEE double format) */
char __infinity[] = { 0, 0, 0, 0, 0, 0, 0xf0, 0x7f };