Pull in r356809 from upstream llvm trunk (by Eli Friedman):
[ARM] Don't form "ands" when it isn't scheduled correctly. In r322972/r323136, the iteration here was changed to catch cases at the beginning of a basic block... but we accidentally deleted an important safety check. Restore that check to the way it was. Fixes https://bugs.llvm.org/show_bug.cgi?id=41116 Differential Revision: https://reviews.llvm.org/D59680 This should fix "Assertion failed: (LiveCPSR && "CPSR liveness tracking is wrong!"), function UpdateCPSRUse" errors when building the devel/xwpe port for armv7. PR: 236062, 236568 MFC after: 1 month X-MFC-With: r344779
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=345449
@ -2824,7 +2824,15 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
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// change. We can't do this transformation.
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return false;
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} while (I != B);
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if (I == B) {
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// In some cases, we scan the use-list of an instruction for an AND;
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// that AND is in the same BB, but may not be scheduled before the
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// corresponding TST. In that case, bail out.
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//
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// FIXME: We could try to reschedule the AND.
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return false;
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}
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} while (true);
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// Return false if no candidates exist.
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if (!MI && !SubAdd)
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