x86: add bits definitions for SRBDS mitigation control.
See https://software.intel.com/security-software-guidance/insights/deep-dive-special-register-buffer-data-sampling Reviewed by: markj Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D25221
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=362129
@ -477,6 +477,7 @@
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#define CPUID_STDEXT3_AVX5124FMAPS 0x00000008
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#define CPUID_STDEXT3_AVX5124FMAPS 0x00000008
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#define CPUID_STDEXT3_FSRM 0x00000010
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#define CPUID_STDEXT3_FSRM 0x00000010
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#define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100
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#define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100
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#define CPUID_STDEXT3_MCUOPT 0x00000200
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#define CPUID_STDEXT3_MD_CLEAR 0x00000400
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#define CPUID_STDEXT3_MD_CLEAR 0x00000400
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#define CPUID_STDEXT3_TSXFA 0x00002000
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#define CPUID_STDEXT3_TSXFA 0x00002000
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#define CPUID_STDEXT3_PCONFIG 0x00040000
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#define CPUID_STDEXT3_PCONFIG 0x00040000
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@ -555,6 +556,7 @@
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#define MSR_BBL_CR_BUSY 0x11b
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#define MSR_BBL_CR_BUSY 0x11b
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#define MSR_BBL_CR_CTL3 0x11e
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#define MSR_BBL_CR_CTL3 0x11e
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#define MSR_IA32_TSX_CTRL 0x122
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#define MSR_IA32_TSX_CTRL 0x122
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#define MSR_IA32_MCU_OPT_CTRL 0x123
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#define MSR_SYSENTER_CS_MSR 0x174
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#define MSR_SYSENTER_CS_MSR 0x174
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#define MSR_SYSENTER_ESP_MSR 0x175
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#define MSR_SYSENTER_ESP_MSR 0x175
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#define MSR_SYSENTER_EIP_MSR 0x176
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#define MSR_SYSENTER_EIP_MSR 0x176
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@ -797,6 +799,9 @@
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/* MSR IA32_FLUSH_CMD */
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/* MSR IA32_FLUSH_CMD */
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#define IA32_FLUSH_CMD_L1D 0x00000001
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#define IA32_FLUSH_CMD_L1D 0x00000001
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/* MSR IA32_MCU_OPT_CTRL */
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#define IA32_RNGDS_MITG_DIS 0x00000001
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/* MSR IA32_HWP_CAPABILITIES */
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/* MSR IA32_HWP_CAPABILITIES */
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#define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff)
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#define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff)
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#define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff)
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#define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff)
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@ -1028,6 +1028,7 @@ printcpuinfo(void)
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"\004AVX512_4FMAPS"
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"\004AVX512_4FMAPS"
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"\005FSRM"
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"\005FSRM"
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"\011AVX512VP2INTERSECT"
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"\011AVX512VP2INTERSECT"
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"\012MCUOPT"
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"\013MD_CLEAR"
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"\013MD_CLEAR"
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"\016TSXFA"
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"\016TSXFA"
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"\023PCONFIG"
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"\023PCONFIG"
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