Move the mds, irbs, and ssb mitigation knobs into machdep.mitigations.
They're in both the old and new places in HEAD for the moment for discussion and transition. The old locations will be garbage collected in 4 weeks. MFCs to 12 an 11 will keep the old and new for transition purposes. Reviewed by: kib MFC after: 4 weeks Sponsored by: Intel Differential Revision: https://reviews.freebsd.org/D22590
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=355436
@ -1778,10 +1778,17 @@ hammer_time(u_int64_t modulep, u_int64_t physfree)
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vty_set_preferred(VTY_VT);
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TUNABLE_INT_FETCH("hw.ibrs_disable", &hw_ibrs_disable);
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TUNABLE_INT_FETCH("machdep.mitigations.ibrs.disable", &hw_ibrs_disable);
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TUNABLE_INT_FETCH("hw.spec_store_bypass_disable", &hw_ssb_disable);
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TUNABLE_INT_FETCH("machdep.mitigations.ssb.disable", &hw_ssb_disable);
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TUNABLE_INT_FETCH("machdep.syscall_ret_l1d_flush",
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&syscall_ret_l1d_flush_mode);
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TUNABLE_INT_FETCH("hw.mds_disable", &hw_mds_disable);
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TUNABLE_INT_FETCH("machdep.mitigations.mds.disable", &hw_mds_disable);
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TUNABLE_INT_FETCH("machdep.mitigations.taa.enable", &x86_taa_enable);
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finishidentcpu(); /* Final stage of CPU initialization */
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@ -877,6 +877,12 @@ int hw_ibrs_disable = 1;
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SYSCTL_INT(_hw, OID_AUTO, ibrs_active, CTLFLAG_RD, &hw_ibrs_active, 0,
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"Indirect Branch Restricted Speculation active");
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SYSCTL_NODE(_machdep_mitigations, OID_AUTO, ibrs, CTLFLAG_RW, 0,
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"Indirect Branch Restricted Speculation active");
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SYSCTL_INT(_machdep_mitigations_ibrs, OID_AUTO, active, CTLFLAG_RD,
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&hw_ibrs_active, 0, "Indirect Branch Restricted Speculation active");
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void
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hw_ibrs_recalculate(void)
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{
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@ -907,6 +913,11 @@ SYSCTL_PROC(_hw, OID_AUTO, ibrs_disable, CTLTYPE_INT | CTLFLAG_RWTUN |
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CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0, hw_ibrs_disable_handler, "I",
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"Disable Indirect Branch Restricted Speculation");
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SYSCTL_PROC(_machdep_mitigations_ibrs, OID_AUTO, disable, CTLTYPE_INT |
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CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
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hw_ibrs_disable_handler, "I",
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"Disable Indirect Branch Restricted Speculation");
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int hw_ssb_active;
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int hw_ssb_disable;
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@ -914,6 +925,12 @@ SYSCTL_INT(_hw, OID_AUTO, spec_store_bypass_disable_active, CTLFLAG_RD,
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&hw_ssb_active, 0,
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"Speculative Store Bypass Disable active");
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SYSCTL_NODE(_machdep_mitigations, OID_AUTO, ssb, CTLFLAG_RW, 0,
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"Speculative Store Bypass Disable active");
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SYSCTL_INT(_machdep_mitigations_ssb, OID_AUTO, active, CTLFLAG_RD,
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&hw_ssb_active, 0, "Speculative Store Bypass Disable active");
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static void
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hw_ssb_set(bool enable, bool for_all_cpus)
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{
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@ -967,6 +984,11 @@ SYSCTL_PROC(_hw, OID_AUTO, spec_store_bypass_disable, CTLTYPE_INT |
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hw_ssb_disable_handler, "I",
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"Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto");
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SYSCTL_PROC(_machdep_mitigations_ssb, OID_AUTO, disable, CTLTYPE_INT |
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CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
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hw_ssb_disable_handler, "I",
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"Speculative Store Bypass Disable (0 - off, 1 - on, 2 - auto");
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int hw_mds_disable;
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/*
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@ -1016,6 +1038,14 @@ SYSCTL_PROC(_hw, OID_AUTO, mds_disable_state,
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sysctl_hw_mds_disable_state_handler, "A",
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"Microarchitectural Data Sampling Mitigation state");
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SYSCTL_NODE(_machdep_mitigations, OID_AUTO, mds, CTLFLAG_RW, 0,
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"Microarchitectural Data Sampling Mitigation state");
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SYSCTL_PROC(_machdep_mitigations_mds, OID_AUTO, state,
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CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
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sysctl_hw_mds_disable_state_handler, "A",
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"Microarchitectural Data Sampling Mitigation state");
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_Static_assert(__offsetof(struct pcpu, pc_mds_tmp) % 64 == 0, "MDS AVX512");
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void
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@ -1172,6 +1202,11 @@ SYSCTL_PROC(_hw, OID_AUTO, mds_disable, CTLTYPE_INT |
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"Microarchitectural Data Sampling Mitigation "
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"(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO");
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SYSCTL_PROC(_machdep_mitigations_mds, OID_AUTO, disable, CTLTYPE_INT |
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CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_MPSAFE, NULL, 0,
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sysctl_mds_disable_handler, "I",
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"Microarchitectural Data Sampling Mitigation "
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"(0 - off, 1 - on VERW, 2 - on SW, 3 - on AUTO");
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/*
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* Intel Transactional Memory Asynchronous Abort Mitigation
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