Merge commit c6b09bff5 from llvm git (by Luís Marques):
[RISCV] Fix wrong CFI directives Summary: Removes CFI CFA directives that could incorrectly propagate beyond the basic block they were inteded for. Specifically it removes the epilogue CFI directives. See the branch_and_tail_call test for an example of the issue. Should fix the stack unwinding issues caused by the incorrect directives. Reviewers: asb, lenary, shiva0217 Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D69723 This is a prerequisite for building and linking hard- and soft-float riscv worlds with clang and lld. Requested by: jhb MFC after: 1 week X-MFC-With: r353358
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=356331
@ -205,7 +205,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineFrameInfo &MFI = MF.getFrameInfo();
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auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
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DebugLoc DL = MBBI->getDebugLoc();
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const RISCVInstrInfo *TII = STI.getInstrInfo();
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unsigned FPReg = getFPReg(STI);
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unsigned SPReg = getSPReg(STI);
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@ -226,47 +225,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineInstr::FrameDestroy);
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}
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if (hasFP(MF)) {
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// To find the instruction restoring FP from stack.
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for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
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if (I->mayLoad() && I->getOperand(0).isReg()) {
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unsigned DestReg = I->getOperand(0).getReg();
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if (DestReg == FPReg) {
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// If there is frame pointer, after restoring $fp registers, we
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// need adjust CFA to ($sp - FPOffset).
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// Emit ".cfi_def_cfa $sp, -FPOffset"
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unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
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nullptr, RI->getDwarfRegNum(SPReg, true), -FPOffset));
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BuildMI(MBB, std::next(I), DL,
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TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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break;
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}
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}
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}
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}
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// Add CFI directives for callee-saved registers.
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const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
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// Iterate over list of callee-saved registers and emit .cfi_restore
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// directives.
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for (const auto &Entry : CSI) {
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unsigned Reg = Entry.getReg();
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unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
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nullptr, RI->getDwarfRegNum(Reg, true)));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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// Deallocate stack
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adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
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// After restoring $sp, we need to adjust CFA to $(sp + 0)
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// Emit ".cfi_def_cfa_offset 0"
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unsigned CFIIndex =
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MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,
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