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Add the if_dc driver and remove all of the al, ax, dm, pn and mx drivers

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which it replaces. The new driver supports all of the chips supported
by the ones it replaces, as well as many DEC/Intel 21143 10/100 cards.

This also completes my quest to convert things to miibus and add
Alpha support.
This commit is contained in:
Bill Paul 1999-12-04 17:41:31 +00:00
parent e92feeebb1
commit 96f2e892a7
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=54134
50 changed files with 8845 additions and 13949 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
release/sysinstall/devices.c
View File

@ -91,14 +91,12 @@ static struct _devname {
{ DEVICE_TYPE_FLOPPY, "fd%d", "floppy drive unit A", 2, 0, 64, 4, 'b' },
{ DEVICE_TYPE_FLOPPY, "wfd%d", "ATAPI floppy drive unit A", 1, 0, 8, 4, 'b' },
{ DEVICE_TYPE_FLOPPY, "worm%d", "SCSI optical disk / CDR", 23, 0, 1, 4, 'b' },
{ DEVICE_TYPE_NETWORK, "al", "ADMtek AL981/AN985 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "ax", "ASIX AX88140A PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "fpa", "DEC DEFPA PCI FDDI card" },
{ DEVICE_TYPE_NETWORK, "sr", "SDL T1/E1 sync serial PCI card" },
{ DEVICE_TYPE_NETWORK, "cc3i", "SDL HSSI sync serial PCI card" },
{ DEVICE_TYPE_NETWORK, "en", "Efficient Networks ATM PCI card" },
{ DEVICE_TYPE_NETWORK, "dc", "DEC/Intel 21143 (and clones) PCI fast ethernet card" },
{ DEVICE_TYPE_NETWORK, "de", "DEC DE435 PCI NIC or other DC21040-AA based card" },
{ DEVICE_TYPE_NETWORK, "dm", "Davicom DM9100/DM9102 PCI fast ethernet card" },
{ DEVICE_TYPE_NETWORK, "fxp", "Intel EtherExpress Pro/100B PCI Fast Ethernet card" },
{ DEVICE_TYPE_NETWORK, "ed", "Novell NE1000/2000; 3C503; NE2000-compatible PCMCIA" },
{ DEVICE_TYPE_NETWORK, "ep", "3Com 3C509 ethernet card/3C589 PCMCIA" },
@ -109,8 +107,6 @@ static struct _devname {
{ DEVICE_TYPE_NETWORK, "ix", "Intel Etherexpress ethernet card" },
{ DEVICE_TYPE_NETWORK, "le", "DEC EtherWorks 2 or 3 ethernet card" },
{ DEVICE_TYPE_NETWORK, "lnc", "Lance/PCnet (Isolan/Novell NE2100/NE32-VL) ethernet" },
{ DEVICE_TYPE_NETWORK, "mx", "Macronix 98713/98715/98725 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "pn", "Lite-On 82168/82169 PNIC PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "rl", "RealTek 8129/8139 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "sf", "Adaptec AIC-6915 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "sis", "SiS 900/SiS 7016 PCI ethernet card" },

6
release/texts/alpha/HARDWARE.TXT
View File

@ -85,11 +85,9 @@ sio1 2f8 3 n/a n/a Serial Port 1 (COM2)
lpt0 dyn 7 n/a n/a Printer Port 0
lpt1 dyn dyn n/a n/a Printer Port 1
al0 dyn dyn n/a dyn ADMtek AL981/AN985 PCI based cards
ax0 dyn dyn n/a dyn ASIX AX88140A PCI based cards
dc0 n/a n/a n/a n/a DEC/Intel 21143 and workalikes
de0 n/a n/a n/a n/a DEC DC21x40 PCI based cards
(including 21140 100bT cards)
dm0 n/a n/a n/a n/a Davicom DM9100/DM9102 PCI based cards
ed0 280 10 dyn d8000 WD & SMC 80xx; Novell NE1000 &
NE2000; 3Com 3C503; HP PC Lan+
eg0 310 5 dyn dyn 3Com 3C505
@ -106,8 +104,6 @@ le0 300 5 dyn d0000 Digital Equipment EtherWorks
lnc0 280 10 n/a dyn Lance/PCnet cards
(Isolan, Novell NE2100, NE32-VL,
some PCnet-PCI cards)
mx0 dyn dyn n/a dyn Macronix 98713/15/25 PCI based cards
pn0 dyn dyn n/a dyn Lite-On PNIC PCI based cards
rl0 dyn dyn n/a dyn RealTek 8129/8139 fast ethernet
sf0 dyn dyn n/a dyn Adaptec AIC-6915 fast ethernet
sis0 dyn dyn n/a dyn SiS 900/SiS 7016 fast ethernet

4
release/texts/alpha/RELNOTES.TXT
View File

@ -120,6 +120,10 @@ Any usage of "/dev/sd*" in ``/etc/fstab'' must be replace by "/dev/da*".
In addition, any useage of "/dev/*sd*" in scripts need to be changed.
Even if you have old `sd' device entries in /dev, they will no longer work.
The `al' `ax' `dm' `pn' and `mx' drivers have been removed and replaced
with a single driver (`dc') in order to reduce code duplication. The
new driver handles all chipsets supported by the older driver, and it
offers improved support for 10/100 cards based on the DEC/Intel 21143.
1.2. SECURITY FIXES
-------------------

6
release/texts/i386/HARDWARE.TXT
View File

@ -87,11 +87,9 @@ sio1 2f8 3 n/a n/a Serial Port 1 (COM2)
ppc0 dyn 7 n/a n/a Printer ports
al0 dyn dyn n/a dyn ADMtek AL981/AN985 PCI based cards
ax0 dyn dyn n/a dyn ASIX AX88140A PCI based cards
dc0 n/a n/a n/a n/a DEC/Intel 21143 cards and workalikes
de0 n/a n/a n/a n/a DEC DC21x40 PCI based cards
(including 21140 100bT cards)
dm0 n/a n/a n/a n/a Davicom DM9100/DM9102 PCI based cards
ed0 280 10 dyn d8000 WD & SMC 80xx; Novell NE1000 &
NE2000; 3Com 3C503; HP PC Lan+
ep0 300 10 dyn dyn 3Com 3C509
@ -108,8 +106,6 @@ le0 300 5 dyn d0000 Digital Equipment EtherWorks
lnc0 280 10 n/a dyn Lance/PCnet cards
(Isolan, Novell NE2100, NE32-VL,
some PCnet-PCI cards)
mx0 dyn dyn n/a dyn Macronix 98713/15/25 PCI based cards
pn0 dyn dyn n/a dyn Lite-On PNIC PCI based cards
rl0 dyn dyn n/a dyn RealTek 8129/8139 fast ethernet
sf0 dyn dyn n/a dyn Adaptec AIC-6915 fast ethernet
sis0 dyn dyn n/a dyn SiS 900/SiS 7016 fast ethernet

4
release/texts/i386/RELNOTES.TXT
View File

@ -122,6 +122,10 @@ Any usage of "/dev/sd*" in ``/etc/fstab'' must be replace by "/dev/da*".
In addition, any useage of "/dev/*sd*" in scripts need to be changed.
Even if you have old `sd' device entries in /dev, they will no longer work.
The `al' `ax' `dm' `pn' and `mx' drivers have been removed and replaced
with a single driver (`dc') in order to reduce code duplication. The
new driver handles all chipsets supported by the older drivers, and it
offers improved support for 10/100 cards based on the DEC/Intel 21143.
1.2. SECURITY FIXES
-------------------

10
share/man/man4/Makefile
View File

@ -1,14 +1,14 @@
# @(#)Makefile 8.1 (Berkeley) 6/18/93
# $FreeBSD$
MAN4= ahc.4 al.4 alpm.4 atkbd.4 atkbdc.4 ax.4 blackhole.4 bpf.4 \
bridge.4 ccd.4 cd.4 ch.4 da.4 ddb.4 de.4 \
divert.4 dm.4 drum.4 dummynet.4 fd.4 fdc.4 fpa.4 fxp.4 \
MAN4= ahc.4 alpm.4 atkbd.4 atkbdc.4 blackhole.4 bpf.4 \
bridge.4 ccd.4 cd.4 ch.4 da.4 dc.4 ddb.4 de.4 \
divert.4 drum.4 dummynet.4 fd.4 fdc.4 fpa.4 fxp.4 \
icmp.4 ifmib.4 iic.4 iicbb.4 iicbus.4 iicsmb.4 \
inet.4 intpm.4 intro.4 ip.4 ipfirewall.4 keyboard.4 kld.4 \
lo.4 lp.4 lpbb.4 lpt.4 mem.4 mouse.4 mtio.4 mx.4 natm.4 ncr.4 \
lo.4 lp.4 lpbb.4 lpt.4 mem.4 mouse.4 mtio.4 natm.4 ncr.4 \
netintro.4 null.4 pass.4 ppbus.4 ppi.4 ppp.4 pt.4 pty.4 \
route.4 ohci.4 pcm.4 pcvt.4 pn.4 psm.4 rl.4 sa.4 screen.4 scsi.4 \
route.4 ohci.4 pcm.4 pcvt.4 psm.4 rl.4 sa.4 screen.4 scsi.4 \
sd.4 sf.4 si.4 sio.4 sis.4 sk.4 sl.4 smb.4 smbus.4 smp.4 snp.4 \
splash.4 sppp.4 ssc.4 st.4 ste.4 su.4 syscons.4 sysmouse.4 tcp.4 \
termios.4 ti.4 tl.4 ttcp.4 tty.4 tun.4 udp.4 uhci.4 uk.4 ukbd.4 \

151
share/man/man4/al.4
View File

@ -1,151 +0,0 @@
.\" Copyright (c) 1997, 1998, 1999
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd May 20, 1999
.Dt AL 4
.Os FreeBSD
.Sh NAME
.Nm al
.Nd ADMtek Inc. AL981 Comet and AN985 Centaur fast ethernet device driver
.Sh SYNOPSIS
.Cd "device al0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the ADMtek Inc. AL981 Comet and AN 985
Centaur fast ethernet controller chips.
.Pp
The ADMtek chip uses bus master DMA and is designed to be a
DEC 21x4x workalike. The only major difference between the DEC
and ADMtek parts is that the ADMtek receiver filter is programmed
using two special registers where as the DEC chip is programmed
by uploading a special setup frame via the transmit DMA engine.
The AL981 and AN985 can only be programmed with a single
perfect filter entry for the local station address and a 64-bit
multicast hash table; the DEC filter supports several other
options. The ADMtek fast ethernet controllers support both
10 and 100Mbps speeds in either full or half duplex using
an internal MII transceiver.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
fine.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "ax%d: couldn't map memory"
A fatal initialization error has occurred.
.It "ax%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "ax%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "ax%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "ax%d: no memory for tx list"
The driver failed to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "ax%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Rs
.%T ADMtek AL981 data sheet
.%O http://www.admtek.com.tw
.Re
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHORS
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .

155
share/man/man4/ax.4
View File

@ -1,155 +0,0 @@
.\" Copyright (c) 1997, 1998, 1999
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd January 2, 1999
.Dt AX 4
.Os FreeBSD
.Sh NAME
.Nm ax
.Nd
ASIX Electronics AX88140A and AX88141 fast ethernet device driver
.Sh SYNOPSIS
.Cd "device ax0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the ASIX AX88140A and AX88141 fast ethernet
controller chips, including the Alfa Inc. GFC2204 and the CNet Pro110B.
The AX88141 is a new version of the AX88140A with power management
and magic packet support.
.Pp
The ASIX chip uses bus master DMA and is designed to be a
DEC 21x4x workalike. The only major difference between the DEC
and ASIX parts is that the ASIX receiver filter is programmed
using two special registers where as the DEC chip is programmed
by uploading a special setup frame via the transmit DMA engine.
The ASIX receive filter can only be programmed with a single
perfect filter entry for the local station address and a 64-bit
multicast hash table; the DEC filter supports several other
options. The ASIX fast ethernet controller supports both
10 and 100Mbps speeds in either full or half duplex using
an external MII transceiver.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
file.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "ax%d: couldn't map memory"
A fatal initialization error has occurred.
.It "ax%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "ax%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "ax%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "ax%d: no memory for tx list"
The driver failed to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "ax%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Rs
.%T ASIX AX81140A data sheet
.%O http://www.asix.com.tw
.Re
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHORS
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .

322
share/man/man4/dc.4 Normal file
View File

@ -0,0 +1,322 @@
.\" Copyright (c) 1997, 1998, 1999
.\" Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd November 20, 1999
.Dt DC 4 i386
.Os FreeBSD
.Sh NAME
.Nm dc
.Nd
DEC/Intel 21143 and clone 10/100 ethernet driver
.Sh SYNOPSIS
.Cd "controller miibus0"
.Cd "device dc0"
.Sh DESCRIPTION
The
.Nm
driver provides support for several PCI fast ethernet adapters and
embedded controllers based on the following chipsets:
.Pp
.Bl -bullet -compact -offset indent
.It
DEC/Intel 21143
.It
Macronix 98713, 98713A, 98715, 98715A and 98725
.It
Davicom DM9100 and DM9102
.It
ASIX Electronics AX88140A and AX88141
.It
ADMtek AL981 Comet and AN985 Centaur
.It
Lite-On 82c168 and 82c169 PNIC
.It
Lite-On/Macronix 82c115 PNIC II
.El
.Pp
All of these chips have the same general register layout, DMA
descriptor format and method of operation. All of the clone chips
are based on the 21143 design with various modifications. The
21143 itself has support for 10baseT, BNC, AUI, MII and symbol
media attachments, 10 and 100Mbps speeds in full or half duplex,
built in NWAY autonegotiation and wake on LAN. The 21143 also
offers several receive filter programming options including
perfect filtering, inverse perfect filtering and hash table
filtering.
.Pp
Some clone chips duplicate the 21143 fairly closely while others
only maintain superficial simularities. Some support only MII
media attachments. Others use different receiver filter programming
mechanisms. At least one supports only chained DMA descriptors
(most support both chained descriptors and contiguously allocated
fixed size rings). Some chips (especially the PNIC) also have
peculiar bugs. The
.Nm
driver does its best to provide generalized support for all
of these chipsets in order to keep special case code to a minimun.
.Pp
These chips are used by many vendors which makes it
difficult provide a complete list of all supported cards. The
following NICs are known to work with the
.Nm
driver at this time:
.Pp
.Bl -bullet -compact -offset indent
.It
Digital DE500-BA 10/100 (21143, non-MII)
.It
Built in DE500-BA on DEC Alpha workstations (21143, non-MII)
.It
Kingston KNE100TX (21143, MII)
.It
D-Link DFE-570TX (21143, MII, quad port)
.It
NDC SOHOware SFA110 (98513A)
.It
SVEC PN102-TX (98713)
.It
CNet Pro120A (98715A or 9713A) and CNet Pro120B (98715)
.It
Compex RL100-TX (98713 or 98713A)
.It
LinkSys LNE100TX (PNIC 82c168, 82c169)
.It
NetGear FA310-TX Rev. D1, D2 or D3 (PNIC 82c169)
.It
Matrox FastNIC 10/100 (PNIC 82c168, 82c169)
.It
Kingston KNE110TX (PNIC 82c169)
.It
LinkSys LNE100TX v2.0 (PNIC II 82c115)
.It
Jaton XpressNet (Davicom DM9102)
.It
Alfa Inc GFC2204 (ASIX AX88140A)
.It
CNet Pro110B (ASIX AX88140A)
.El
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
file.
.Pp
Note: the built-in NWAY autonegotiation on the original PNIC 82c168
chip is horribly broken and is not supported by the
.Nm
driver at this time: the chip will operate in any speed or duplex
mode, however these must be set manually. The original 82c168 appears
on very early revisions of the LinkSys LNE100TX and Matrox FastNIC.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to enable
.Ar full-duplex
operation. Not specifying
.Ar full duplex
implies
.Ar half-duplex
mode.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to enable
.Ar full-duplex
operation. Not specifying
.Ar full duplex
implies
.Ar half-duplex
mode.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation. The interface will operate in
half duplex mode if this media option is not specified.
.El
.Pp
Note that the 100baseTX media type may not be available on certain
Intel 21143 adapters which support 10mbps media attachments only.
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "dc%d: couldn't map ports/memory"
A fatal initialization error has occurred.
.It "dc%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "dc%d: watchdog timeout"
A packet was queued for transmission and a transmit command was
issued, however the device failed to acknowledge the transmission
before a timeout expired. This can happen if the device is unable
to deliver interrupts for some reason, of if there is a problem with
the network connection (cable).
.It "dc%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "dc%d: TX underrun -- increasing TX threshold"
The device generated a transmit underrun error while attempting to
DMA and transmit a packet. This happens if the host is not able to
DMA the packet data into the NIC's FIFO fast enough. The driver
will dynamically increase the transmit start threshold so that
more data must be DMAed into the FIFO before the NIC will start
transmitting it onto the wire.
.It "dc%d: TX underrun -- using store and forward mode"
The device continued to generate transmit underruns even after all
possible transmit start threshold settings had been tried, so the
driver programmed the chip for store and forward mode. In this mode,
the NIC will not begin transmission until the entire packet has been
transfered into its FIFO memory.
.It "dc%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Rs
.%T ADMtek AL981, AL983 and AL985 data sheets
.%O http://www.admtek.com.tw
.Re
.Rs
.%T ASIX Electronics AX88140A and AX88141 data sheets
.%O http://www.asix.com.tw
.Re
.Rs
.%T Davicom DM9102 data sheet
.%O http://www.davicom8.com
.Re
.Rs
.%T Intel 21143 Hardware Reference Manual
.%O http://developer.intel.com
.Re
.Rs
.%T Macronix 98713/A, 98715/A and 98725 data sheets
.%O http://www.macronix.com
.Re
.Rs
.%T Macronix 98713/A and 98715/A app notes
.%O http://www.macronix.com
.Re
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 4.0 .
.Sh AUTHORS
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ee.columbia.edu .
.Sh BUGS
The Macronix application notes claim that in order to put the
chips in normal operation, the driver must write a certian magic
number into the CSR16 register. The numbers are documented in
the app notes, but the exact meaning of the bits is not.
.Pp
The 98713A seems to have a problem with 10Mbps full duplex mode.
The transmitter works but the receiver tends to produce many
unexplained errors leading to very poor overall performance. The
98715A does not exhibit this problem. All other modes on the
98713A seem to work correctly.
.Pp
The original 82c168 PNIC chip has built in NWAY support which is
used on certain early LinkSys LNE100TX and Matrox FastNIC cards,
however it is horribly broken and difficult to use reliably.
Consequently, autonegotiation is not currently supported for this
chipset: the driver defaults the NIC to 10baseT half duplex, and it's
up to the operator to manually select a different mode if necessary.
(Later cards use an external MII transceiver to implement NWAY
autonegotiation and work correctly.)
.Pp
The
.Nm
driver programs 82c168 and 82c169 PNIC chips to use the store and
forward setting for the transmit start threshold by default. This
is to work around problems with some NIC/PCI bus combinations where
the PNIC can transmit corrupt frames when operating at 100Mbps,
probably due to PCI DMA burst transfer errors.
.Pp
The 82c168 abd 82c169 PNIC chips also have a receiver bug that
sometimes manifests during periods of heavy receive and transmit
activity, where the chip will improperly DMA received frames to
the host. The chips appear to upload several kilobytes of garbage
data along with the received frame data, dirtying several RX buffers
instead of just the expected one. The
.Nm
driver detects this condition and will salvage the frame, however
it incurs a serious performance penalty in the process.
.Pp
The PNIC chips also sometimes generate a transmit underrun error when
the driver attempts to download the receiver filter setup frame, which
can result in the receive filter being incorrectly programmed. The
.Nm
driver will watch for this condition and requeue the setup frame until
it is transfered successfully.
.Pp
The ADMtek AL981 chip (and possibly the AN985 as well) has been observed
to sometimes wedge on transmit: this appears to happen when the driver
queues a sequence of frames which cause it to wrap from the end of the
the transmit descriptor ring back to the beginning. The
.Nm
driver attempts to avoid this condition by not queing any frames past
the end of the transmit ring during a single invocation of the
.Fn dc_start
routine. This workaround has a negligible impact on transmit performance.

150
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View File

@ -1,150 +0,0 @@
.\" Copyright (c) 1997, 1998, 1999
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd September 4, 1999
.Dt DM 4 i386
.Os FreeBSD
.Sh NAME
.Nm dm
.Nd
Davicom DM9100/DM9102 fast ethernet device driver
.Sh SYNOPSIS
.Cd "controller miibus0"
.Cd "device dm0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the Davicom DM9100 and DM9102 PCI
fast ethernet controller chips including the Jaton Corporation
XPressNet.
.Pp
The DM9100 and DM9102 are designed to be DEC 21x4x workalikes. The
register layout, DMA descriptor scheme and receive filter programming
are identical to the DEC part. The DM9102
is a 100Mbps ethernet MAC and MII-compliant transceiver
in a single package. The DM9100 is similar to the DM9102 except
that it has no internal PHY, requiring instead an external transceiver
to be attached to its MII interface.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
fine.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "dm%d: couldn't map ports/memory"
A fatal initialization error has occurred.
.It "dm%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "dm%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "dm%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "dm%d: no memory for tx list"
The driver failed to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cludmr.
.It "dm%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating sydmms place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating sydmm. If you power down your sydmm prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Rs
.%T Davicom DM9102 datasheet
.%O http://www.davicom8.com
.Re
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHORS
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ee.columbia.edu .

173
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@ -1,173 +0,0 @@
.\" Copyright (c) 1997, 1998
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd November 5, 1998
.Dt MX 4
.Os FreeBSD
.Sh NAME
.Nm mx
.Nd
Macronix 98713/98715/98725 fast ethernet device driver
.Sh SYNOPSIS
.Cd "controller miibus0"
.Cd "device mx0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the Macronix 98713, 98713A, 98715, 98715A and
98725 fast ethernet controller chips. This includes the NDC
Communications SOHOware SFA110, the SVEC PN102-TX
fast ethernet card, and various other adapters. The
.Nm
driver also supports the Lite-On 82c115 PNIC II chip, which is
actually similar in design to the Macronix 98715A with the addition
of wake on LAN support. Supported PNIC II cards include the
LinkSys LNE100TX Version 2.
.Pp
The Macronix chips use bus master DMA and are designed to be
DEC 'tulip' workalikes. The original 98713 had an MII bus for
controlling an external PHY, however the 98713A and up use an
internal transceiver with NWAY support. The Macronix parts are
advertised as being register compatible with the DEC 21x4x
controllers. All of the Macronix controllers support both
10 and 100Mbps speeds in either full or half duplex.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
file.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
Note that the 100baseTX media type is only available if supported
by the adapter.
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "mx%d: couldn't map memory"
A fatal initialization error has occurred.
.It "mx%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "mx%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "mx%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "mx%d: no memory for tx list"
The driver failed to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "mx%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Rs
.%T Macronix 98713/A, 98715/A and 98725 data sheets
.%O http://www.macronix.com
.Re
.Rs
.%T Macronix 98713/A and 98715/A app notes
.%O http://www.macronix.com
.Re
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHORS
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .
.Sh BUGS
The Macronix application notes claim that in order to put the
chips in normal operation, the driver must write a certian magic
number into the CSR16 register. The numbers are documented in
the app notes, but the exact meaning of the bits is not.
.Pp
The 98713A seems to have a problem with 10Mbps full duplex mode.
The transmitter works but the receiver tends to produce many
unexplained errors leading to very poor overall performance. The
98715A does not exhibit this problem. All other modes on the
98713A seem to work correctly.

160
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View File

@ -1,160 +0,0 @@
.\" Copyright (c) 1997, 1998
.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Bill Paul.
.\" 4. Neither the name of the author nor the names of any co-contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
.\" THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd November 7, 1998
.Dt PN 4
.Os FreeBSD
.Sh NAME
.Nm pn
.Nd
Lite-On 82c168/82c169 PNIC fast ethernet device driver
.Sh SYNOPSIS
.Cd "device pn0"
.Sh DESCRIPTION
The
.Nm
driver provides support for PCI ethernet adapters and embedded
controllers based on the Lite-On 82c168 and 82c169 fast ethernet
controller chips. This includes the LinkSys LNE100TX, the
Bay Networks Netgear FA310TX revision D1, the Matrox Networks
FastNIC 10/100, the Kingston KNE110TX (EtherRx VP),
and various other commodity fast ethernet cards.
.Pp
The Lite-On chips use bus master DMA and are designed to be
DEC 'tulip' workalikes. Many vendors that formerly based their
designs around the DEC 21x4x devices are now using the PNIC
instead. The chips support both an internal transceiver
and external transceivers via an MII bus. The Lite-On parts are
advertised as being register compatible with the DEC 21x4x
controllers, however there are some differences in the way the
EEPROM and MII access is done. The PNIC controllers support both
10 and 100Mbps speeds in either full or half duplex.
.Pp
The
.Nm
driver supports the following media types:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options.
The user can manually override
the autoselected mode by adding media options to the
.Pa /etc/rc.conf
fine.
.It 10baseT/UTP
Set 10Mbps operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex modes.
.It 100baseTX
Set 100Mbps (fast ethernet) operation. The
.Ar mediaopt
option can also be used to select either
.Ar full-duplex
or
.Ar half-duplex
modes.
.El
.Pp
The
.Nm
driver supports the following media options:
.Pp
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Force full duplex operation
.It half-duplex
Force half duplex operation.
.El
.Pp
Note that the 100baseTX media type is only available if supported
by the adapter.
For more information on configuring this device, see
.Xr ifconfig 8 .
.Sh DIAGNOSTICS
.Bl -diag
.It "pn%d: couldn't map memory"
A fatal initialization error has occurred.
.It "pn%d: couldn't map interrupt"
A fatal initialization error has occurred.
.It "pn%d: watchdog timeout"
The device has stopped responding to the network, or there is a problem with
the network connection (cable).
.It "pn%d: no memory for rx list"
The driver failed to allocate an mbuf for the receiver ring.
.It "pn%d: no memory for tx list"
The driver failed to allocate an mbuf for the transmitter ring when
allocating a pad buffer or collapsing an mbuf chain into a cluster.
.It "pn%d: chip is in D3 power state -- setting to D0"
This message applies only to adapters which support power
management. Some operating systems place the controller in low power
mode when shutting down, and some PCI BIOSes fail to bring the chip
out of this state before configuring it. The controller loses all of
its PCI configuration in the D3 state, so if the BIOS does not set
it back to full power mode in time, it won't be able to configure it
correctly. The driver tries to detect this condition and bring
the adapter back to the D0 (full power) state, but this may not be
enough to return the driver to a fully operational condition. If
you see this message at boot time and the driver fails to attach
the device as a network interface, you will have to perform second
warm boot to have the device properly configured.
.Pp
Note that this condition only occurs when warm booting from another
operating system. If you power down your system prior to booting
.Fx ,
the card should be configured correctly.
.El
.Sh SEE ALSO
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ifconfig 8
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 3.0 .
.Sh AUTHORS
The
.Nm
driver was written by
.An Bill Paul Aq wpaul@ctr.columbia.edu .
.Sh BUGS
The internal NWAY support on the 82c168 chip is horribly broken, which
means that autoselection will not work, except maybe for half-duplex
10Mbps links. In order to use other modes (e.g. 100Mbps) it will be
necessary to
use
.Xr ifconfig 8
to set the interface manually. Autoselection for 82c169 boards using
MII transceivers should work correctly.

6
sys/alpha/conf/GENERIC
View File

@ -114,17 +114,13 @@ device sio0 at isa0 port IO_COM1 irq 4
device sio1 at isa0 port IO_COM2 irq 3 flags 0x50
# PCI Ethernet NICs.
device ax0 # ASIX AX88140A
device de0 # DEC/Intel DC21x4x (``Tulip'')
device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
device le0 # Lance
device pn0 # Lite-On 82c168/82c169 (``PNIC'')
# PCI Ethernet NICs that use the common MII bus controller code.
controller miibus0 # MII bus support
device al0 # ADMtek AL981/AN985 (``Comet''/``Centaur'')
device dm0 # Davicom DM9100/DM9102
device mx0 # Macronix 98713/98715/98725 (``PMAC'')
device dc0 # DEC/Intel 21143 and workalikes
device rl0 # RealTek 8129/8139
device sf0 # Adaptec AIC-6915 (``Starfire'')
device sis0 # Silicon Integrated Systems SiS 900/SiS 7016

6
sys/alpha/conf/NOTES
View File

@ -114,17 +114,13 @@ device sio0 at isa0 port IO_COM1 irq 4
device sio1 at isa0 port IO_COM2 irq 3 flags 0x50
# PCI Ethernet NICs.
device ax0 # ASIX AX88140A
device de0 # DEC/Intel DC21x4x (``Tulip'')
device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
device le0 # Lance
device pn0 # Lite-On 82c168/82c169 (``PNIC'')
# PCI Ethernet NICs that use the common MII bus controller code.
controller miibus0 # MII bus support
device al0 # ADMtek AL981/AN985 (``Comet''/``Centaur'')
device dm0 # Davicom DM9100/DM9102
device mx0 # Macronix 98713/98715/98725 (``PMAC'')
device dc0 # DEC/Intel 21143 and workalikes
device rl0 # RealTek 8129/8139
device sf0 # Adaptec AIC-6915 (``Starfire'')
device sis0 # Silicon Integrated Systems SiS 900/SiS 7016

6
sys/amd64/conf/GENERIC
View File

@ -175,18 +175,14 @@ device ppi0 # Parallel port interface device
# PCI Ethernet NICs.
device ax0 # ASIX AX88140A
device de0 # DEC/Intel DC21x4x (``Tulip'')
device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
device pn0 # Lite-On 82c168/82c169 (``PNIC'')
device tx0 # SMC 9432TX (83c170 ``EPIC'')
device vx0 # 3Com 3c590, 3c595 (``Vortex'')
# PCI Ethernet NICs that use the common MII bus controller code.
controller miibus0 # MII bus support
device al0 # ADMtek AL981/AN985 (``Comet''/``Centaur'')
device dm0 # Davicom DM9100/DM9102
device mx0 # Macronix 98713/98715/98725 (``PMAC'')
device dc0 # DEC/Intel 21143 and various workalikes
device rl0 # RealTek 8129/8139
device sf0 # Adaptec AIC-6915 (``Starfire'')
device sis0 # Silicon Integrated Systems SiS 900/SiS 7016

31
sys/conf/NOTES
View File

@ -1646,31 +1646,20 @@ controller miibus0
# nd 1040B PCI SCSI host adapters, as well as the Qlogic ISP 2100
# FC/AL Host Adapter.
#
# The `al' device provides support for PCI fast ethernet adapters
# based on the ADMtek Inc. AL981 "Comet" and the AN985 "Centaur" chips.
#
# The `ax' device provides support for PCI fast ethernet adapters
# based on the ASIX Electronics AX88140A chip, including the Alfa
# Inc. GFC2204.
# The `dc' device provides support for PCI fast ethernet adapters
# based on the DEC/Intel 21143 and various workalikes including:
# the ADMtek AL981 Comet and AN985 Centaur, the ASIX Electronics
# AX88140A and AX88141, the Davicom DM9100 and DM9102, the Lite-On
# 82c168 and 82c169 PNIC, the Lite-On/Macronix LC82C115 PNIC II
# and the Macronix 98713/98713A/98715/98715A/98725 PMAC. This driver
# replaces the old al, ax, dm, pn and mx drivers.
#
# The `de' device provides support for the Digital Equipment DC21040
# self-contained Ethernet adapter.
#
# The `dm' device provides support for PCI fast ethernet adapters
# based on the the Davicom DM9100 and DM9102 controller chips, including
# the Jaton Corporation XPressNet.
#
# The `fxp' device provides support for the Intel EtherExpress Pro/100B
# PCI Fast Ethernet adapters.
#
# The `mx' device provides support for various fast ethernet adapters
# based on the Macronix 98713, 987615 and 98725 series chips.
#
# The `pn' device provides support for various fast ethernet adapters
# based on the Lite-On 82c168 and 82c169 PNIC chips, including the
# LinkSys LNE100TX, the NetGear FA310TX rev. D1 and the Matrox
# FastNIC 10/100.
#
# The 'rl' device provides support for PCI fast ethernet adapters based
# on the RealTek 8129/8139 chipset. Note that the RealTek driver defaults
# to using programmed I/O to do register accesses because memory mapped
@ -1852,13 +1841,9 @@ options SCSI_ISP_WWN="0x5000000099990000"
#options ISP_COMPILE_2100_FW=1
#options ISP_COMPILE_2200_FW=1
device al0
device ax0
device dc0
device de0
device dm0
device fxp0
device mx0
device pn0
device rl0
device sf0
device sis0

6
sys/conf/files
View File

@ -715,18 +715,14 @@ dev/bktr/bktr_os.c optional bktr pci
pci/pccbb.c optional pccbb cardbus
pci/cy_pci.c optional cy pci
pci/ida_pci.c optional ida pci
pci/if_al.c optional al
pci/if_ar_p.c optional ar pci
pci/if_ax.c optional ax
pci/if_dc.c optional dc
pci/if_de.c optional de
pci/if_dm.c optional dm
pci/if_en_pci.c optional en pci
pci/if_fpa.c optional fpa pci
pci/if_fxp.c optional fxp
pci/if_lnc_p.c optional lnc pci
pci/if_mn.c optional mn
pci/if_mx.c optional mx
pci/if_pn.c optional pn
pci/if_rl.c optional rl
pci/if_sf.c optional sf
pci/if_sis.c optional sis

236
sys/dev/mii/mxphy.c → sys/dev/dc/dcphy.c
View File

@ -33,13 +33,12 @@
*/
/*
* Pseudo-driver for internal NWAY support on Macronix 98713/98715/98725
* PMAC controller chips. The Macronix chips use the same internal
* NWAY register layout as the DEC/Intel 21143. Technically we're
* abusing the miibus code to handle the media selection and NWAY
* support here since there is no MII interface. However the logical
* operations are roughly the same, and the alternative is to create
* a fake MII interface in the driver, which is harder to do.
* Pseudo-driver for internal NWAY support on DEC 21143 and workalike
* controllers. Technically we're abusing the miibus code to handle
* media selection and NWAY support here since there is no MII
* interface. However the logical operations are roughly the same,
* and the alternative is to create a fake MII interface in the driver,
* which is harder to do.
*/
#include <sys/param.h>
@ -66,7 +65,9 @@
#include <machine/resource.h>
#include <sys/bus.h>
#include <pci/if_mxreg.h>
#include <pci/pcivar.h>
#include <pci/if_dcreg.h>
#include "miibus_if.h"
@ -75,45 +76,45 @@ static const char rcsid[] =
"$FreeBSD$";
#endif
#define MX_SETBIT(sc, reg, x) \
#define DC_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) | x)
#define MX_CLRBIT(sc, reg, x) \
#define DC_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) & ~x)
#define MIIF_AUTOTIMEOUT 0x0004
static int mxphy_probe __P((device_t));
static int mxphy_attach __P((device_t));
static int mxphy_detach __P((device_t));
static int dcphy_probe __P((device_t));
static int dcphy_attach __P((device_t));
static int dcphy_detach __P((device_t));
static device_method_t mxphy_methods[] = {
static device_method_t dcphy_methods[] = {
/* device interface */
DEVMETHOD(device_probe, mxphy_probe),
DEVMETHOD(device_attach, mxphy_attach),
DEVMETHOD(device_detach, mxphy_detach),
DEVMETHOD(device_probe, dcphy_probe),
DEVMETHOD(device_attach, dcphy_attach),
DEVMETHOD(device_detach, dcphy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};
static devclass_t mxphy_devclass;
static devclass_t dcphy_devclass;
static driver_t mxphy_driver = {
"mxphy",
mxphy_methods,
static driver_t dcphy_driver = {
"dcphy",
dcphy_methods,
sizeof(struct mii_softc)
};
DRIVER_MODULE(mxphy, miibus, mxphy_driver, mxphy_devclass, 0, 0);
DRIVER_MODULE(dcphy, miibus, dcphy_driver, dcphy_devclass, 0, 0);
int mxphy_service __P((struct mii_softc *, struct mii_data *, int));
void mxphy_status __P((struct mii_softc *));
static int mxphy_auto __P((struct mii_softc *, int));
static void mxphy_reset __P((struct mii_softc *));
int dcphy_service __P((struct mii_softc *, struct mii_data *, int));
void dcphy_status __P((struct mii_softc *));
static int dcphy_auto __P((struct mii_softc *, int));
static void dcphy_reset __P((struct mii_softc *));
static int mxphy_probe(dev)
static int dcphy_probe(dev)
device_t dev;
{
struct mii_attach_args *ma;
@ -121,25 +122,25 @@ static int mxphy_probe(dev)
ma = device_get_ivars(dev);
/*
* The mx driver will report a Macronix vendor and device
* The dc driver will report the 21143 vendor and device
* ID to let us know that it wants us to attach.
*/
if (ma->mii_id1 != MX_VENDORID ||
ma->mii_id2 != MX_DEVICEID_987x5)
if (ma->mii_id1 != DC_VENDORID_DEC ||
ma->mii_id2 != DC_DEVICEID_21143)
return(ENXIO);
device_set_desc(dev, "Macronix NWAY media interface");
device_set_desc(dev, "Intel 21143 NWAY media interface");
return (0);
}
static int mxphy_attach(dev)
static int dcphy_attach(dev)
device_t dev;
{
struct mii_softc *sc;
struct mii_attach_args *ma;
struct mii_data *mii;
struct mx_softc *mx_sc;
struct dc_softc *dc_sc;
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
@ -149,7 +150,7 @@ static int mxphy_attach(dev)
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = mxphy_service;
sc->mii_service = dcphy_service;
sc->mii_pdata = mii;
sc->mii_flags |= MIIF_NOISOLATE;
@ -163,13 +164,24 @@ static int mxphy_attach(dev)
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
BMCR_LOOP|BMCR_S100);
/*mxphy_reset(sc);*/
mx_sc = mii->mii_ifp->if_softc;
CSR_WRITE_4(mx_sc, MX_10BTSTAT, 0);
CSR_WRITE_4(mx_sc, MX_10BTCTRL, 0);
/*dcphy_reset(sc);*/
dc_sc = mii->mii_ifp->if_softc;
CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0);
CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0);
switch(pci_read_config(device_get_parent(sc->mii_dev),
DC_PCI_CSID, 4)) {
case 0x99999999:
/* Example of how to only allow 10Mbps modes. */
sc->mii_capabilities = BMSR_10TFDX|BMSR_10THDX;
break;
default:
sc->mii_capabilities =
BMSR_ANEG|BMSR_100TXFDX|BMSR_100TXHDX|
BMSR_10TFDX|BMSR_10THDX;
break;
}
sc->mii_capabilities =
BMSR_ANEG|BMSR_100TXFDX|BMSR_100TXHDX|BMSR_10TFDX|BMSR_10THDX;
sc->mii_capabilities &= ma->mii_capmask;
device_printf(dev, " ");
if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0)
@ -183,7 +195,7 @@ static int mxphy_attach(dev)
return(0);
}
static int mxphy_detach(dev)
static int dcphy_detach(dev)
device_t dev;
{
struct mii_softc *sc;
@ -198,17 +210,17 @@ static int mxphy_detach(dev)
}
int
mxphy_service(sc, mii, cmd)
dcphy_service(sc, mii, cmd)
struct mii_softc *sc;
struct mii_data *mii;
int cmd;
{
struct mx_softc *mx_sc;
struct dc_softc *dc_sc;
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int reg;
u_int32_t mode;
mx_sc = mii->mii_ifp->if_softc;
dc_sc = mii->mii_ifp->if_softc;
switch (cmd) {
case MII_POLLSTAT:
@ -237,14 +249,14 @@ mxphy_service(sc, mii, cmd)
sc->mii_flags = 0;
mii->mii_media_active = IFM_NONE;
mode = CSR_READ_4(mx_sc, MX_NETCFG);
mode &= ~(MX_NETCFG_FULLDUPLEX|MX_NETCFG_PORTSEL|
MX_NETCFG_PCS|MX_NETCFG_SCRAMBLER|MX_NETCFG_SPEEDSEL);
mode = CSR_READ_4(dc_sc, DC_NETCFG);
mode &= ~(DC_NETCFG_FULLDUPLEX|DC_NETCFG_PORTSEL|
DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER|DC_NETCFG_SPEEDSEL);
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_AUTO:
mxphy_reset(sc);
(void) mxphy_auto(sc, 0);
/*dcphy_reset(sc);*/
(void) dcphy_auto(sc, 0);
break;
case IFM_100_T4:
/*
@ -252,26 +264,32 @@ mxphy_service(sc, mii, cmd)
*/
return (EINVAL);
case IFM_100_TX:
mxphy_reset(sc);
MX_CLRBIT(mx_sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL);
mode |= MX_NETCFG_PORTSEL|MX_NETCFG_PCS|
MX_NETCFG_SCRAMBLER;
dcphy_reset(sc);
DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
mode |= DC_NETCFG_PORTSEL|DC_NETCFG_PCS|
DC_NETCFG_SCRAMBLER;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mode |= MX_NETCFG_FULLDUPLEX;
mode |= DC_NETCFG_FULLDUPLEX;
else
mode &= ~MX_NETCFG_FULLDUPLEX;
CSR_WRITE_4(mx_sc, MX_NETCFG, mode);
mode &= ~DC_NETCFG_FULLDUPLEX;
CSR_WRITE_4(dc_sc, DC_NETCFG, mode);
break;
case IFM_10_T:
mxphy_reset(sc);
MX_CLRBIT(mx_sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL);
mode &= ~MX_NETCFG_PORTSEL;
mode |= MX_NETCFG_SPEEDSEL;
DC_CLRBIT(dc_sc, DC_SIARESET, DC_SIA_RESET);
DC_CLRBIT(dc_sc, DC_10BTCTRL, 0xFFFF);
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mode |= MX_NETCFG_FULLDUPLEX;
DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3D);
else
mode &= ~MX_NETCFG_FULLDUPLEX;
CSR_WRITE_4(mx_sc, MX_NETCFG, mode);
DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3F);
DC_SETBIT(dc_sc, DC_SIARESET, DC_SIA_RESET);
DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
mode &= ~DC_NETCFG_PORTSEL;
mode |= DC_NETCFG_SPEEDSEL;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mode |= DC_NETCFG_FULLDUPLEX;
else
mode &= ~DC_NETCFG_FULLDUPLEX;
CSR_WRITE_4(dc_sc, DC_NETCFG, mode);
break;
default:
return(EINVAL);
@ -315,25 +333,31 @@ mxphy_service(sc, mii, cmd)
* need to restart the autonegotiation process. Read
* the BMSR twice in case it's latched.
*/
reg = CSR_READ_4(mx_sc, MX_10BTSTAT) &
(MX_TSTAT_LS10|MX_TSTAT_LS100);
reg = CSR_READ_4(dc_sc, DC_10BTSTAT) &
(DC_TSTAT_LS10|DC_TSTAT_LS100);
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX &&
!(reg & MX_TSTAT_LS100)) {
!(reg & DC_TSTAT_LS100)) {
if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
break;
} else
return(0);
} else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T &&
!(reg & MX_TSTAT_LS10)) {
!(reg & DC_TSTAT_LS10)) {
if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
break;
} else
return(0);
} else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE &&
(!(reg & MX_TSTAT_LS10) || !(reg & MX_TSTAT_LS100))) {
(!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))) {
if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
break;
} else
return(0);
} else if (CSR_READ_4(dc_sc, DC_ISR) & DC_ISR_LINKGOOD) {
if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
break;
@ -342,14 +366,14 @@ mxphy_service(sc, mii, cmd)
}
sc->mii_ticks = 0;
mxphy_reset(sc);
mxphy_auto(sc, 0);
/*dcphy_reset(sc);*/
dcphy_auto(sc, 0);
break;
}
/* Update the media status. */
mxphy_status(sc);
dcphy_status(sc);
/* Callback if something changed. */
if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
@ -360,22 +384,22 @@ mxphy_service(sc, mii, cmd)
}
void
mxphy_status(sc)
dcphy_status(sc)
struct mii_softc *sc;
{
struct mii_data *mii = sc->mii_pdata;
int reg, anlpar;
struct mx_softc *mx_sc;
struct dc_softc *dc_sc;
mx_sc = mii->mii_ifp->if_softc;
dc_sc = mii->mii_ifp->if_softc;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
reg = CSR_READ_4(mx_sc, MX_10BTSTAT) &
(MX_TSTAT_LS10|MX_TSTAT_LS100);
reg = CSR_READ_4(dc_sc, DC_10BTSTAT) &
(DC_TSTAT_LS10|DC_TSTAT_LS100);
if (!(reg & MX_TSTAT_LS10) || !(reg & MX_TSTAT_LS100))
if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
mii->mii_media_status |= IFM_ACTIVE;
if (sc->mii_flags & MIIF_DOINGAUTO) {
@ -383,17 +407,17 @@ mxphy_status(sc)
return;
}
if (CSR_READ_4(mx_sc, MX_10BTCTRL) & MX_TCTL_AUTONEGENBL &&
CSR_READ_4(mx_sc, MX_10BTSTAT) & MX_TSTAT_ANEGSTAT) {
if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL &&
CSR_READ_4(dc_sc, DC_10BTSTAT) & DC_TSTAT_ANEGSTAT) {
/* Erg, still trying, I guess... */
if ((CSR_READ_4(mx_sc, MX_10BTSTAT) &
MX_ASTAT_AUTONEGCMP) != MX_ASTAT_AUTONEGCMP) {
if ((CSR_READ_4(dc_sc, DC_10BTSTAT) &
DC_ASTAT_AUTONEGCMP) != DC_ASTAT_AUTONEGCMP) {
mii->mii_media_active |= IFM_NONE;
return;
}
if (CSR_READ_4(mx_sc, MX_10BTSTAT) & MX_TSTAT_LP_CAN_NWAY) {
anlpar = CSR_READ_4(mx_sc, MX_10BTSTAT) >> 16;
if (CSR_READ_4(dc_sc, DC_10BTSTAT) & DC_TSTAT_LP_CAN_NWAY) {
anlpar = CSR_READ_4(dc_sc, DC_10BTSTAT) >> 16;
if (anlpar & ANLPAR_T4)
mii->mii_media_active |= IFM_100_T4;
else if (anlpar & ANLPAR_TX_FD)
@ -406,59 +430,65 @@ mxphy_status(sc)
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_NONE;
if (DC_IS_INTEL(dc_sc))
DC_CLRBIT(dc_sc, DC_10BTCTRL,
DC_TCTL_AUTONEGENBL);
return;
}
/*
* If the other side doesn't support NWAY, then the
* If the other side doesn't support NWAY, then the
* best we can do is determine if we have a 10Mbps or
* 100Mbps link. There's no way to know if the link
* 100Mbps link. There's no way to know if the link
* is full or half duplex, so we default to half duplex
* and hope that the user is clever enough to manually
* change the media settings if we're wrong.
*/
if (!(reg & MX_TSTAT_LS100))
if (!(reg & DC_TSTAT_LS100))
mii->mii_media_active |= IFM_100_TX;
else if (!(reg & MX_TSTAT_LS10))
else if (!(reg & DC_TSTAT_LS10))
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_NONE;
if (DC_IS_INTEL(dc_sc))
DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
return;
}
if (CSR_READ_4(mx_sc, MX_NETCFG) & MX_NETCFG_SCRAMBLER)
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SCRAMBLER)
mii->mii_media_active |= IFM_100_TX;
else
mii->mii_media_active |= IFM_10_T;
if (CSR_READ_4(mx_sc, MX_NETCFG) & MX_NETCFG_FULLDUPLEX)
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
mii->mii_media_active |= IFM_FDX;
return;
}
static int
mxphy_auto(mii, waitfor)
dcphy_auto(mii, waitfor)
struct mii_softc *mii;
int waitfor;
{
int i;
struct mx_softc *sc;
struct dc_softc *sc;
sc = mii->mii_pdata->mii_ifp->if_softc;
if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
CSR_WRITE_4(sc, MX_10BTCTRL, 0x3FFFF);
MX_CLRBIT(sc, MX_NETCFG, MX_NETCFG_PORTSEL);
MX_SETBIT(sc, MX_NETCFG, MX_NETCFG_FULLDUPLEX);
MX_SETBIT(sc, MX_10BTCTRL, MX_TCTL_AUTONEGENBL);
MX_SETBIT(sc, MX_10BTCTRL, MX_ASTAT_TXDISABLE);
DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF);
DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
DC_SETBIT(sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
DC_SETBIT(sc, DC_10BTSTAT, DC_ASTAT_TXDISABLE);
}
if (waitfor) {
/* Wait 500ms for it to complete. */
for (i = 0; i < 500; i++) {
if ((CSR_READ_4(sc, MX_10BTSTAT) & MX_TSTAT_ANEGSTAT)
== MX_ASTAT_AUTONEGCMP)
if ((CSR_READ_4(sc, DC_10BTSTAT) & DC_TSTAT_ANEGSTAT)
== DC_ASTAT_AUTONEGCMP)
return(0);
DELAY(1000);
}
@ -482,16 +512,16 @@ mxphy_auto(mii, waitfor)
}
static void
mxphy_reset(mii)
dcphy_reset(mii)
struct mii_softc *mii;
{
struct mx_softc *sc;
struct dc_softc *sc;
sc = mii->mii_pdata->mii_ifp->if_softc;
MX_SETBIT(sc, MX_SIARESET, MX_SIA_RESET_NWAY);
DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
DELAY(1000);
MX_CLRBIT(sc, MX_SIARESET, MX_SIA_RESET_NWAY);
DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
return;
}

2689
sys/dev/dc/if_dc.c Normal file
View File

File diff suppressed because it is too large Load Diff

903
sys/dev/dc/if_dcreg.h Normal file
View File

@ -0,0 +1,903 @@
/*
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* 21143 and clone common register definitions.
*/
#define DC_BUSCTL 0x00 /* bus control */
#define DC_TXSTART 0x08 /* tx start demand */
#define DC_RXSTART 0x10 /* rx start demand */
#define DC_RXADDR 0x18 /* rx descriptor list start addr */
#define DC_TXADDR 0x20 /* tx descriptor list start addr */
#define DC_ISR 0x28 /* interrupt status register */
#define DC_NETCFG 0x30 /* network config register */
#define DC_IMR 0x38 /* interrupt mask */
#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
#define DC_SIO 0x48 /* MII and ROM/EEPROM access */
#define DC_ROM 0x50 /* ROM programming address */
#define DC_TIMER 0x58 /* general timer */
#define DC_10BTSTAT 0x60 /* SIA status */
#define DC_SIARESET 0x68 /* SIA connectivity */
#define DC_10BTCTRL 0x70 /* SIA transmit and receive */
#define DC_WATCHDOG 0x78 /* SIA and general purpose port */
/*
* There are two general 'types' of MX chips that we need to be
* concerned with. One is the original 98713, which has its internal
* NWAY support controlled via the MDIO bits in the serial I/O
* register. The other is everything else (from the 98713A on up),
* which has its internal NWAY controlled via CSR13, CSR14 and CSR15,
* just like the 21143. This type setting also governs which of the
* 'magic' numbers we write to CSR16. The PNIC II falls into the
* 98713A/98715/98715A/98725 category.
*/
#define DC_TYPE_98713 0x1
#define DC_TYPE_98713A 0x2
#define DC_TYPE_987x5 0x3
/* Other type of supported chips. */
#define DC_TYPE_21143 0x4 /* Intel 21143 */
#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */
#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */
#define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */
#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */
#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */
#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */
#define DC_IS_MACRONIX(x) \
(x->dc_type == DC_TYPE_98713 || \
x->dc_type == DC_TYPE_98713A || \
x->dc_type == DC_TYPE_987x5)
#define DC_IS_ADMTEK(x) \
(x->dc_type == DC_TYPE_AL981 || \
x->dc_type == DC_TYPE_AN985)
#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143)
#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX)
#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981)
#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985)
#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102)
#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII)
#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC)
/* MII/symbol mode port types */
#define DC_PMODE_MII 0x1
#define DC_PMODE_SYM 0x2
/*
* Bus control bits.
*/
#define DC_BUSCTL_RESET 0x00000001
#define DC_BUSCTL_ARBITRATION 0x00000002
#define DC_BUSCTL_SKIPLEN 0x0000007C
#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080
#define DC_BUSCTL_BURSTLEN 0x00003F00
#define DC_BUSCTL_CACHEALIGN 0x0000C000
#define DC_BUSCTL_TXPOLL 0x000E0000
#define DC_BUSCTL_DBO 0x00100000
#define DC_BUSCTL_MRME 0x00200000
#define DC_BUSCTL_MRLE 0x00800000
#define DC_BUSCTL_MWIE 0x01000000
#define DC_BUSCTL_ONNOW_ENB 0x04000000
#define DC_SKIPLEN_1LONG 0x00000004
#define DC_SKIPLEN_2LONG 0x00000008
#define DC_SKIPLEN_3LONG 0x00000010
#define DC_SKIPLEN_4LONG 0x00000020
#define DC_SKIPLEN_5LONG 0x00000040
#define DC_CACHEALIGN_NONE 0x00000000
#define DC_CACHEALIGN_8LONG 0x00004000
#define DC_CACHEALIGN_16LONG 0x00008000
#define DC_CACHEALIGN_32LONG 0x0000C000
#define DC_BURSTLEN_USECA 0x00000000
#define DC_BURSTLEN_1LONG 0x00000100
#define DC_BURSTLEN_2LONG 0x00000200
#define DC_BURSTLEN_4LONG 0x00000400
#define DC_BURSTLEN_8LONG 0x00000800
#define DC_BURSTLEN_16LONG 0x00001000
#define DC_BURSTLEN_32LONG 0x00002000
#define DC_TXPOLL_OFF 0x00000000
#define DC_TXPOLL_1 0x00020000
#define DC_TXPOLL_2 0x00040000
#define DC_TXPOLL_3 0x00060000
#define DC_TXPOLL_4 0x00080000
#define DC_TXPOLL_5 0x000A0000
#define DC_TXPOLL_6 0x000C0000
#define DC_TXPOLL_7 0x000E0000
/*
* Interrupt status bits.
*/
#define DC_ISR_TX_OK 0x00000001
#define DC_ISR_TX_IDLE 0x00000002
#define DC_ISR_TX_NOBUF 0x00000004
#define DC_ISR_TX_JABBERTIMEO 0x00000008
#define DC_ISR_LINKGOOD 0x00000010
#define DC_ISR_TX_UNDERRUN 0x00000020
#define DC_ISR_RX_OK 0x00000040
#define DC_ISR_RX_NOBUF 0x00000080
#define DC_ISR_RX_READ 0x00000100
#define DC_ISR_RX_WATDOGTIMEO 0x00000200
#define DC_ISR_TX_EARLY 0x00000400
#define DC_ISR_TIMER_EXPIRED 0x00000800
#define DC_ISR_LINKFAIL 0x00001000
#define DC_ISR_BUS_ERR 0x00002000
#define DC_ISR_RX_EARLY 0x00004000
#define DC_ISR_ABNORMAL 0x00008000
#define DC_ISR_NORMAL 0x00010000
#define DC_ISR_RX_STATE 0x000E0000
#define DC_ISR_TX_STATE 0x00700000
#define DC_ISR_BUSERRTYPE 0x03800000
#define DC_ISR_100MBPSLINK 0x08000000
#define DC_ISR_MAGICKPACK 0x10000000
#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */
#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
/*
* Network config bits.
*/
#define DC_NETCFG_RX_HASHPERF 0x00000001
#define DC_NETCFG_RX_ON 0x00000002
#define DC_NETCFG_RX_HASHONLY 0x00000004
#define DC_NETCFG_RX_BADFRAMES 0x00000008
#define DC_NETCFG_RX_INVFILT 0x00000010
#define DC_NETCFG_BACKOFFCNT 0x00000020
#define DC_NETCFG_RX_PROMISC 0x00000040
#define DC_NETCFG_RX_ALLMULTI 0x00000080
#define DC_NETCFG_FULLDUPLEX 0x00000200
#define DC_NETCFG_LOOPBACK 0x00000C00
#define DC_NETCFG_FORCECOLL 0x00001000
#define DC_NETCFG_TX_ON 0x00002000
#define DC_NETCFG_TX_THRESH 0x0000C000
#define DC_NETCFG_TX_BACKOFF 0x00020000
#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
#define DC_NETCFG_HEARTBEAT 0x00080000
#define DC_NETCFG_STORENFWD 0x00200000
#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
#define DC_NETCFG_PCS 0x00800000
#define DC_NETCFG_SCRAMBLER 0x01000000
#define DC_NETCFG_NO_RXCRC 0x02000000
#define DC_NETCFG_RX_ALL 0x40000000
#define DC_NETCFG_CAPEFFECT 0x80000000
#define DC_OPMODE_NORM 0x00000000
#define DC_OPMODE_INTLOOP 0x00000400
#define DC_OPMODE_EXTLOOP 0x00000800
#define DC_TXTHRESH_72BYTES 0x00000000
#define DC_TXTHRESH_96BYTES 0x00004000
#define DC_TXTHRESH_128BYTES 0x00008000
#define DC_TXTHRESH_160BYTES 0x0000C000
/*
* Interrupt mask bits.
*/
#define DC_IMR_TX_OK 0x00000001
#define DC_IMR_TX_IDLE 0x00000002
#define DC_IMR_TX_NOBUF 0x00000004
#define DC_IMR_TX_JABBERTIMEO 0x00000008
#define DC_IMR_LINKGOOD 0x00000010
#define DC_IMR_TX_UNDERRUN 0x00000020
#define DC_IMR_RX_OK 0x00000040
#define DC_IMR_RX_NOBUF 0x00000080
#define DC_IMR_RX_READ 0x00000100
#define DC_IMR_RX_WATDOGTIMEO 0x00000200
#define DC_IMR_TX_EARLY 0x00000400
#define DC_IMR_TIMER_EXPIRED 0x00000800
#define DC_IMR_LINKFAIL 0x00001000
#define DC_IMR_BUS_ERR 0x00002000
#define DC_IMR_RX_EARLY 0x00004000
#define DC_IMR_ABNORMAL 0x00008000
#define DC_IMR_NORMAL 0x00010000
#define DC_IMR_100MBPSLINK 0x08000000
#define DC_IMR_MAGICKPACK 0x10000000
#define DC_INTRS \
(DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\
DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \
DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/)
/*
* Serial I/O (EEPROM/ROM) bits.
*/
#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */
#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */
#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
#define DC_SIO_ROMDATA4 0x00000010
#define DC_SIO_ROMDATA5 0x00000020
#define DC_SIO_ROMDATA6 0x00000040
#define DC_SIO_ROMDATA7 0x00000080
#define DC_SIO_EESEL 0x00000800
#define DC_SIO_ROMSEL 0x00001000
#define DC_SIO_ROMCTL_WRITE 0x00002000
#define DC_SIO_ROMCTL_READ 0x00004000
#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */
#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */
#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
#define DC_EECMD_WRITE 0x140
#define DC_EECMD_READ 0x180
#define DC_EECMD_ERASE 0x1c0
#define DC_EE_NODEADDR_OFFSET 0x70
#define DC_EE_NODEADDR 10
/*
* General purpose timer register
*/
#define DC_TIMER_VALUE 0x0000FFFF
#define DC_TIMER_CONTINUOUS 0x00010000
/*
* 10baseT status register
*/
#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */
#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */
#define DC_TSTAT_AUTOPOLARITY 0x00000008
#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */
#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */
#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */
#define DC_TSTAT_REMFAULT 0x00000800
#define DC_TSTAT_ANEGSTAT 0x00007000
#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
#define DC_ASTAT_DISABLE 0x00000000
#define DC_ASTAT_TXDISABLE 0x00001000
#define DC_ASTAT_ABDETECT 0x00002000
#define DC_ASTAT_ACKDETECT 0x00003000
#define DC_ASTAT_CMPACKDETECT 0x00004000
#define DC_ASTAT_AUTONEGCMP 0x00005000
#define DC_ASTAT_LINKCHECK 0x00006000
/*
* PHY reset register
*/
#define DC_SIA_RESET 0x00000001
#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */
/*
* 10baseT control register
*/
#define DC_TCTL_ENCODER_ENB 0x00000001
#define DC_TCTL_LOOPBACK 0x00000002
#define DC_TCTL_DRIVER_ENB 0x00000004
#define DC_TCTL_LNKPULSE_ENB 0x00000008
#define DC_TCTL_HALFDUPLEX 0x00000040
#define DC_TCTL_AUTONEGENBL 0x00000080
#define DC_TCTL_RX_SQUELCH 0x00000100
#define DC_TCTL_COLL_SQUELCH 0x00000200
#define DC_TCTL_COLL_DETECT 0x00000400
#define DC_TCTL_SQE_ENB 0x00000800
#define DC_TCTL_LINKTEST 0x00001000
#define DC_TCTL_AUTOPOLARITY 0x00002000
#define DC_TCTL_SET_POL_PLUS 0x00004000
#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */
#define DC_TCTL_100BTXHALF 0x00010000
#define DC_TCTL_100BTXFULL 0x00020000
#define DC_TCTL_100BT4 0x00040000
/*
* Watchdog timer register
*/
#define DC_WDOG_JABBERDIS 0x00000001
#define DC_WDOG_HOSTUNJAB 0x00000002
#define DC_WDOG_JABBERCLK 0x00000004
#define DC_WDOG_RXWDOGDIS 0x00000010
#define DC_WDOG_RXWDOGCLK 0x00000020
#define DC_WDOG_MUSTBEZERO 0x00000100
/*
* Size of a setup frame.
*/
#define DC_SFRAME_LEN 192
/*
* 21x4x TX/RX list structure.
*/
struct dc_desc {
u_int32_t dc_status;
u_int32_t dc_ctl;
u_int32_t dc_ptr1;
u_int32_t dc_ptr2;
};
#define dc_data dc_ptr1
#define dc_next dc_ptr2
#define DC_RXSTAT_FIFOOFLOW 0x00000001
#define DC_RXSTAT_CRCERR 0x00000002
#define DC_RXSTAT_DRIBBLE 0x00000004
#define DC_RXSTAT_WATCHDOG 0x00000010
#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
#define DC_RXSTAT_COLLSEEN 0x00000040
#define DC_RXSTAT_GIANT 0x00000080
#define DC_RXSTAT_LASTFRAG 0x00000100
#define DC_RXSTAT_FIRSTFRAG 0x00000200
#define DC_RXSTAT_MULTICAST 0x00000400
#define DC_RXSTAT_RUNT 0x00000800
#define DC_RXSTAT_RXTYPE 0x00003000
#define DC_RXSTAT_RXERR 0x00008000
#define DC_RXSTAT_RXLEN 0x3FFF0000
#define DC_RXSTAT_OWN 0x80000000
#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16)
#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN)
#define DC_RXCTL_BUFLEN1 0x00000FFF
#define DC_RXCTL_BUFLEN2 0x00FFF000
#define DC_RXCTL_RLINK 0x01000000
#define DC_RXCTL_RLAST 0x02000000
#define DC_TXSTAT_DEFER 0x00000001
#define DC_TXSTAT_UNDERRUN 0x00000002
#define DC_TXSTAT_LINKFAIL 0x00000003
#define DC_TXSTAT_COLLCNT 0x00000078
#define DC_TXSTAT_SQE 0x00000080
#define DC_TXSTAT_EXCESSCOLL 0x00000100
#define DC_TXSTAT_LATECOLL 0x00000200
#define DC_TXSTAT_NOCARRIER 0x00000400
#define DC_TXSTAT_CARRLOST 0x00000800
#define DC_TXSTAT_JABTIMEO 0x00004000
#define DC_TXSTAT_ERRSUM 0x00008000
#define DC_TXSTAT_OWN 0x80000000
#define DC_TXCTL_BUFLEN1 0x000007FF
#define DC_TXCTL_BUFLEN2 0x003FF800
#define DC_TXCTL_FILTTYPE0 0x00400000
#define DC_TXCTL_PAD 0x00800000
#define DC_TXCTL_TLINK 0x01000000
#define DC_TXCTL_TLAST 0x02000000
#define DC_TXCTL_NOCRC 0x04000000
#define DC_TXCTL_SETUP 0x08000000
#define DC_TXCTL_FILTTYPE1 0x10000000
#define DC_TXCTL_FIRSTFRAG 0x20000000
#define DC_TXCTL_LASTFRAG 0x40000000
#define DC_TXCTL_FINT 0x80000000
#define DC_FILTER_PERFECT 0x00000000
#define DC_FILTER_HASHPERF 0x00400000
#define DC_FILTER_INVERSE 0x10000000
#define DC_FILTER_HASHONLY 0x10400000
#define DC_MAXFRAGS 16
#define DC_RX_LIST_CNT 64
#define DC_TX_LIST_CNT 256
#define DC_MIN_FRAMELEN 60
#define DC_RXLEN 1536
#define DC_INC(x, y) (x) = (x + 1) % y
struct dc_list_data {
struct dc_desc dc_rx_list[DC_RX_LIST_CNT];
struct dc_desc dc_tx_list[DC_TX_LIST_CNT];
};
struct dc_chain_data {
struct mbuf *dc_rx_chain[DC_RX_LIST_CNT];
struct mbuf *dc_tx_chain[DC_TX_LIST_CNT];
u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)];
u_int8_t dc_pad[DC_MIN_FRAMELEN];
int dc_tx_prod;
int dc_tx_cons;
int dc_tx_cnt;
int dc_rx_prod;
};
struct dc_type {
u_int16_t dc_vid;
u_int16_t dc_did;
char *dc_name;
};
struct dc_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define DC_MII_STARTDELIM 0x01
#define DC_MII_READOP 0x02
#define DC_MII_WRITEOP 0x01
#define DC_MII_TURNAROUND 0x02
/*
* Registers specific to clone devices.
* This mainly relates to RX filter programming: not all 21x4x clones
* use the standard DEC filter programming mechanism.
*/
/*
* ADMtek specific registers and constants for the AL981 and AN985.
* The AN985 doesn't use the magic PHY registers.
*/
#define DC_AL_PAR0 0xA4 /* station address */
#define DC_AL_PAR1 0xA8 /* station address */
#define DC_AL_MAR0 0xAC /* multicast hash filter */
#define DC_AL_MAR1 0xB0 /* multicast hash filter */
#define DC_AL_BMCR 0xB4 /* built in PHY control */
#define DC_AL_BMSR 0xB8 /* built in PHY status */
#define DC_AL_VENID 0xBC /* built in PHY ID0 */
#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */
#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */
#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */
#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */
#define DC_ADMTEK_PHYADDR 0x1
#define DC_AL_EE_NODEADDR 4
/* End of ADMtek specific registers */
/*
* ASIX specific registers.
*/
#define DC_AX_FILTIDX 0x68 /* RX filter index */
#define DC_AX_FILTDATA 0x70 /* RX filter data */
/*
* Special ASIX-specific bits in the ASIX NETCFG register (CSR6).
*/
#define DC_AX_NETCFG_RX_BROAD 0x00000100
/*
* RX Filter Index Register values
*/
#define DC_AX_FILTIDX_PAR0 0x00000000
#define DC_AX_FILTIDX_PAR1 0x00000001
#define DC_AX_FILTIDX_MAR0 0x00000002
#define DC_AX_FILTIDX_MAR1 0x00000003
/* End of ASIX specific registers */
/*
* Macronix specific registers. The Macronix chips have a special
* register for reading the NWAY status, which we don't use, plus
* a magic packet register, which we need to tweak a bit per the
* Macronix application notes.
*/
#define DC_MX_MAGICPACKET 0x80
#define DC_MX_NWAYSTAT 0xA0
/*
* Magic packet register
*/
#define DC_MX_MPACK_DISABLE 0x00400000
/*
* NWAY status register.
*/
#define DC_MX_NWAY_10BTHALF 0x08000000
#define DC_MX_NWAY_10BTFULL 0x10000000
#define DC_MX_NWAY_100BTHALF 0x20000000
#define DC_MX_NWAY_100BTFULL 0x40000000
#define DC_MX_NWAY_100BT4 0x80000000
/*
* These are magic values that must be written into CSR16
* (DC_MX_MAGICPACKET) in order to put the chip into proper
* operating mode. The magic numbers are documented in the
* Macronix 98715 application notes.
*/
#define DC_MX_MAGIC_98713 0x0F370000
#define DC_MX_MAGIC_98713A 0x0B3C0000
#define DC_MX_MAGIC_98715 0x0B3C0000
#define DC_MX_MAGIC_98725 0x0B3C0000
/* End of Macronix specific registers */
/*
* PNIC 82c168/82c169 specific registers.
* The PNIC has its own special NWAY support, which doesn't work,
* and shortcut ways of reading the EEPROM and MII bus.
*/
#define DC_PN_GPIO 0x60 /* general purpose pins control */
#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */
#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */
#define DC_PN_MII 0xA0 /* MII access register */
#define DC_PN_NWAY 0xB8 /* Internal NWAY register */
/* Serial I/O EEPROM register */
#define DC_PN_SIOCTL_DATA 0x0000003F
#define DC_PN_SIOCTL_OPCODE 0x00000300
#define DC_PN_SIOCTL_BUSY 0x80000000
#define DC_PN_EEOPCODE_ERASE 0x00000300
#define DC_PN_EEOPCODE_READ 0x00000600
#define DC_PN_EEOPCODE_WRITE 0x00000100
/*
* The first two general purpose pins control speed selection and
* 100Mbps loopback on the 82c168 chip. The control bits should always
* be set (to make the data pins outputs) and the speed selction and
* loopback bits set accordingly when changing media. Physically, this
* will set the state of a relay mounted on the card.
*/
#define DC_PN_GPIO_DATA0 0x000000001
#define DC_PN_GPIO_DATA1 0x000000002
#define DC_PN_GPIO_DATA2 0x000000004
#define DC_PN_GPIO_DATA3 0x000000008
#define DC_PN_GPIO_CTL0 0x000000010
#define DC_PN_GPIO_CTL1 0x000000020
#define DC_PN_GPIO_CTL2 0x000000040
#define DC_PN_GPIO_CTL3 0x000000080
#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */
#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */
#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2
#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3
#define DC_PN_GPIO_SETBIT(sc, r) \
DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4)))
#define DC_PN_GPIO_CLRBIT(sc, r) \
{ \
DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \
DC_CLRBIT(sc, DC_PN_GPIO, (r)); \
}
/* shortcut MII access register */
#define DC_PN_MII_DATA 0x0000FFFF
#define DC_PN_MII_RESERVER 0x00020000
#define DC_PN_MII_REGADDR 0x007C0000
#define DC_PN_MII_PHYADDR 0x0F800000
#define DC_PN_MII_OPCODE 0x30000000
#define DC_PN_MII_BUSY 0x80000000
#define DC_PN_MIIOPCODE_READ 0x60020000
#define DC_PN_MIIOPCODE_WRITE 0x50020000
/* Internal NWAY bits */
#define DC_PN_NWAY_RESET 0x00000001 /* reset */
#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */
#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */
#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */
#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */
#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */
#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */
#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */
#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */
#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */
#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */
#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */
#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */
#define DC_PN_NWAY_CAP10HDX 0x00002000
#define DC_PN_NWAY_CAP10FDX 0x00004000
#define DC_PN_NWAY_CAP100FDX 0x00008000
#define DC_PN_NWAY_CAP100HDX 0x00010000
#define DC_PN_NWAY_CAP100T4 0x00020000
#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */
#define DC_PN_NWAY_REMFAULT 0x04000000
#define DC_PN_NWAY_LPAR10HDX 0x08000000
#define DC_PN_NWAY_LPAR10FDX 0x10000000
#define DC_PN_NWAY_LPAR100FDX 0x20000000
#define DC_PN_NWAY_LPAR100HDX 0x40000000
#define DC_PN_NWAY_LPAR100T4 0x80000000
/* End of PNIC specific registers */
struct dc_softc {
struct arpcom arpcom; /* interface info */
bus_space_handle_t dc_bhandle; /* bus space handle */
bus_space_tag_t dc_btag; /* bus space tag */
void *dc_intrhand;
struct resource *dc_irq;
struct resource *dc_res;
struct dc_type *dc_info; /* adapter info */
device_t dc_miibus;
u_int8_t dc_unit; /* interface number */
u_int8_t dc_type;
u_int8_t dc_pmode;
u_int8_t dc_link;
u_int8_t dc_cachesize;
int dc_pnic_rx_bug_save;
unsigned char *dc_pnic_rx_buf;
int dc_if_flags;
int dc_if_media;
u_int32_t dc_flags;
u_int32_t dc_txthresh;
struct dc_list_data *dc_ldata;
struct dc_chain_data dc_cdata;
struct callout_handle dc_stat_ch;
};
#define DC_TX_POLL 0x00000001
#define DC_TX_COALESCE 0x00000002
#define DC_TX_ADMTEK_WAR 0x00000004
#define DC_TX_USE_TX_INTR 0x00000008
#define DC_RX_FILTER_TULIP 0x00000010
#define DC_TX_INTR_FIRSTFRAG 0x00000020
#define DC_PNIC_RX_BUG_WAR 0x00000040
#define DC_TX_FIXED_RING 0x00000080
#define DC_TX_STORENFWD 0x00000100
#define DC_REDUCED_MII_POLL 0x00000200
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)
#define DC_TIMEOUT 1000
#define ETHER_ALIGN 2
/*
* General constants that are fun to know.
*/
/*
* DEC PCI vendor ID
*/
#define DC_VENDORID_DEC 0x1011
/*
* DEC/Intel 21143 PCI device ID
*/
#define DC_DEVICEID_21143 0x0019
/*
* Macronix PCI vendor ID
*/
#define DC_VENDORID_MX 0x10D9
/*
* Macronix PMAC device IDs.
*/
#define DC_DEVICEID_98713 0x0512
#define DC_DEVICEID_987x5 0x0531
/* Macronix PCI revision codes. */
#define DC_REVISION_98713 0x00
#define DC_REVISION_98713A 0x10
#define DC_REVISION_98715 0x20
#define DC_REVISION_98725 0x30
/*
* Compex PCI vendor ID.
*/
#define DC_VENDORID_CP 0x11F6
/*
* Compex PMAC PCI device IDs.
*/
#define DC_DEVICEID_98713_CP 0x9881
/*
* Lite-On PNIC PCI vendor ID
*/
#define DC_VENDORID_LO 0x11AD
/*
* 82c168/82c169 PNIC device IDs. Both chips have the same device
* ID but different revisions. Revision 0x10 is the 82c168, and
* 0x20 is the 82c169.
*/
#define DC_DEVICEID_82C168 0x0002
#define DC_REVISION_82C168 0x10
#define DC_REVISION_82C169 0x20
/*
* Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A
* with wake on lan/magic packet support.
*/
#define DC_DEVICEID_82C115 0xc115
/*
* Davicom vendor ID.
*/
#define DC_VENDORID_DAVICOM 0x1282
/*
* Davicom device IDs.
*/
#define DC_DEVICEID_DM9100 0x9100
#define DC_DEVICEID_DM9102 0x9102
/*
* ADMtek vendor ID.
*/
#define DC_VENDORID_ADMTEK 0x1317
/*
* ADMtek device IDs.
*/
#define DC_DEVICEID_AL981 0x0981
#define DC_DEVICEID_AN985 0x0985
/*
* ASIX vendor ID.
*/
#define DC_VENDORID_ASIX 0x125B
/*
* ASIX device IDs.
*/
#define DC_DEVICEID_AX88140A 0x1400
/*
* The ASIX AX88140 and ASIX AX88141 have the same vendor and
* device IDs but different revision values.
*/
#define DC_REVISION_88140 0x00
#define DC_REVISION_88141 0x10
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define DC_PCI_CFID 0x00 /* Id */
#define DC_PCI_CFCS 0x04 /* Command and status */
#define DC_PCI_CFRV 0x08 /* Revision */
#define DC_PCI_CFLT 0x0C /* Latency timer */
#define DC_PCI_CFBIO 0x10 /* Base I/O address */
#define DC_PCI_CFBMA 0x14 /* Base memory address */
#define DC_PCI_CCIS 0x28 /* Card info struct */
#define DC_PCI_CSID 0x2C /* Subsystem ID */
#define DC_PCI_CBER 0x30 /* Expansion ROM base address */
#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */
#define DC_PCI_CFIT 0x3C /* Interrupt */
#define DC_PCI_CFDD 0x40 /* Device and driver area */
#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */
#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */
#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */
#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */
#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */
#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */
#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */
/* PCI ID register */
#define DC_CFID_VENDOR 0x0000FFFF
#define DC_CFID_DEVICE 0xFFFF0000
/* PCI command/status register */
#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */
#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */
#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */
#define DC_CFCS_MWI_ENB 0x00000008 /* mem write and inval enable */
#define DC_CFCS_PARITYERR_ENB 0x00000020 /* parity error enable */
#define DC_CFCS_SYSERR_ENB 0x00000080 /* system error enable */
#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */
#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */
#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */
#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */
#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */
#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */
#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */
#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */
/* PCI revision register */
#define DC_CFRV_STEPPING 0x0000000F
#define DC_CFRV_REVISION 0x000000F0
#define DC_CFRV_SUBCLASS 0x00FF0000
#define DC_CFRV_BASECLASS 0xFF000000
#define DC_21143_PB_REV 0x00000030
#define DC_21143_TB_REV 0x00000030
#define DC_21143_PC_REV 0x00000030
#define DC_21143_TC_REV 0x00000030
#define DC_21143_PD_REV 0x00000041
#define DC_21143_TD_REV 0x00000041
/* PCI latency timer register */
#define DC_CFLT_CACHELINESIZE 0x000000FF
#define DC_CFLT_LATENCYTIMER 0x0000FF00
/* PCI subsystem ID register */
#define DC_CSID_VENDOR 0x0000FFFF
#define DC_CSID_DEVICE 0xFFFF0000
/* PCI cababilities pointer */
#define DC_CCAP_OFFSET 0x000000FF
/* PCI interrupt config register */
#define DC_CFIT_INTLINE 0x000000FF
#define DC_CFIT_INTPIN 0x0000FF00
#define DC_CFIT_MIN_GNT 0x00FF0000
#define DC_CFIT_MAX_LAT 0xFF000000
/* PCI capability register */
#define DC_CCID_CAPID 0x000000FF
#define DC_CCID_NEXTPTR 0x0000FF00
#define DC_CCID_PM_VERS 0x00070000
#define DC_CCID_PME_CLK 0x00080000
#define DC_CCID_DVSPEC_INT 0x00200000
#define DC_CCID_STATE_D1 0x02000000
#define DC_CCID_STATE_D2 0x04000000
#define DC_CCID_PME_D0 0x08000000
#define DC_CCID_PME_D1 0x10000000
#define DC_CCID_PME_D2 0x20000000
#define DC_CCID_PME_D3HOT 0x40000000
#define DC_CCID_PME_D3COLD 0x80000000
/* PCI power management control/status register */
#define DC_CPMC_STATE 0x00000003
#define DC_CPMC_PME_ENB 0x00000100
#define DC_CPMC_PME_STS 0x00008000
#define DC_PSTATE_D0 0x0
#define DC_PSTATE_D1 0x1
#define DC_PSTATE_D2 0x2
#define DC_PSTATE_D3 0x3
/* Device specific region */
/* Configuration and driver area */
#define DC_CFDD_DRVUSE 0x0000FFFF
#define DC_CFDD_SNOOZE_MODE 0x40000000
#define DC_CFDD_SLEEP_MODE 0x80000000
/* Configuration wake-up command register */
#define DC_CWUC_MUST_BE_ZERO 0x00000001
#define DC_CWUC_SECUREON_ENB 0x00000002
#define DC_CWUC_FORCE_WUL 0x00000004
#define DC_CWUC_BNC_ABILITY 0x00000008
#define DC_CWUC_AUI_ABILITY 0x00000010
#define DC_CWUC_TP10_ABILITY 0x00000020
#define DC_CWUC_MII_ABILITY 0x00000040
#define DC_CWUC_SYM_ABILITY 0x00000080
#define DC_CWUC_LOCK 0x00000100
#ifdef __alpha__
#undef vtophys
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
#endif

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/*
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* Pseudo-driver for media selection on the Lite-On PNIC 82c168
* chip. The NWAY support on this chip is horribly broken, so we
* only support manual mode selection. This is lame, but getting
* NWAY to work right is amazingly difficult.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/socket.h>
#include <sys/errno.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/if_media.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include <dev/mii/miidevs.h>
#include <machine/clock.h>
#include <machine/bus_pio.h>
#include <machine/bus_memio.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/bus.h>
#include <pci/if_dcreg.h>
#include "miibus_if.h"
#if !defined(lint)
static const char rcsid[] =
"$FreeBSD$";
#endif
#define DC_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) | x)
#define DC_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) & ~x)
static int pnphy_probe __P((device_t));
static int pnphy_attach __P((device_t));
static int pnphy_detach __P((device_t));
static device_method_t pnphy_methods[] = {
/* device interface */
DEVMETHOD(device_probe, pnphy_probe),
DEVMETHOD(device_attach, pnphy_attach),
DEVMETHOD(device_detach, pnphy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};
static devclass_t pnphy_devclass;
static driver_t pnphy_driver = {
"pnphy",
pnphy_methods,
sizeof(struct mii_softc)
};
DRIVER_MODULE(pnphy, miibus, pnphy_driver, pnphy_devclass, 0, 0);
int pnphy_service __P((struct mii_softc *, struct mii_data *, int));
void pnphy_status __P((struct mii_softc *));
static int pnphy_probe(dev)
device_t dev;
{
struct mii_attach_args *ma;
ma = device_get_ivars(dev);
/*
* The dc driver will report the 82c168 vendor and device
* ID to let us know that it wants us to attach.
*/
if (ma->mii_id1 != DC_VENDORID_LO ||
ma->mii_id2 != DC_DEVICEID_82C168)
return(ENXIO);
device_set_desc(dev, "PNIC 82c168 media interface");
return (0);
}
static int pnphy_attach(dev)
device_t dev;
{
struct mii_softc *sc;
struct mii_attach_args *ma;
struct mii_data *mii;
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
mii = device_get_softc(sc->mii_dev);
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = pnphy_service;
sc->mii_pdata = mii;
sc->mii_flags |= MIIF_NOISOLATE;
mii->mii_instance++;
#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
sc->mii_capabilities =
BMSR_100TXFDX|BMSR_100TXHDX|BMSR_10TFDX|BMSR_10THDX;
sc->mii_capabilities &= ma->mii_capmask;
device_printf(dev, " ");
if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0)
printf("no media present");
else
mii_add_media(mii, sc->mii_capabilities, sc->mii_inst);
printf("\n");
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
BMCR_ISO);
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
BMCR_LOOP|BMCR_S100);
#undef ADD
MIIBUS_MEDIAINIT(sc->mii_dev);
return(0);
}
static int pnphy_detach(dev)
device_t dev;
{
struct mii_softc *sc;
struct mii_data *mii;
sc = device_get_softc(dev);
mii = device_get_softc(device_get_parent(dev));
sc->mii_dev = NULL;
LIST_REMOVE(sc, mii_list);
return(0);
}
int
pnphy_service(sc, mii, cmd)
struct mii_softc *sc;
struct mii_data *mii;
int cmd;
{
struct dc_softc *dc_sc;
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
dc_sc = mii->mii_ifp->if_softc;
switch (cmd) {
case MII_POLLSTAT:
/*
* If we're not polling our PHY instance, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
return (0);
}
break;
case MII_MEDIACHG:
/*
* If the media indicates a different PHY instance,
* isolate ourselves.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
/*
* If the interface is not up, don't do anything.
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
sc->mii_flags = 0;
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_AUTO:
/* NWAY is busted on this chip */
case IFM_100_T4:
/*
* XXX Not supported as a manual setting right now.
*/
return (EINVAL);
case IFM_100_TX:
mii->mii_media_active = IFM_ETHER|IFM_100_TX;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mii->mii_media_active |= IFM_FDX;
MIIBUS_STATCHG(sc->mii_dev);
return(0);
break;
case IFM_10_T:
mii->mii_media_active = IFM_ETHER|IFM_10_T;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mii->mii_media_active |= IFM_FDX;
MIIBUS_STATCHG(sc->mii_dev);
return(0);
break;
default:
return(EINVAL);
break;
}
break;
case MII_TICK:
/*
* If we're not currently selected, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
/*
* Only used for autonegotiation.
*/
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
return (0);
/*
* Is the interface even up?
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
return (0);
return(0);
}
/* Update the media status. */
pnphy_status(sc);
/* Callback if something changed. */
if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
MIIBUS_STATCHG(sc->mii_dev);
sc->mii_active = mii->mii_media_active;
}
return (0);
}
void
pnphy_status(sc)
struct mii_softc *sc;
{
struct mii_data *mii = sc->mii_pdata;
int reg;
struct dc_softc *dc_sc;
dc_sc = mii->mii_ifp->if_softc;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
reg = CSR_READ_4(dc_sc, DC_ISR);
if (!(reg & DC_ISR_LINKFAIL))
mii->mii_media_status |= IFM_ACTIVE;
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_100_TX;
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
mii->mii_media_active |= IFM_FDX;
return;
}

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/*
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* Pseudo-driver for internal NWAY support on DEC 21143 and workalike
* controllers. Technically we're abusing the miibus code to handle
* media selection and NWAY support here since there is no MII
* interface. However the logical operations are roughly the same,
* and the alternative is to create a fake MII interface in the driver,
* which is harder to do.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/socket.h>
#include <sys/errno.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/if_media.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include <dev/mii/miidevs.h>
#include <machine/clock.h>
#include <machine/bus_pio.h>
#include <machine/bus_memio.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/bus.h>
#include <pci/pcivar.h>
#include <pci/if_dcreg.h>
#include "miibus_if.h"
#if !defined(lint)
static const char rcsid[] =
"$FreeBSD$";
#endif
#define DC_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) | x)
#define DC_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) & ~x)
#define MIIF_AUTOTIMEOUT 0x0004
static int dcphy_probe __P((device_t));
static int dcphy_attach __P((device_t));
static int dcphy_detach __P((device_t));
static device_method_t dcphy_methods[] = {
/* device interface */
DEVMETHOD(device_probe, dcphy_probe),
DEVMETHOD(device_attach, dcphy_attach),
DEVMETHOD(device_detach, dcphy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};
static devclass_t dcphy_devclass;
static driver_t dcphy_driver = {
"dcphy",
dcphy_methods,
sizeof(struct mii_softc)
};
DRIVER_MODULE(dcphy, miibus, dcphy_driver, dcphy_devclass, 0, 0);
int dcphy_service __P((struct mii_softc *, struct mii_data *, int));
void dcphy_status __P((struct mii_softc *));
static int dcphy_auto __P((struct mii_softc *, int));
static void dcphy_reset __P((struct mii_softc *));
static int dcphy_probe(dev)
device_t dev;
{
struct mii_attach_args *ma;
ma = device_get_ivars(dev);
/*
* The dc driver will report the 21143 vendor and device
* ID to let us know that it wants us to attach.
*/
if (ma->mii_id1 != DC_VENDORID_DEC ||
ma->mii_id2 != DC_DEVICEID_21143)
return(ENXIO);
device_set_desc(dev, "Intel 21143 NWAY media interface");
return (0);
}
static int dcphy_attach(dev)
device_t dev;
{
struct mii_softc *sc;
struct mii_attach_args *ma;
struct mii_data *mii;
struct dc_softc *dc_sc;
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
mii = device_get_softc(sc->mii_dev);
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = dcphy_service;
sc->mii_pdata = mii;
sc->mii_flags |= MIIF_NOISOLATE;
mii->mii_instance++;
#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
BMCR_ISO);
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
BMCR_LOOP|BMCR_S100);
/*dcphy_reset(sc);*/
dc_sc = mii->mii_ifp->if_softc;
CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0);
CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0);
switch(pci_read_config(device_get_parent(sc->mii_dev),
DC_PCI_CSID, 4)) {
case 0x99999999:
/* Example of how to only allow 10Mbps modes. */
sc->mii_capabilities = BMSR_10TFDX|BMSR_10THDX;
break;
default:
sc->mii_capabilities =
BMSR_ANEG|BMSR_100TXFDX|BMSR_100TXHDX|
BMSR_10TFDX|BMSR_10THDX;
break;
}
sc->mii_capabilities &= ma->mii_capmask;
device_printf(dev, " ");
if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0)
printf("no media present");
else
mii_add_media(mii, sc->mii_capabilities, sc->mii_inst);
printf("\n");
#undef ADD
MIIBUS_MEDIAINIT(sc->mii_dev);
return(0);
}
static int dcphy_detach(dev)
device_t dev;
{
struct mii_softc *sc;
struct mii_data *mii;
sc = device_get_softc(dev);
mii = device_get_softc(device_get_parent(dev));
sc->mii_dev = NULL;
LIST_REMOVE(sc, mii_list);
return(0);
}
int
dcphy_service(sc, mii, cmd)
struct mii_softc *sc;
struct mii_data *mii;
int cmd;
{
struct dc_softc *dc_sc;
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int reg;
u_int32_t mode;
dc_sc = mii->mii_ifp->if_softc;
switch (cmd) {
case MII_POLLSTAT:
/*
* If we're not polling our PHY instance, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
return (0);
}
break;
case MII_MEDIACHG:
/*
* If the media indicates a different PHY instance,
* isolate ourselves.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
return (0);
}
/*
* If the interface is not up, don't do anything.
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
sc->mii_flags = 0;
mii->mii_media_active = IFM_NONE;
mode = CSR_READ_4(dc_sc, DC_NETCFG);
mode &= ~(DC_NETCFG_FULLDUPLEX|DC_NETCFG_PORTSEL|
DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER|DC_NETCFG_SPEEDSEL);
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_AUTO:
/*dcphy_reset(sc);*/
(void) dcphy_auto(sc, 0);
break;
case IFM_100_T4:
/*
* XXX Not supported as a manual setting right now.
*/
return (EINVAL);
case IFM_100_TX:
dcphy_reset(sc);
DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
mode |= DC_NETCFG_PORTSEL|DC_NETCFG_PCS|
DC_NETCFG_SCRAMBLER;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mode |= DC_NETCFG_FULLDUPLEX;
else
mode &= ~DC_NETCFG_FULLDUPLEX;
CSR_WRITE_4(dc_sc, DC_NETCFG, mode);
break;
case IFM_10_T:
DC_CLRBIT(dc_sc, DC_SIARESET, DC_SIA_RESET);
DC_CLRBIT(dc_sc, DC_10BTCTRL, 0xFFFF);
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3D);
else
DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3F);
DC_SETBIT(dc_sc, DC_SIARESET, DC_SIA_RESET);
DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
mode &= ~DC_NETCFG_PORTSEL;
mode |= DC_NETCFG_SPEEDSEL;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mode |= DC_NETCFG_FULLDUPLEX;
else
mode &= ~DC_NETCFG_FULLDUPLEX;
CSR_WRITE_4(dc_sc, DC_NETCFG, mode);
break;
default:
return(EINVAL);
break;
}
break;
case MII_TICK:
/*
* If we're not currently selected, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
/*
* Only used for autonegotiation.
*/
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
return (0);
/*
* Is the interface even up?
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
return (0);
if (sc->mii_flags & MIIF_DOINGAUTO) {
if (++sc->mii_ticks != 5)
return(0);
else {
sc->mii_ticks = 0;
sc->mii_flags &= ~MIIF_DOINGAUTO;
sc->mii_flags |= MIIF_AUTOTIMEOUT;
}
}
sc->mii_flags &= ~MIIF_DOINGAUTO;
/*
* Check to see if we have link. If we do, we don't
* need to restart the autonegotiation process. Read
* the BMSR twice in case it's latched.
*/
reg = CSR_READ_4(dc_sc, DC_10BTSTAT) &
(DC_TSTAT_LS10|DC_TSTAT_LS100);
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX &&
!(reg & DC_TSTAT_LS100)) {
if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
break;
} else
return(0);
} else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T &&
!(reg & DC_TSTAT_LS10)) {
if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
break;
} else
return(0);
} else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE &&
(!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))) {
if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
break;
} else
return(0);
} else if (CSR_READ_4(dc_sc, DC_ISR) & DC_ISR_LINKGOOD) {
if (sc->mii_flags & MIIF_AUTOTIMEOUT) {
sc->mii_flags &= ~MIIF_AUTOTIMEOUT;
break;
} else
return(0);
}
sc->mii_ticks = 0;
/*dcphy_reset(sc);*/
dcphy_auto(sc, 0);
break;
}
/* Update the media status. */
dcphy_status(sc);
/* Callback if something changed. */
if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
MIIBUS_STATCHG(sc->mii_dev);
sc->mii_active = mii->mii_media_active;
}
return (0);
}
void
dcphy_status(sc)
struct mii_softc *sc;
{
struct mii_data *mii = sc->mii_pdata;
int reg, anlpar;
struct dc_softc *dc_sc;
dc_sc = mii->mii_ifp->if_softc;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
reg = CSR_READ_4(dc_sc, DC_10BTSTAT) &
(DC_TSTAT_LS10|DC_TSTAT_LS100);
if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
mii->mii_media_status |= IFM_ACTIVE;
if (sc->mii_flags & MIIF_DOINGAUTO) {
mii->mii_media_active |= IFM_NONE;
return;
}
if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL &&
CSR_READ_4(dc_sc, DC_10BTSTAT) & DC_TSTAT_ANEGSTAT) {
/* Erg, still trying, I guess... */
if ((CSR_READ_4(dc_sc, DC_10BTSTAT) &
DC_ASTAT_AUTONEGCMP) != DC_ASTAT_AUTONEGCMP) {
mii->mii_media_active |= IFM_NONE;
return;
}
if (CSR_READ_4(dc_sc, DC_10BTSTAT) & DC_TSTAT_LP_CAN_NWAY) {
anlpar = CSR_READ_4(dc_sc, DC_10BTSTAT) >> 16;
if (anlpar & ANLPAR_T4)
mii->mii_media_active |= IFM_100_T4;
else if (anlpar & ANLPAR_TX_FD)
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
else if (anlpar & ANLPAR_TX)
mii->mii_media_active |= IFM_100_TX;
else if (anlpar & ANLPAR_10_FD)
mii->mii_media_active |= IFM_10_T|IFM_FDX;
else if (anlpar & ANLPAR_10)
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_NONE;
if (DC_IS_INTEL(dc_sc))
DC_CLRBIT(dc_sc, DC_10BTCTRL,
DC_TCTL_AUTONEGENBL);
return;
}
/*
* If the other side doesn't support NWAY, then the
* best we can do is determine if we have a 10Mbps or
* 100Mbps link. There's no way to know if the link
* is full or half duplex, so we default to half duplex
* and hope that the user is clever enough to manually
* change the media settings if we're wrong.
*/
if (!(reg & DC_TSTAT_LS100))
mii->mii_media_active |= IFM_100_TX;
else if (!(reg & DC_TSTAT_LS10))
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_NONE;
if (DC_IS_INTEL(dc_sc))
DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
return;
}
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SCRAMBLER)
mii->mii_media_active |= IFM_100_TX;
else
mii->mii_media_active |= IFM_10_T;
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
mii->mii_media_active |= IFM_FDX;
return;
}
static int
dcphy_auto(mii, waitfor)
struct mii_softc *mii;
int waitfor;
{
int i;
struct dc_softc *sc;
sc = mii->mii_pdata->mii_ifp->if_softc;
if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF);
DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
DC_SETBIT(sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
DC_SETBIT(sc, DC_10BTSTAT, DC_ASTAT_TXDISABLE);
}
if (waitfor) {
/* Wait 500ms for it to complete. */
for (i = 0; i < 500; i++) {
if ((CSR_READ_4(sc, DC_10BTSTAT) & DC_TSTAT_ANEGSTAT)
== DC_ASTAT_AUTONEGCMP)
return(0);
DELAY(1000);
}
/*
* Don't need to worry about clearing MIIF_DOINGAUTO.
* If that's set, a timeout is pending, and it will
* clear the flag.
*/
return(EIO);
}
/*
* Just let it finish asynchronously. This is for the benefit of
* the tick handler driving autonegotiation. Don't want 500ms
* delays all the time while the system is running!
*/
if ((mii->mii_flags & MIIF_DOINGAUTO) == 0)
mii->mii_flags |= MIIF_DOINGAUTO;
return(EJUSTRETURN);
}
static void
dcphy_reset(mii)
struct mii_softc *mii;
{
struct dc_softc *sc;
sc = mii->mii_pdata->mii_ifp->if_softc;
DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
DELAY(1000);
DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
return;
}

311
sys/dev/mii/pnphy.c Normal file
View File

@ -0,0 +1,311 @@
/*
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* Pseudo-driver for media selection on the Lite-On PNIC 82c168
* chip. The NWAY support on this chip is horribly broken, so we
* only support manual mode selection. This is lame, but getting
* NWAY to work right is amazingly difficult.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/socket.h>
#include <sys/errno.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/if_media.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include <dev/mii/miidevs.h>
#include <machine/clock.h>
#include <machine/bus_pio.h>
#include <machine/bus_memio.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/bus.h>
#include <pci/if_dcreg.h>
#include "miibus_if.h"
#if !defined(lint)
static const char rcsid[] =
"$FreeBSD$";
#endif
#define DC_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) | x)
#define DC_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) & ~x)
static int pnphy_probe __P((device_t));
static int pnphy_attach __P((device_t));
static int pnphy_detach __P((device_t));
static device_method_t pnphy_methods[] = {
/* device interface */
DEVMETHOD(device_probe, pnphy_probe),
DEVMETHOD(device_attach, pnphy_attach),
DEVMETHOD(device_detach, pnphy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{ 0, 0 }
};
static devclass_t pnphy_devclass;
static driver_t pnphy_driver = {
"pnphy",
pnphy_methods,
sizeof(struct mii_softc)
};
DRIVER_MODULE(pnphy, miibus, pnphy_driver, pnphy_devclass, 0, 0);
int pnphy_service __P((struct mii_softc *, struct mii_data *, int));
void pnphy_status __P((struct mii_softc *));
static int pnphy_probe(dev)
device_t dev;
{
struct mii_attach_args *ma;
ma = device_get_ivars(dev);
/*
* The dc driver will report the 82c168 vendor and device
* ID to let us know that it wants us to attach.
*/
if (ma->mii_id1 != DC_VENDORID_LO ||
ma->mii_id2 != DC_DEVICEID_82C168)
return(ENXIO);
device_set_desc(dev, "PNIC 82c168 media interface");
return (0);
}
static int pnphy_attach(dev)
device_t dev;
{
struct mii_softc *sc;
struct mii_attach_args *ma;
struct mii_data *mii;
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
mii = device_get_softc(sc->mii_dev);
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = pnphy_service;
sc->mii_pdata = mii;
sc->mii_flags |= MIIF_NOISOLATE;
mii->mii_instance++;
#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
sc->mii_capabilities =
BMSR_100TXFDX|BMSR_100TXHDX|BMSR_10TFDX|BMSR_10THDX;
sc->mii_capabilities &= ma->mii_capmask;
device_printf(dev, " ");
if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0)
printf("no media present");
else
mii_add_media(mii, sc->mii_capabilities, sc->mii_inst);
printf("\n");
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
BMCR_ISO);
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
BMCR_LOOP|BMCR_S100);
#undef ADD
MIIBUS_MEDIAINIT(sc->mii_dev);
return(0);
}
static int pnphy_detach(dev)
device_t dev;
{
struct mii_softc *sc;
struct mii_data *mii;
sc = device_get_softc(dev);
mii = device_get_softc(device_get_parent(dev));
sc->mii_dev = NULL;
LIST_REMOVE(sc, mii_list);
return(0);
}
int
pnphy_service(sc, mii, cmd)
struct mii_softc *sc;
struct mii_data *mii;
int cmd;
{
struct dc_softc *dc_sc;
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
dc_sc = mii->mii_ifp->if_softc;
switch (cmd) {
case MII_POLLSTAT:
/*
* If we're not polling our PHY instance, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
return (0);
}
break;
case MII_MEDIACHG:
/*
* If the media indicates a different PHY instance,
* isolate ourselves.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
/*
* If the interface is not up, don't do anything.
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
sc->mii_flags = 0;
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_AUTO:
/* NWAY is busted on this chip */
case IFM_100_T4:
/*
* XXX Not supported as a manual setting right now.
*/
return (EINVAL);
case IFM_100_TX:
mii->mii_media_active = IFM_ETHER|IFM_100_TX;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mii->mii_media_active |= IFM_FDX;
MIIBUS_STATCHG(sc->mii_dev);
return(0);
break;
case IFM_10_T:
mii->mii_media_active = IFM_ETHER|IFM_10_T;
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
mii->mii_media_active |= IFM_FDX;
MIIBUS_STATCHG(sc->mii_dev);
return(0);
break;
default:
return(EINVAL);
break;
}
break;
case MII_TICK:
/*
* If we're not currently selected, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
/*
* Only used for autonegotiation.
*/
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
return (0);
/*
* Is the interface even up?
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
return (0);
return(0);
}
/* Update the media status. */
pnphy_status(sc);
/* Callback if something changed. */
if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
MIIBUS_STATCHG(sc->mii_dev);
sc->mii_active = mii->mii_media_active;
}
return (0);
}
void
pnphy_status(sc)
struct mii_softc *sc;
{
struct mii_data *mii = sc->mii_pdata;
int reg;
struct dc_softc *dc_sc;
dc_sc = mii->mii_ifp->if_softc;
mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;
reg = CSR_READ_4(dc_sc, DC_ISR);
if (!(reg & DC_ISR_LINKFAIL))
mii->mii_media_status |= IFM_ACTIVE;
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_100_TX;
if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
mii->mii_media_active |= IFM_FDX;
return;
}

6
sys/i386/conf/GENERIC
View File

@ -175,18 +175,14 @@ device ppi0 # Parallel port interface device
# PCI Ethernet NICs.
device ax0 # ASIX AX88140A
device de0 # DEC/Intel DC21x4x (``Tulip'')
device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
device pn0 # Lite-On 82c168/82c169 (``PNIC'')
device tx0 # SMC 9432TX (83c170 ``EPIC'')
device vx0 # 3Com 3c590, 3c595 (``Vortex'')
# PCI Ethernet NICs that use the common MII bus controller code.
controller miibus0 # MII bus support
device al0 # ADMtek AL981/AN985 (``Comet''/``Centaur'')
device dm0 # Davicom DM9100/DM9102
device mx0 # Macronix 98713/98715/98725 (``PMAC'')
device dc0 # DEC/Intel 21143 and various workalikes
device rl0 # RealTek 8129/8139
device sf0 # Adaptec AIC-6915 (``Starfire'')
device sis0 # Silicon Integrated Systems SiS 900/SiS 7016

31
sys/i386/conf/LINT
View File

@ -1646,31 +1646,20 @@ controller miibus0
# nd 1040B PCI SCSI host adapters, as well as the Qlogic ISP 2100
# FC/AL Host Adapter.
#
# The `al' device provides support for PCI fast ethernet adapters
# based on the ADMtek Inc. AL981 "Comet" and the AN985 "Centaur" chips.
#
# The `ax' device provides support for PCI fast ethernet adapters
# based on the ASIX Electronics AX88140A chip, including the Alfa
# Inc. GFC2204.
# The `dc' device provides support for PCI fast ethernet adapters
# based on the DEC/Intel 21143 and various workalikes including:
# the ADMtek AL981 Comet and AN985 Centaur, the ASIX Electronics
# AX88140A and AX88141, the Davicom DM9100 and DM9102, the Lite-On
# 82c168 and 82c169 PNIC, the Lite-On/Macronix LC82C115 PNIC II
# and the Macronix 98713/98713A/98715/98715A/98725 PMAC. This driver
# replaces the old al, ax, dm, pn and mx drivers.
#
# The `de' device provides support for the Digital Equipment DC21040
# self-contained Ethernet adapter.
#
# The `dm' device provides support for PCI fast ethernet adapters
# based on the the Davicom DM9100 and DM9102 controller chips, including
# the Jaton Corporation XPressNet.
#
# The `fxp' device provides support for the Intel EtherExpress Pro/100B
# PCI Fast Ethernet adapters.
#
# The `mx' device provides support for various fast ethernet adapters
# based on the Macronix 98713, 987615 and 98725 series chips.
#
# The `pn' device provides support for various fast ethernet adapters
# based on the Lite-On 82c168 and 82c169 PNIC chips, including the
# LinkSys LNE100TX, the NetGear FA310TX rev. D1 and the Matrox
# FastNIC 10/100.
#
# The 'rl' device provides support for PCI fast ethernet adapters based
# on the RealTek 8129/8139 chipset. Note that the RealTek driver defaults
# to using programmed I/O to do register accesses because memory mapped
@ -1852,13 +1841,9 @@ options SCSI_ISP_WWN="0x5000000099990000"
#options ISP_COMPILE_2100_FW=1
#options ISP_COMPILE_2200_FW=1
device al0
device ax0
device dc0
device de0
device dm0
device fxp0
device mx0
device pn0
device rl0
device sf0
device sis0

6
sys/i386/conf/NEWCARD
View File

@ -169,13 +169,9 @@ device ppi0 # Parallel port interface device
controller miibus0
# PCI Ethernet NICs.
device al0 # ADMtek AL981 (``Comet'')
device ax0 # ASIX AX88140A
device de0 # DEC/Intel DC21x4x (``Tulip'')
device dm0 # Davicom DM9100/DM9102
device dc0 # DEC/Intel 21143 and various workalikes
device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
device mx0 # Macronix 98713/98715/98725 (``PMAC'')
device pn0 # Lite-On 82c168/82c169 (``PNIC'')
device rl0 # RealTek 8129/8139
device sf0 # Adaptec AIC-6915 (``Starfire'')
device sis0 # Silicon Integrated Systems SiS 900/SiS 7016

31
sys/i386/conf/NOTES
View File

@ -1646,31 +1646,20 @@ controller miibus0
# nd 1040B PCI SCSI host adapters, as well as the Qlogic ISP 2100
# FC/AL Host Adapter.
#
# The `al' device provides support for PCI fast ethernet adapters
# based on the ADMtek Inc. AL981 "Comet" and the AN985 "Centaur" chips.
#
# The `ax' device provides support for PCI fast ethernet adapters
# based on the ASIX Electronics AX88140A chip, including the Alfa
# Inc. GFC2204.
# The `dc' device provides support for PCI fast ethernet adapters
# based on the DEC/Intel 21143 and various workalikes including:
# the ADMtek AL981 Comet and AN985 Centaur, the ASIX Electronics
# AX88140A and AX88141, the Davicom DM9100 and DM9102, the Lite-On
# 82c168 and 82c169 PNIC, the Lite-On/Macronix LC82C115 PNIC II
# and the Macronix 98713/98713A/98715/98715A/98725 PMAC. This driver
# replaces the old al, ax, dm, pn and mx drivers.
#
# The `de' device provides support for the Digital Equipment DC21040
# self-contained Ethernet adapter.
#
# The `dm' device provides support for PCI fast ethernet adapters
# based on the the Davicom DM9100 and DM9102 controller chips, including
# the Jaton Corporation XPressNet.
#
# The `fxp' device provides support for the Intel EtherExpress Pro/100B
# PCI Fast Ethernet adapters.
#
# The `mx' device provides support for various fast ethernet adapters
# based on the Macronix 98713, 987615 and 98725 series chips.
#
# The `pn' device provides support for various fast ethernet adapters
# based on the Lite-On 82c168 and 82c169 PNIC chips, including the
# LinkSys LNE100TX, the NetGear FA310TX rev. D1 and the Matrox
# FastNIC 10/100.
#
# The 'rl' device provides support for PCI fast ethernet adapters based
# on the RealTek 8129/8139 chipset. Note that the RealTek driver defaults
# to using programmed I/O to do register accesses because memory mapped
@ -1852,13 +1841,9 @@ options SCSI_ISP_WWN="0x5000000099990000"
#options ISP_COMPILE_2100_FW=1
#options ISP_COMPILE_2200_FW=1
device al0
device ax0
device dc0
device de0
device dm0
device fxp0
device mx0
device pn0
device rl0
device sf0
device sis0

6
sys/i386/conf/PCCARD
View File

@ -159,18 +159,14 @@ device ppi0 # Parallel port interface device
# PCI Ethernet NICs.
device ax0 # ASIX AX88140A
device de0 # DEC/Intel DC21x4x (``Tulip'')
device fxp0 # Intel EtherExpress PRO/100B (82557, 82558)
device pn0 # Lite-On 82c168/82c169 (``PNIC'')
device tx0 # SMC 9432TX (83c170 ``EPIC'')
device vx0 # 3Com 3c590, 3c595 (``Vortex'')
# PCI Ethernet NICs that use the common MII bus controller code.
controller miibus0 # MII bus support
device al0 # ADMtek AL981/AN985 (``Comet''/``Centaur'')
device dm0 # Davicom DM9100/DM9102
device mx0 # Macronix 98713/98715/98725 (``PMAC'')
device dc0 # DEC/Intrl 21143 and various workalikes
device rl0 # RealTek 8129/8139
device sf0 # Adaptec AIC-6915 (``Starfire'')
device sis0 # Silicon Integrated Systems SiS 900/SiS 7016

6
sys/i386/i386/userconfig.c
View File

@ -401,14 +401,10 @@ static DEV_INFO device_info[] = {
{"xe", "Xircom PC Card Ethernet adapter", 0, CLS_NETWORK},
{"ze", "IBM/National Semiconductor PCMCIA Ethernet adapter",0, CLS_NETWORK},
{"zp", "3COM PCMCIA Etherlink III Ethernet adapter", 0, CLS_NETWORK},
{"al", "ADMtek AL981/AN985 ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"ax", "ASIX AX88140A ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"dc", "DEC/Intel 21143 or clone Ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"de", "DEC DC21040 Ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"dm", "Davicom DM910x Ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"fpa", "DEC DEFPA PCI FDDI adapter", FLG_FIXED, CLS_NETWORK},
{"rl", "RealTek 8129/8139 ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"mx", "Macronix PMAC ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"pn", "Lite-On 82c168/82c169 PNIC adapter", FLG_FIXED, CLS_NETWORK},
{"tl", "Texas Instruments ThunderLAN ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"vr", "VIA Rhine/Rhine II ethernet adapter", FLG_FIXED, CLS_NETWORK},
{"wb", "Winbond W89C840F ethernet adapter", FLG_FIXED, CLS_NETWORK},

6
sys/modules/Makefile
View File

@ -2,9 +2,9 @@
# XXX present but broken: atapi ip_mroute_mod joy pcic
SUBDIR= aha al ax ccd cd9660 coda dm fdesc fxp if_disc if_ppp if_sl if_tun \
ipfilter ipfw kernfs md mfs mii msdos mx netgraph nfs ntfs nullfs \
pn portal procfs rl sf sis sk ste ti tl umapfs union vn vr wb xl
SUBDIR= aha ccd dc cd9660 coda fdesc fxp if_disc if_ppp if_sl if_tun \
ipfilter ipfw kernfs md mfs mii msdos netgraph nfs ntfs nullfs \
portal procfs rl sf sis sk ste ti tl umapfs union vn vr wb xl
SUBDIR+=usb ugen uhid ukbd ulpt ums umodem umass

8
sys/modules/ax/Makefile
View File

@ -1,8 +0,0 @@
# $FreeBSD$
.PATH: ${.CURDIR}/../../pci
KMOD = if_ax
SRCS = if_ax.c opt_bdg.h device_if.h bus_if.h pci_if.h
CFLAGS += ${DEBUG_FLAGS}
.include <bsd.kmod.mk>

4
sys/modules/al/Makefile → sys/modules/dc/Makefile
View File

@ -1,8 +1,8 @@
# $FreeBSD$
.PATH: ${.CURDIR}/../../pci
KMOD = al
SRCS = if_al.c opt_bdg.h device_if.h bus_if.h pci_if.h
KMOD = if_dc
SRCS = if_dc.c opt_bdg.h device_if.h bus_if.h pci_if.h
SRCS += miibus_if.h
CFLAGS += ${DEBUG_FLAGS}
KMODDEPS = miibus

10
sys/modules/dm/Makefile
View File

@ -1,10 +0,0 @@
# $FreeBSD$
.PATH: ${.CURDIR}/../../pci
KMOD = if_dm
SRCS = if_dm.c opt_bdg.h device_if.h bus_if.h pci_if.h
SRCS += miibus_if.h
CFLAGS += ${DEBUG_FLAGS}
KMODDEPS = miibus
.include <bsd.kmod.mk>

2
sys/modules/mii/Makefile
View File

@ -4,7 +4,7 @@
KMOD = miibus
SRCS = mii.c mii_physubr.c ukphy.c ukphy_subr.c bus_if.h
SRCS += miibus_if.h device_if.h miibus_if.c exphy.c nsphy.c
SRCS += mlphy.c tlphy.c rlphy.c amphy.c mxphy.c
SRCS += mlphy.c tlphy.c rlphy.c amphy.c dcphy.c pnphy.c
CFLAGS += ${DEBUG_FLAGS}
.include <bsd.kmod.mk>

8
sys/modules/mx/Makefile
View File

@ -1,8 +0,0 @@
# $FreeBSD$
.PATH: ${.CURDIR}/../../pci
KMOD = if_mx
SRCS = if_mx.c opt_bdg.h device_if.h bus_if.h pci_if.h miibus_if.h
CFLAGS += ${DEBUG_FLAGS}
.include <bsd.kmod.mk>

8
sys/modules/pn/Makefile
View File

@ -1,8 +0,0 @@
# $FreeBSD$
.PATH: ${.CURDIR}/../../pci
KMOD = if_pn
SRCS = if_pn.c opt_bdg.h device_if.h bus_if.h pci_if.h
CFLAGS += ${DEBUG_FLAGS}
.include <bsd.kmod.mk>

1762
sys/pci/if_al.c
View File

File diff suppressed because it is too large Load Diff

553
sys/pci/if_alreg.h
View File

@ -1,553 +0,0 @@
/*
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* COMET register definitions.
*/
#define AL_BUSCTL 0x00 /* bus control */
#define AL_TXSTART 0x08 /* tx start demand */
#define AL_RXSTART 0x10 /* rx start demand */
#define AL_RXADDR 0x18 /* rx descriptor list start addr */
#define AL_TXADDR 0x20 /* tx descriptor list start addr */
#define AL_ISR 0x28 /* interrupt status register */
#define AL_NETCFG 0x30 /* network config register */
#define AL_IMR 0x38 /* interrupt mask */
#define AL_FRAMESDISCARDED 0x40 /* # of discarded frames */
#define AL_SIO 0x48 /* MII and ROM/EEPROM access */
#define AL_RESERVED 0x50
#define AL_GENTIMER 0x58 /* general timer */
#define AL_GENPORT 0x60 /* general purpose port */
#define AL_WAKEUP_CTL 0x68 /* wake-up control/status register */
#define AL_WAKEUP_PAT 0x70 /* wake-up pattern data register */
#define AL_WATCHDOG 0x78 /* watchdog timer */
#define AL_ISR2 0x80 /* ISR assist register */
#define AL_IMR2 0x84 /* IRM assist register */
#define AL_COMMAND 0x88 /* command register */
#define AL_PCIPERF 0x8C /* pci perf counter */
#define AL_PWRMGMT 0x90 /* pwr management command/status */
#define AL_TXBURST 0x9C /* tx burst counter/timeout */
#define AL_FLASHPROM 0xA0 /* flash(boot) PROM port */
#define AL_PAR0 0xA4 /* station address */
#define AL_PAR1 0xA8 /* station address */
#define AL_MAR0 0xAC /* multicast hash filter */
#define AL_MAR1 0xB0 /* multicast hash filter */
#define AL_BMCR 0xB4 /* built in PHY control */
#define AL_BMSR 0xB8 /* built in PHY status */
#define AL_VENID 0xBC /* built in PHY ID0 */
#define AL_DEVID 0xC0 /* built in PHY ID1 */
#define AL_ANAR 0xC4 /* built in PHY autoneg advert */
#define AL_LPAR 0xC8 /* bnilt in PHY link part. ability */
#define AL_ANER 0xCC /* built in PHY autoneg expansion */
#define AL_PHY_MODECTL 0xD0 /* mode control */
#define AL_PHY_CONFIG 0xD4 /* config info and inter status */
#define AL_PHY_INTEN 0xD8 /* interrupto enable */
#define AL_PHY_MODECTL_100TX 0xDC /* 100baseTX control/status */
/*
* Bus control bits.
*/
#define AL_BUSCTL_RESET 0x00000001
#define AL_BUSCTL_ARBITRATION 0x00000002
#define AL_BUSCTL_SKIPLEN 0x0000007C
#define AL_BUSCTL_BIGENDIAN 0x00000080
#define AL_BUSCTL_BURSTLEN 0x00003F00
#define AL_BUSCTL_CACHEALIGN 0x0000C000
#define AL_BUSCTL_XMITPOLL 0x00060000
#define AL_BUSCTL_BUF_BIGENDIAN 0x00100000
#define AL_BUSCTL_READMULTI 0x00200000
#define AL_BUSCTL_READLINE 0x00800000
#define AL_BUSCTL_WRITEINVAL 0x01000000
#define AL_SKIPLEN_1LONG 0x00000004
#define AL_SKIPLEN_2LONG 0x00000008
#define AL_SKIPLEN_3LONG 0x00000010
#define AL_SKIPLEN_4LONG 0x00000020
#define AL_SKIPLEN_5LONG 0x00000040
#define AL_BURSTLEN_UNLIMIT 0x00000000
#define AL_BURSTLEN_1LONG 0x00000100
#define AL_BURSTLEN_2LONG 0x00000200
#define AL_BURSTLEN_4LONG 0x00000400
#define AL_BURSTLEN_8LONG 0x00000800
#define AL_BURSTLEN_16LONG 0x00001000
#define AL_BURSTLEN_32LONG 0x00002000
#define AL_CACHEALIGN_NONE 0x00000000
#define AL_CACHEALIGN_8LONG 0x00004000
#define AL_CACHEALIGN_16LONG 0x00008000
#define AL_CACHEALIGN_32LONG 0x0000C000
#define AL_TXPOLL_OFF 0x00000000
#define AL_TXPOLL_200U 0x00020000
#define AX_TXPOLL_800U 0x00040000
#define AL_TXPOLL_1600U 0x00060000
/*
* Interrupt status bits.
*/
#define AL_ISR_TX_OK 0x00000001
#define AL_ISR_TX_IDLE 0x00000002
#define AL_ISR_TX_NOBUF 0x00000004
#define AL_ISR_TX_JABBERTIMEO 0x00000008
#define AL_ISR_TX_UNDERRUN 0x00000020
#define AL_ISR_RX_OK 0x00000040
#define AL_ISR_RX_NOBUF 0x00000080
#define AL_ISR_RX_IDLE 0x00000100
#define AL_ISR_RX_WATDOGTIMEO 0x00000200
#define AL_ISR_TIMER_EXPIRED 0x00000800
#define AL_ISR_BUS_ERR 0x00002000
#define AL_ISR_ABNORMAL 0x00008000
#define AL_ISR_NORMAL 0x00010000
#define AL_ISR_RX_STATE 0x000E0000
#define AL_ISR_TX_STATE 0x00700000
#define AL_ISR_BUSERRTYPE 0x03800000
#define AL_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
#define AL_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
#define AL_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
#define AL_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
#define AL_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
#define AL_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
#define AL_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
#define AL_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
#define AL_TXSTATE_RESET 0x00000000 /* 000 - reset */
#define AL_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
#define AL_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
#define AL_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
#define AL_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
#define AL_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
#define AL_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
#define AL_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
/*
* Network config bits.
*/
#define AL_NETCFG_RX_ON 0x00000002
#define AL_NETCFG_RX_BADFRAMES 0x00000008
#define AL_NETCFG_RX_BACKOFF 0x00000020
#define AL_NETCFG_RX_PROMISC 0x00000040
#define AL_NETCFG_RX_ALLMULTI 0x00000080
#define AL_NETCFG_OPMODE 0x00000C00
#define AL_NETCFG_FORCECOLL 0x00001000
#define AL_NETCFG_TX_ON 0x00002000
#define AL_NETCFG_TX_THRESH 0x0000C000
#define AL_NETCFG_HEARTBEAT 0x00080000 /* 0 == ON, 1 == OFF */
#define AL_NETCFG_STORENFWD 0x00200000
#define AL_OPMODE_NORM 0x00000000
#define AL_OPMODE_INTLOOP 0x00000400
#define AL_OPMODE_EXTLOOP 0x00000800
#define AL_TXTHRESH_72BYTES 0x00000000
#define AL_TXTHRESH_96BYTES 0x00004000
#define AL_TXTHRESH_128BYTES 0x00008000
#define AL_TXTHRESH_160BYTES 0x0000C000
/*
* Interrupt mask bits.
*/
#define AL_IMR_TX_OK 0x00000001
#define AL_IMR_TX_IDLE 0x00000002
#define AL_IMR_TX_NOBUF 0x00000004
#define AL_IMR_TX_JABBERTIMEO 0x00000008
#define AL_IMR_TX_UNDERRUN 0x00000020
#define AL_IMR_RX_OK 0x00000040
#define AL_IMR_RX_NOBUF 0x00000080
#define AL_IMR_RX_IDLE 0x00000100
#define AL_IMR_RX_WATDOGTIMEO 0x00000200
#define AL_IMR_TIMER_EXPIRED 0x00000800
#define AL_IMR_BUS_ERR 0x00002000
#define AL_IMR_ABNORMAL 0x00008000
#define AL_IMR_NORMAL 0x00010000
#define AL_INTRS \
(AL_IMR_RX_OK|AL_IMR_TX_OK|AL_IMR_RX_NOBUF|AL_IMR_RX_WATDOGTIMEO|\
AL_IMR_TX_NOBUF|AL_IMR_TX_UNDERRUN|AL_IMR_BUS_ERR| \
AL_IMR_ABNORMAL|AL_IMR_NORMAL|AL_IMR_TX_IDLE|AL_IMR_RX_IDLE)
/*
* Missed packer register.
*/
#define AL_MISSEDPKT_CNT 0x0000FFFF
#define AL_MISSEDPKT_OFLOW 0x00010000
/*
* Serial I/O (EEPROM/ROM) bits.
*/
#define AL_SIO_EE_CS 0x00000001 /* EEPROM chip select */
#define AL_SIO_EE_CLK 0x00000002 /* EEPROM clock */
#define AL_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
#define AL_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
#define AL_SIO_EESEL 0x00000800
#define AL_SIO_ROMCTL_WRITE 0x00002000
#define AL_SIO_ROMCTL_READ 0x00004000
#define AL_SIO_MII_CLK 0x00010000 /* MDIO clock */
#define AL_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
#define AL_SIO_MII_DIR 0x00040000 /* MDIO dir */
#define AL_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
#define AL_EECMD_WRITE 0x140
#define AL_EECMD_READ 0x180
#define AL_EECMD_ERASE 0x1c0
#define AL_EE_NODEADDR_OFFSET 0x70
#define AL_EE_NODEADDR 4
/*
* General purpose timer register
*/
#define AL_TIMER_VALUE 0x0000FFFF
#define AL_TIMER_CONTINUOUS 0x00010000
/*
* Wakeup control/status register.
*/
#define AL_WU_LINKSTS 0x00000001 /* link status changed */
#define AL_WU_MAGICPKT 0x00000002 /* magic packet received */
#define AL_WU_WUPKT 0x00000004 /* wake up pkt received */
#define AL_WU_LINKSTS_ENB 0x00000100 /* enable linksts event */
#define AL_WU_MAGICPKT_ENB 0x00000200 /* enable magicpkt event */
#define AL_WU_WUPKT_ENB 0x00000400 /* enable wakeup pkt event */
#define AL_WU_LINKON_ENB 0x00010000 /* enable link on detect */
#define AL_WU_LINKOFF_ENB 0x00020000 /* enable link off detect */
#define AL_WU_WKUPMATCH_PAT5 0x02000000 /* enable wkup pat 5 match */
#define AL_WU_WKUPMATCH_PAT4 0x04000000 /* enable wkup pat 4 match */
#define AL_WU_WKUPMATCH_PAT3 0x08000000 /* enable wkup pat 3 match */
#define AL_WU_WKUPMATCH_PAT2 0x10000000 /* enable wkup pat 2 match */
#define AL_WU_WKUPMATCH_PAT1 0x20000000 /* enable wkup pat 1 match */
#define AL_WU_CRCTYPE 0x40000000 /* crc: 0=0000, 1=ffff */
/*
* Wakeup pattern structure.
*/
struct al_wu_pattern {
u_int32_t al_wu_bits[4];
};
struct al_wakeup {
struct al_wu_pattern al_wu_pat;
u_int16_t al_wu_crc1;
u_int16_t al_wu_offset1;
};
struct al_wakup_record {
struct al_wakeup al_wakeup[5];
};
/*
* Watchdog timer register.
*/
#define AL_WDOG_JABDISABLE 0x00000001
#define AL_WDOG_NONJABBER 0x00000002
#define AL_WDOG_JABCLK 0x00000004
#define AL_WDOG_RXWDOG_DIS 0x00000010
#define AL_WDOG_RXWDOG_REL 0x00000020
/*
* Assistant status register.
*/
#define AL_ISR2_ABNORMAL 0x00008000
#define AL_ISR2_NORMAL 0x00010000
#define AL_ISR2_RX_STATE 0x000E0000
#define AL_ISR2_TX_STATE 0x00700000
#define AL_ISR2_BUSERRTYPE 0x03800000
#define AL_ISR2_PAUSE 0x04000000 /* PAUSE frame received */
#define AL_ISR2_TX_DEFER 0x10000000
#define AL_ISR2_XCVR_INT 0x20000000
#define AL_ISR2_RX_EARLY 0x40000000
#define AL_ISR2_TX_EARLY 0x80000000
/*
* Assistant mask register.
*/
#define AL_IMR2_ABNORMAL 0x00008000
#define AL_IMR2_NORMAL 0x00010000
#define AL_IMR2_PAUSE 0x04000000 /* PAUSE frame received */
#define AL_IMR2_TX_DEFER 0x10000000
#define AL_IMR2_XCVR_INT 0x20000000
#define AL_IMR2_RX_EARLY 0x40000000
#define AL_IMR2_TX_EARLY 0x80000000
/*
* Command register, some bits loaded from EEPROM.
*/
#define AL_CMD_TXURUN_REC 0x00000001 /* enable TX underflow recovery */
#define AL_CMD_SOFTWARE_INT 0x00000002 /* software interrupt */
#define AL_CMD_DRT 0x0000000C /* drain receive threshold */
#define AL_CMD_RXTHRESH_ENB 0x00000010 /* rx threshold enable */
#define AL_CMD_PAUSE 0x00000020
#define AL_CMD_RST_WU_PTR 0x00000040 /* reset wakeup pattern reg. */
/* Values below loaded from EEPROM. */
#define AL_CMD_WOL_ENB 0x00040000 /* WOL enable */
#define AL_CMD_PM_ENB 0x00080000 /* pwr mgmt enable */
#define AL_CMD_RX_FIFO 0x00300000
#define AL_CMD_LED_MODE 0x00400000
#define AL_CMD_CURRENT_MODE 0x70000000
#define AL_CMD_D3COLD 0x80000000
/*
* PCI performance counter.
*/
#define AL_PCI_DW_CNT 0x000000FF
#define AL_PCI_CLK 0xFFFF0000
/*
* Power management command and status.
*/
#define AL_PWRM_PWR_STATE 0x00000003
#define AL_PWRM_PME_EN 0x00000100
#define AL_PWRM_DSEL 0x00001E00
#define AL_PWRM_DSCALE 0x00006000
#define AL_PWRM_PME_STAT 0x00008000
/*
* TX burst count / timeout register.
*/
#define AL_TXB_TIMEO 0x00000FFF
#define AL_TXB_BURSTCNT 0x0000F000
/*
* Flash PROM register.
*/
#define AL_PROM_DATA 0x0000000F
#define AL_PROM_ADDR 0x01FFFFF0
#define AL_PROM_WR_ENB 0x04000000
#define AL_PROM_BRA16_ON 0x80000000
/*
* COMET TX/RX list structure.
*/
struct al_desc {
u_int32_t al_status;
u_int32_t al_ctl;
u_int32_t al_ptr1;
u_int32_t al_ptr2;
/* Driver specific stuff. */
#ifdef __i386__
u_int32_t al_pad;
#endif
struct mbuf *al_mbuf;
struct al_desc *al_nextdesc;
};
#define al_data al_ptr1
#define al_next al_ptr2
#define AL_RXSTAT_FIFOOFLOW 0x00000001
#define AL_RXSTAT_CRCERR 0x00000002
#define AL_RXSTAT_DRIBBLE 0x00000004
#define AL_RXSTAT_WATCHDOG 0x00000010
#define AL_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
#define AL_RXSTAT_COLLSEEN 0x00000040
#define AL_RXSTAT_GIANT 0x00000080
#define AL_RXSTAT_LASTFRAG 0x00000100
#define AL_RXSTAT_FIRSTFRAG 0x00000200
#define AL_RXSTAT_MULTICAST 0x00000400
#define AL_RXSTAT_RUNT 0x00000800
#define AL_RXSTAT_RXTYPE 0x00003000
#define AL_RXSTAT_RXERR 0x00008000
#define AL_RXSTAT_RXLEN 0x3FFF0000
#define AL_RXSTAT_OWN 0x80000000
#define AL_RXBYTES(x) ((x & AL_RXSTAT_RXLEN) >> 16)
#define AL_RXSTAT (AL_RXSTAT_FIRSTFRAG|AL_RXSTAT_LASTFRAG|AL_RXSTAT_OWN)
#define AL_RXCTL_BUFLEN1 0x00000FFF
#define AL_RXCTL_BUFLEN2 0x00FFF000
#define AL_RXCTL_RLINK 0x01000000
#define AL_RXCTL_RLAST 0x02000000
#define AL_TXSTAT_DEFER 0x00000001
#define AL_TXSTAT_UNDERRUN 0x00000002
#define AL_TXSTAT_LINKFAIL 0x00000003
#define AL_TXSTAT_COLLCNT 0x00000078
#define AL_TXSTAT_SQE 0x00000080
#define AL_TXSTAT_EXCESSCOLL 0x00000100
#define AL_TXSTAT_LATECOLL 0x00000200
#define AL_TXSTAT_NOCARRIER 0x00000400
#define AL_TXSTAT_CARRLOST 0x00000800
#define AL_TXSTAT_JABTIMEO 0x00004000
#define AL_TXSTAT_ERRSUM 0x00008000
#define AL_TXSTAT_OWN 0x80000000
#define AL_TXCTL_BUFLEN1 0x000007FF
#define AL_TXCTL_BUFLEN2 0x003FF800
#define AL_TXCTL_PAD 0x00800000
#define AL_TXCTL_TLINK 0x01000000
#define AL_TXCTL_TLAST 0x02000000
#define AL_TXCTL_NOCRC 0x04000000
#define AL_TXCTL_FIRSTFRAG 0x20000000
#define AL_TXCTL_LASTFRAG 0x40000000
#define AL_TXCTL_FINT 0x80000000
#define AL_MAXFRAGS 16
#define AL_RX_LIST_CNT 64
#define AL_TX_LIST_CNT 128
#define AL_MIN_FRAMELEN 60
#define AL_RXLEN 1536
#define AL_INC(x, y) (x) = (x + 1) % y
struct al_list_data {
struct al_desc al_rx_list[AL_RX_LIST_CNT];
struct al_desc al_tx_list[AL_TX_LIST_CNT];
};
struct al_chain_data {
int al_tx_prod;
int al_tx_cons;
int al_tx_cnt;
int al_rx_prod;
};
struct al_type {
u_int16_t al_vid;
u_int16_t al_did;
char *al_name;
};
struct al_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
#define AL_MII_STARTDELIM 0x01
#define AL_MII_READOP 0x02
#define AL_MII_WRITEOP 0x01
#define AL_MII_TURNAROUND 0x02
struct al_softc {
struct arpcom arpcom; /* interface info */
struct ifmedia ifmedia; /* media info */
bus_space_handle_t al_bhandle; /* bus space handle */
bus_space_tag_t al_btag; /* bus space tag */
struct resource *al_res;
struct resource *al_irq;
void *al_intrhand;
device_t al_miibus;
struct al_type *al_info; /* COMET adapter info */
int al_did;
u_int8_t al_unit; /* interface number */
struct al_list_data *al_ldata;
struct al_chain_data al_cdata;
u_int8_t al_cachesize;
struct callout_handle al_stat_ch;
};
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->al_btag, sc->al_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->al_btag, sc->al_bbhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->al_btag, sc->al_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->al_btag, sc->al_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->al_btag, sc->al_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->al_btag, sc->al_bhandle, reg)
#define AL_TIMEOUT 1000
#define ETHER_ALIGN 2
/*
* General constants that are fun to know.
*
* ADMtek PCI vendor ID
*/
#define AL_VENDORID 0x1317
/*
* AL981 device IDs.
*/
#define AL_DEVICEID_AL981 0x0981
/*
* AN985 device IDs.
*/
#define AL_DEVICEID_AN985 0x0985
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define AL_PCI_VENDOR_ID 0x00
#define AL_PCI_DEVICE_ID 0x02
#define AL_PCI_COMMAND 0x04
#define AL_PCI_STATUS 0x06
#define AL_PCI_REVID 0x08
#define AL_PCI_CLASSCODE 0x09
#define AL_PCI_CACHELEN 0x0C
#define AL_PCI_LATENCY_TIMER 0x0D
#define AL_PCI_HEADER_TYPE 0x0E
#define AL_PCI_LOIO 0x10
#define AL_PCI_LOMEM 0x14
#define AL_PCI_BIOSROM 0x30
#define AL_PCI_INTLINE 0x3C
#define AL_PCI_INTPIN 0x3D
#define AL_PCI_MINGNT 0x3E
#define AL_PCI_MINLAT 0x0F
#define AL_PCI_RESETOPT 0x48
#define AL_PCI_EEPROM_DATA 0x4C
/* power management registers */
#define AL_PCI_CAPID 0x44 /* 8 bits */
#define AL_PCI_NEXTPTR 0x45 /* 8 bits */
#define AL_PCI_PWRMGMTCAP 0x46 /* 16 bits */
#define AL_PCI_PWRMGMTCTRL 0x48 /* 16 bits */
#define AL_PSTATE_MASK 0x0003
#define AL_PSTATE_D0 0x0000
#define AL_PSTATE_D1 0x0001
#define AL_PSTATE_D2 0x0002
#define AL_PSTATE_D3 0x0003
#define AL_PME_EN 0x0010
#define AL_PME_STATUS 0x8000
#ifdef __alpha__
#undef vtophys
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
#endif

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sys/pci/if_ax.c
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sys/pci/if_axreg.h
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/*
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* ASIX register definitions.
*/
#define AX_BUSCTL 0x00 /* bus control */
#define AX_TXSTART 0x08 /* tx start demand */
#define AX_RXSTART 0x10 /* rx start demand */
#define AX_RXADDR 0x18 /* rx descriptor list start addr */
#define AX_TXADDR 0x20 /* tx descriptor list start addr */
#define AX_ISR 0x28 /* interrupt status register */
#define AX_NETCFG 0x30 /* network config register */
#define AX_IMR 0x38 /* interrupt mask */
#define AX_FRAMESDISCARDED 0x40 /* # of discarded frames */
#define AX_SIO 0x48 /* MII and ROM/EEPROM access */
#define AX_RESERVED 0x50
#define AX_GENTIMER 0x58 /* general timer */
#define AX_GENPORT 0x60 /* general purpose port */
#define AX_FILTIDX 0x68 /* RX filter index */
#define AX_FILTDATA 0x70 /* RX filter data */
/*
* Bus control bits.
*/
#define AX_BUSCTL_RESET 0x00000001
#define AX_BUSCTL_ARBITRATION 0x00000002
#define AX_BUSCTL_BIGENDIAN 0x00000080
#define AX_BUSCTL_BURSTLEN 0x00003F00
#define AX_BUSCTL_BUF_BIGENDIAN 0x00100000
#define AX_BISCTL_READMULTI 0x00200000
#define AX_BURSTLEN_UNLIMIT 0x00000000
#define AX_BURSTLEN_1LONG 0x00000100
#define AX_BURSTLEN_2LONG 0x00000200
#define AX_BURSTLEN_4LONG 0x00000400
#define AX_BURSTLEN_8LONG 0x00000800
#define AX_BURSTLEN_16LONG 0x00001000
#define AX_BURSTLEN_32LONG 0x00002000
#define AX_BUSCTL_CONFIG (AX_BUSCTL_ARBITRATION|AX_BURSTLEN_8LONG|AX_BURSTLEN_8LONG)
/*
* Interrupt status bits.
*/
#define AX_ISR_TX_OK 0x00000001
#define AX_ISR_TX_IDLE 0x00000002
#define AX_ISR_TX_NOBUF 0x00000004
#define AX_ISR_TX_JABBERTIMEO 0x00000008
#define AX_ISR_TX_UNDERRUN 0x00000020
#define AX_ISR_RX_OK 0x00000040
#define AX_ISR_RX_NOBUF 0x00000080
#define AX_ISR_RX_IDLE 0x00000100
#define AX_ISR_RX_WATDOGTIMEO 0x00000200
#define AX_ISR_TX_EARLY 0x00000400
#define AX_ISR_TIMER_EXPIRED 0x00000800
#define AX_ISR_BUS_ERR 0x00002000
#define AX_ISR_ABNORMAL 0x00008000
#define AX_ISR_NORMAL 0x00010000
#define AX_ISR_RX_STATE 0x000E0000
#define AX_ISR_TX_STATE 0x00700000
#define AX_ISR_BUSERRTYPE 0x03800000
#define AX_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
#define AX_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
#define AX_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
#define AX_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
#define AX_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
#define AX_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
#define AX_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
#define AX_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
#define AX_TXSTATE_RESET 0x00000000 /* 000 - reset */
#define AX_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
#define AX_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
#define AX_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
#define AX_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
#define AX_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
#define AX_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
#define AX_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
/*
* Network config bits.
*/
#define AX_NETCFG_LINKSTAT_PCS 0x00000001
#define AX_NETCFG_RX_ON 0x00000002
#define AX_NETCFG_RX_BADFRAMES 0x00000008
#define AX_NETCFG_RX_PROMISC 0x00000040
#define AX_NETCFG_RX_ALLMULTI 0x00000080
#define AX_NETCFG_RX_BROAD 0x00000100
#define AX_NETCFG_FULLDUPLEX 0x00000200
#define AX_NETCFG_LOOPBACK 0x00000C00
#define AX_NETCFG_FORCECOLL 0x00001000
#define AX_NETCFG_TX_ON 0x00002000
#define AX_NETCFG_TX_THRESH 0x0000C000
#define AX_NETCFG_PORTSEL 0x00040000 /* 0 == SRL, 1 == MII/SYM */
#define AX_NETCFG_HEARTBEAT 0x00080000 /* 0 == ON, 1 == OFF */
#define AX_NETCFG_STORENFWD 0x00200000
#define AX_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
#define AX_NETCFG_PCS 0x00800000
#define AX_NETCFG_SCRAMBLER 0x01000000
#define AX_NETCFG_RX_ALL 0x40000000
#define AX_OPMODE_NORM 0x00000000
#define AX_OPMODE_INTLOOP 0x00000400
#define AX_OPMODE_EXTLOOP 0x00000800
#define AX_TXTHRESH_72BYTES 0x00000000
#define AX_TXTHRESH_96BYTES 0x00004000
#define AX_TXTHRESH_128BYTES 0x00008000
#define AX_TXTHRESH_160BYTES 0x0000C000
/*
* Interrupt mask bits.
*/
#define AX_IMR_TX_OK 0x00000001
#define AX_IMR_TX_IDLE 0x00000002
#define AX_IMR_TX_NOBUF 0x00000004
#define AX_IMR_TX_JABBERTIMEO 0x00000008
#define AX_IMR_TX_UNDERRUN 0x00000020
#define AX_IMR_RX_OK 0x00000040
#define AX_IMR_RX_NOBUF 0x00000080
#define AX_IMR_RX_IDLE 0x00000100
#define AX_IMR_RX_WATDOGTIMEO 0x00000200
#define AX_IMR_TX_EARLY 0x00000400
#define AX_IMR_TIMER_EXPIRED 0x00000800
#define AX_IMR_BUS_ERR 0x00002000
#define AX_IMR_RX_EARLY 0x00004000
#define AX_IMR_ABNORMAL 0x00008000
#define AX_IMR_NORMAL 0x00010000
#define AX_INTRS \
(AX_IMR_RX_OK|AX_IMR_TX_OK|AX_IMR_RX_NOBUF|AX_IMR_RX_WATDOGTIMEO|\
AX_IMR_TX_NOBUF|AX_IMR_TX_UNDERRUN|AX_IMR_BUS_ERR| \
AX_IMR_ABNORMAL|AX_IMR_NORMAL|/*AX_IMR_TX_EARLY*/ \
AX_IMR_TX_IDLE|AX_IMR_RX_IDLE)
/*
* Serial I/O (EEPROM/ROM) bits.
*/
#define AX_SIO_EE_CS 0x00000001 /* EEPROM chip select */
#define AX_SIO_EE_CLK 0x00000002 /* EEPROM clock */
#define AX_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
#define AX_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
#define AX_SIO_EESEL 0x00000800
#define AX_SIO_ROMSEL 0x00001000
#define AX_SIO_ROMCTL_WRITE 0x00002000
#define AX_SIO_ROMCTL_READ 0x00004000
#define AX_SIO_MII_CLK 0x00010000 /* MDIO clock */
#define AX_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
#define AX_SIO_MII_DIR 0x00040000 /* MDIO dir */
#define AX_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
#define AX_EECMD_WRITE 0x140
#define AX_EECMD_READ 0x180
#define AX_EECMD_ERASE 0x1c0
#define AX_EE_NODEADDR_OFFSET 0x70
#define AX_EE_NODEADDR 10
/*
* General purpose timer register
*/
#define AX_TIMER_VALUE 0x0000FFFF
#define AX_TIMER_CONTINUOUS 0x00010000
/*
* RX Filter Index Register values
*/
#define AX_FILTIDX_PAR0 0x00000000
#define AX_FILTIDX_PAR1 0x00000001
#define AX_FILTIDX_MAR0 0x00000002
#define AX_FILTIDX_MAR1 0x00000003
/*
* ASIX TX/RX list structure.
*/
struct ax_desc {
volatile u_int32_t ax_status;
volatile u_int32_t ax_ctl;
volatile u_int32_t ax_ptr1;
volatile u_int32_t ax_ptr2;
};
#define ax_data ax_ptr1
#define ax_next ax_ptr2
#define AX_RXSTAT_FIFOOFLOW 0x00000001
#define AX_RXSTAT_CRCERR 0x00000002
#define AX_RXSTAT_DRIBBLE 0x00000004
#define AX_RXSTAT_WATCHDOG 0x00000010
#define AX_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
#define AX_RXSTAT_COLLSEEN 0x00000040
#define AX_RXSTAT_GIANT 0x00000080
#define AX_RXSTAT_LASTFRAG 0x00000100
#define AX_RXSTAT_FIRSTFRAG 0x00000200
#define AX_RXSTAT_MULTICAST 0x00000400
#define AX_RXSTAT_RUNT 0x00000800
#define AX_RXSTAT_RXTYPE 0x00003000
#define AX_RXSTAT_RXERR 0x00008000
#define AX_RXSTAT_RXLEN 0x3FFF0000
#define AX_RXSTAT_OWN 0x80000000
#define AX_RXBYTES(x) ((x & AX_RXSTAT_RXLEN) >> 16)
#define AX_RXSTAT (AX_RXSTAT_FIRSTFRAG|AX_RXSTAT_LASTFRAG|AX_RXSTAT_OWN)
#define AX_RXCTL_BUFLEN1 0x00000FFF
#define AX_RXCTL_BUFLEN2 0x00FFF000
#define AX_RXCTL_RLAST 0x02000000
#define AX_TXSTAT_DEFER 0x00000001
#define AX_TXSTAT_UNDERRUN 0x00000002
#define AX_TXSTAT_LINKFAIL 0x00000003
#define AX_TXSTAT_COLLCNT 0x00000078
#define AX_TXSTAT_SQE 0x00000080
#define AX_TXSTAT_EXCESSCOLL 0x00000100
#define AX_TXSTAT_LATECOLL 0x00000200
#define AX_TXSTAT_NOCARRIER 0x00000400
#define AX_TXSTAT_CARRLOST 0x00000800
#define AX_TXSTAT_JABTIMEO 0x00004000
#define AX_TXSTAT_ERRSUM 0x00008000
#define AX_TXSTAT_OWN 0x80000000
#define AX_TXCTL_BUFLEN1 0x000007FF
#define AX_TXCTL_BUFLEN2 0x003FF800
#define AX_TXCTL_PAD 0x00800000
#define AX_TXCTL_TLAST 0x02000000
#define AX_TXCTL_NOCRC 0x04000000
#define AX_TXCTL_FIRSTFRAG 0x20000000
#define AX_TXCTL_LASTFRAG 0x40000000
#define AX_TXCTL_FINT 0x80000000
#define AX_MAXFRAGS 16
#define AX_RX_LIST_CNT 64
#define AX_TX_LIST_CNT 128
#define AX_MIN_FRAMELEN 60
/*
* A tx 'super descriptor' is actually 16 regular descriptors
* back to back.
*/
struct ax_txdesc {
volatile struct ax_desc ax_frag[AX_MAXFRAGS];
};
#define AX_TXNEXT(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_next
#define AX_TXSTATUS(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_status
#define AX_TXCTL(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_ctl
#define AX_TXDATA(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_data
#define AX_TXOWN(x) x->ax_ptr->ax_frag[0].ax_status
#define AX_UNSENT 0x12341234
struct ax_list_data {
volatile struct ax_desc ax_rx_list[AX_RX_LIST_CNT];
volatile struct ax_txdesc ax_tx_list[AX_TX_LIST_CNT];
};
struct ax_chain {
volatile struct ax_txdesc *ax_ptr;
struct mbuf *ax_mbuf;
struct ax_chain *ax_nextdesc;
u_int8_t ax_lastdesc;
};
struct ax_chain_onefrag {
volatile struct ax_desc *ax_ptr;
struct mbuf *ax_mbuf;
struct ax_chain_onefrag *ax_nextdesc;
};
struct ax_chain_data {
struct ax_chain_onefrag ax_rx_chain[AX_RX_LIST_CNT];
struct ax_chain ax_tx_chain[AX_TX_LIST_CNT];
struct ax_chain_onefrag *ax_rx_head;
struct ax_chain *ax_tx_head;
struct ax_chain *ax_tx_tail;
struct ax_chain *ax_tx_free;
};
struct ax_type {
u_int16_t ax_vid;
u_int16_t ax_did;
char *ax_name;
};
struct ax_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define AX_MII_STARTDELIM 0x01
#define AX_MII_READOP 0x02
#define AX_MII_WRITEOP 0x01
#define AX_MII_TURNAROUND 0x02
#define AX_FLAG_FORCEDELAY 1
#define AX_FLAG_SCHEDDELAY 2
#define AX_FLAG_DELAYTIMEO 3
struct ax_softc {
struct arpcom arpcom; /* interface info */
struct ifmedia ifmedia; /* media info */
bus_space_handle_t ax_bhandle; /* bus space handle */
bus_space_tag_t ax_btag; /* bus space tag */
void *ax_intrhand;
struct resource *ax_irq;
struct resource *ax_res;
struct ax_type *ax_info; /* ASIX adapter info */
struct ax_type *ax_pinfo; /* phy info */
u_int8_t ax_unit; /* interface number */
u_int8_t ax_type;
u_int8_t ax_phy_addr; /* PHY address */
u_int8_t ax_tx_pend; /* TX pending */
u_int8_t ax_want_auto;
u_int8_t ax_autoneg;
caddr_t ax_ldata_ptr;
struct ax_list_data *ax_ldata;
struct ax_chain_data ax_cdata;
};
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->ax_btag, sc->ax_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->ax_btag, sc->ax_bbhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->ax_btag, sc->ax_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->ax_btag, sc->ax_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->ax_btag, sc->ax_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->ax_btag, sc->ax_bhandle, reg)
#define AX_TIMEOUT 1000
#define ETHER_ALIGN 2
/*
* General constants that are fun to know.
*
* ASIX PCI vendor ID
*/
#define AX_VENDORID 0x125B
/*
* ASIX device IDs.
*/
#define AX_DEVICEID_AX88140A 0x1400
/*
* The ASIX AX88140 and ASIX AX88141 have the same vendor and
* device IDs but different revision values.
*/
#define AX_REVISION_88140 0x00
#define AX_REVISION_88141 0x10
/*
* Texas Instruments PHY identifiers
*/
#define TI_PHY_VENDORID 0x4000
#define TI_PHY_10BT 0x501F
#define TI_PHY_100VGPMI 0x502F
/*
* These ID values are for the NS DP83840A 10/100 PHY
*/
#define NS_PHY_VENDORID 0x2000
#define NS_PHY_83840A 0x5C0F
/*
* Level 1 10/100 PHY
*/
#define LEVEL1_PHY_VENDORID 0x7810
#define LEVEL1_PHY_LXT970 0x000F
/*
* Intel 82555 10/100 PHY
*/
#define INTEL_PHY_VENDORID 0x0A28
#define INTEL_PHY_82555 0x015F
/*
* SEEQ 80220 10/100 PHY
*/
#define SEEQ_PHY_VENDORID 0x0016
#define SEEQ_PHY_80220 0xF83F
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define AX_PCI_VENDOR_ID 0x00
#define AX_PCI_DEVICE_ID 0x02
#define AX_PCI_COMMAND 0x04
#define AX_PCI_STATUS 0x06
#define AX_PCI_REVID 0x08
#define AX_PCI_CLASSCODE 0x09
#define AX_PCI_LATENCY_TIMER 0x0D
#define AX_PCI_HEADER_TYPE 0x0E
#define AX_PCI_LOIO 0x10
#define AX_PCI_LOMEM 0x14
#define AX_PCI_BIOSROM 0x30
#define AX_PCI_INTLINE 0x3C
#define AX_PCI_INTPIN 0x3D
#define AX_PCI_MINGNT 0x3E
#define AX_PCI_MINLAT 0x0F
#define AX_PCI_RESETOPT 0x48
#define AX_PCI_EEPROM_DATA 0x4C
/* power management registers */
#define AX_PCI_CAPID 0x44 /* 8 bits */
#define AX_PCI_NEXTPTR 0x45 /* 8 bits */
#define AX_PCI_PWRMGMTCAP 0x46 /* 16 bits */
#define AX_PCI_PWRMGMTCTRL 0x48 /* 16 bits */
#define AX_PSTATE_MASK 0x0003
#define AX_PSTATE_D0 0x0000
#define AX_PSTATE_D1 0x0001
#define AX_PSTATE_D2 0x0002
#define AX_PSTATE_D3 0x0003
#define AX_PME_EN 0x0010
#define AX_PME_STATUS 0x8000
#define PHY_UNKNOWN 6
#define AX_PHYADDR_MIN 0x00
#define AX_PHYADDR_MAX 0x1F
#define PHY_BMCR 0x00
#define PHY_BMSR 0x01
#define PHY_VENID 0x02
#define PHY_DEVID 0x03
#define PHY_ANAR 0x04
#define PHY_LPAR 0x05
#define PHY_ANEXP 0x06
#define PHY_ANAR_NEXTPAGE 0x8000
#define PHY_ANAR_RSVD0 0x4000
#define PHY_ANAR_TLRFLT 0x2000
#define PHY_ANAR_RSVD1 0x1000
#define PHY_ANAR_RSVD2 0x0800
#define PHY_ANAR_RSVD3 0x0400
#define PHY_ANAR_100BT4 0x0200
#define PHY_ANAR_100BTXFULL 0x0100
#define PHY_ANAR_100BTXHALF 0x0080
#define PHY_ANAR_10BTFULL 0x0040
#define PHY_ANAR_10BTHALF 0x0020
#define PHY_ANAR_PROTO4 0x0010
#define PHY_ANAR_PROTO3 0x0008
#define PHY_ANAR_PROTO2 0x0004
#define PHY_ANAR_PROTO1 0x0002
#define PHY_ANAR_PROTO0 0x0001
/*
* These are the register definitions for the PHY (physical layer
* interface chip).
*/
/*
* PHY BMCR Basic Mode Control Register
*/
#define PHY_BMCR_RESET 0x8000
#define PHY_BMCR_LOOPBK 0x4000
#define PHY_BMCR_SPEEDSEL 0x2000
#define PHY_BMCR_AUTONEGENBL 0x1000
#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
#define PHY_BMCR_ISOLATE 0x0400
#define PHY_BMCR_AUTONEGRSTR 0x0200
#define PHY_BMCR_DUPLEX 0x0100
#define PHY_BMCR_COLLTEST 0x0080
#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
/*
* RESET: 1 == software reset, 0 == normal operation
* Resets status and control registers to default values.
* Relatches all hardware config values.
*
* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
*
* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
* Link speed is selected byt his bit or if auto-negotiation if bit
* 12 (AUTONEGENBL) is set (in which case the value of this register
* is ignored).
*
* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
* determine speed and mode. Should be cleared and then set if PHY configured
* for no autoneg on startup.
*
* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
*
* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
*
* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
*
* COLLTEST: 1 == collision test enabled, 0 == normal operation
*/
/*
* PHY, BMSR Basic Mode Status Register
*/
#define PHY_BMSR_100BT4 0x8000
#define PHY_BMSR_100BTXFULL 0x4000
#define PHY_BMSR_100BTXHALF 0x2000
#define PHY_BMSR_10BTFULL 0x1000
#define PHY_BMSR_10BTHALF 0x0800
#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
#define PHY_BMSR_MFPRESUP 0x0040
#define PHY_BMSR_AUTONEGCOMP 0x0020
#define PHY_BMSR_REMFAULT 0x0010
#define PHY_BMSR_CANAUTONEG 0x0008
#define PHY_BMSR_LINKSTAT 0x0004
#define PHY_BMSR_JABBER 0x0002
#define PHY_BMSR_EXTENDED 0x0001
#ifdef __alpha__
#undef vtophys
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
#endif

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/*
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* 21143 and clone common register definitions.
*/
#define DC_BUSCTL 0x00 /* bus control */
#define DC_TXSTART 0x08 /* tx start demand */
#define DC_RXSTART 0x10 /* rx start demand */
#define DC_RXADDR 0x18 /* rx descriptor list start addr */
#define DC_TXADDR 0x20 /* tx descriptor list start addr */
#define DC_ISR 0x28 /* interrupt status register */
#define DC_NETCFG 0x30 /* network config register */
#define DC_IMR 0x38 /* interrupt mask */
#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
#define DC_SIO 0x48 /* MII and ROM/EEPROM access */
#define DC_ROM 0x50 /* ROM programming address */
#define DC_TIMER 0x58 /* general timer */
#define DC_10BTSTAT 0x60 /* SIA status */
#define DC_SIARESET 0x68 /* SIA connectivity */
#define DC_10BTCTRL 0x70 /* SIA transmit and receive */
#define DC_WATCHDOG 0x78 /* SIA and general purpose port */
/*
* There are two general 'types' of MX chips that we need to be
* concerned with. One is the original 98713, which has its internal
* NWAY support controlled via the MDIO bits in the serial I/O
* register. The other is everything else (from the 98713A on up),
* which has its internal NWAY controlled via CSR13, CSR14 and CSR15,
* just like the 21143. This type setting also governs which of the
* 'magic' numbers we write to CSR16. The PNIC II falls into the
* 98713A/98715/98715A/98725 category.
*/
#define DC_TYPE_98713 0x1
#define DC_TYPE_98713A 0x2
#define DC_TYPE_987x5 0x3
/* Other type of supported chips. */
#define DC_TYPE_21143 0x4 /* Intel 21143 */
#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */
#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */
#define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */
#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */
#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */
#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */
#define DC_IS_MACRONIX(x) \
(x->dc_type == DC_TYPE_98713 || \
x->dc_type == DC_TYPE_98713A || \
x->dc_type == DC_TYPE_987x5)
#define DC_IS_ADMTEK(x) \
(x->dc_type == DC_TYPE_AL981 || \
x->dc_type == DC_TYPE_AN985)
#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143)
#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX)
#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981)
#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985)
#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102)
#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII)
#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC)
/* MII/symbol mode port types */
#define DC_PMODE_MII 0x1
#define DC_PMODE_SYM 0x2
/*
* Bus control bits.
*/
#define DC_BUSCTL_RESET 0x00000001
#define DC_BUSCTL_ARBITRATION 0x00000002
#define DC_BUSCTL_SKIPLEN 0x0000007C
#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080
#define DC_BUSCTL_BURSTLEN 0x00003F00
#define DC_BUSCTL_CACHEALIGN 0x0000C000
#define DC_BUSCTL_TXPOLL 0x000E0000
#define DC_BUSCTL_DBO 0x00100000
#define DC_BUSCTL_MRME 0x00200000
#define DC_BUSCTL_MRLE 0x00800000
#define DC_BUSCTL_MWIE 0x01000000
#define DC_BUSCTL_ONNOW_ENB 0x04000000
#define DC_SKIPLEN_1LONG 0x00000004
#define DC_SKIPLEN_2LONG 0x00000008
#define DC_SKIPLEN_3LONG 0x00000010
#define DC_SKIPLEN_4LONG 0x00000020
#define DC_SKIPLEN_5LONG 0x00000040
#define DC_CACHEALIGN_NONE 0x00000000
#define DC_CACHEALIGN_8LONG 0x00004000
#define DC_CACHEALIGN_16LONG 0x00008000
#define DC_CACHEALIGN_32LONG 0x0000C000
#define DC_BURSTLEN_USECA 0x00000000
#define DC_BURSTLEN_1LONG 0x00000100
#define DC_BURSTLEN_2LONG 0x00000200
#define DC_BURSTLEN_4LONG 0x00000400
#define DC_BURSTLEN_8LONG 0x00000800
#define DC_BURSTLEN_16LONG 0x00001000
#define DC_BURSTLEN_32LONG 0x00002000
#define DC_TXPOLL_OFF 0x00000000
#define DC_TXPOLL_1 0x00020000
#define DC_TXPOLL_2 0x00040000
#define DC_TXPOLL_3 0x00060000
#define DC_TXPOLL_4 0x00080000
#define DC_TXPOLL_5 0x000A0000
#define DC_TXPOLL_6 0x000C0000
#define DC_TXPOLL_7 0x000E0000
/*
* Interrupt status bits.
*/
#define DC_ISR_TX_OK 0x00000001
#define DC_ISR_TX_IDLE 0x00000002
#define DC_ISR_TX_NOBUF 0x00000004
#define DC_ISR_TX_JABBERTIMEO 0x00000008
#define DC_ISR_LINKGOOD 0x00000010
#define DC_ISR_TX_UNDERRUN 0x00000020
#define DC_ISR_RX_OK 0x00000040
#define DC_ISR_RX_NOBUF 0x00000080
#define DC_ISR_RX_READ 0x00000100
#define DC_ISR_RX_WATDOGTIMEO 0x00000200
#define DC_ISR_TX_EARLY 0x00000400
#define DC_ISR_TIMER_EXPIRED 0x00000800
#define DC_ISR_LINKFAIL 0x00001000
#define DC_ISR_BUS_ERR 0x00002000
#define DC_ISR_RX_EARLY 0x00004000
#define DC_ISR_ABNORMAL 0x00008000
#define DC_ISR_NORMAL 0x00010000
#define DC_ISR_RX_STATE 0x000E0000
#define DC_ISR_TX_STATE 0x00700000
#define DC_ISR_BUSERRTYPE 0x03800000
#define DC_ISR_100MBPSLINK 0x08000000
#define DC_ISR_MAGICKPACK 0x10000000
#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */
#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
/*
* Network config bits.
*/
#define DC_NETCFG_RX_HASHPERF 0x00000001
#define DC_NETCFG_RX_ON 0x00000002
#define DC_NETCFG_RX_HASHONLY 0x00000004
#define DC_NETCFG_RX_BADFRAMES 0x00000008
#define DC_NETCFG_RX_INVFILT 0x00000010
#define DC_NETCFG_BACKOFFCNT 0x00000020
#define DC_NETCFG_RX_PROMISC 0x00000040
#define DC_NETCFG_RX_ALLMULTI 0x00000080
#define DC_NETCFG_FULLDUPLEX 0x00000200
#define DC_NETCFG_LOOPBACK 0x00000C00
#define DC_NETCFG_FORCECOLL 0x00001000
#define DC_NETCFG_TX_ON 0x00002000
#define DC_NETCFG_TX_THRESH 0x0000C000
#define DC_NETCFG_TX_BACKOFF 0x00020000
#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
#define DC_NETCFG_HEARTBEAT 0x00080000
#define DC_NETCFG_STORENFWD 0x00200000
#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
#define DC_NETCFG_PCS 0x00800000
#define DC_NETCFG_SCRAMBLER 0x01000000
#define DC_NETCFG_NO_RXCRC 0x02000000
#define DC_NETCFG_RX_ALL 0x40000000
#define DC_NETCFG_CAPEFFECT 0x80000000
#define DC_OPMODE_NORM 0x00000000
#define DC_OPMODE_INTLOOP 0x00000400
#define DC_OPMODE_EXTLOOP 0x00000800
#define DC_TXTHRESH_72BYTES 0x00000000
#define DC_TXTHRESH_96BYTES 0x00004000
#define DC_TXTHRESH_128BYTES 0x00008000
#define DC_TXTHRESH_160BYTES 0x0000C000
/*
* Interrupt mask bits.
*/
#define DC_IMR_TX_OK 0x00000001
#define DC_IMR_TX_IDLE 0x00000002
#define DC_IMR_TX_NOBUF 0x00000004
#define DC_IMR_TX_JABBERTIMEO 0x00000008
#define DC_IMR_LINKGOOD 0x00000010
#define DC_IMR_TX_UNDERRUN 0x00000020
#define DC_IMR_RX_OK 0x00000040
#define DC_IMR_RX_NOBUF 0x00000080
#define DC_IMR_RX_READ 0x00000100
#define DC_IMR_RX_WATDOGTIMEO 0x00000200
#define DC_IMR_TX_EARLY 0x00000400
#define DC_IMR_TIMER_EXPIRED 0x00000800
#define DC_IMR_LINKFAIL 0x00001000
#define DC_IMR_BUS_ERR 0x00002000
#define DC_IMR_RX_EARLY 0x00004000
#define DC_IMR_ABNORMAL 0x00008000
#define DC_IMR_NORMAL 0x00010000
#define DC_IMR_100MBPSLINK 0x08000000
#define DC_IMR_MAGICKPACK 0x10000000
#define DC_INTRS \
(DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\
DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \
DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/)
/*
* Serial I/O (EEPROM/ROM) bits.
*/
#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */
#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */
#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
#define DC_SIO_ROMDATA4 0x00000010
#define DC_SIO_ROMDATA5 0x00000020
#define DC_SIO_ROMDATA6 0x00000040
#define DC_SIO_ROMDATA7 0x00000080
#define DC_SIO_EESEL 0x00000800
#define DC_SIO_ROMSEL 0x00001000
#define DC_SIO_ROMCTL_WRITE 0x00002000
#define DC_SIO_ROMCTL_READ 0x00004000
#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */
#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */
#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
#define DC_EECMD_WRITE 0x140
#define DC_EECMD_READ 0x180
#define DC_EECMD_ERASE 0x1c0
#define DC_EE_NODEADDR_OFFSET 0x70
#define DC_EE_NODEADDR 10
/*
* General purpose timer register
*/
#define DC_TIMER_VALUE 0x0000FFFF
#define DC_TIMER_CONTINUOUS 0x00010000
/*
* 10baseT status register
*/
#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */
#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */
#define DC_TSTAT_AUTOPOLARITY 0x00000008
#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */
#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */
#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */
#define DC_TSTAT_REMFAULT 0x00000800
#define DC_TSTAT_ANEGSTAT 0x00007000
#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
#define DC_ASTAT_DISABLE 0x00000000
#define DC_ASTAT_TXDISABLE 0x00001000
#define DC_ASTAT_ABDETECT 0x00002000
#define DC_ASTAT_ACKDETECT 0x00003000
#define DC_ASTAT_CMPACKDETECT 0x00004000
#define DC_ASTAT_AUTONEGCMP 0x00005000
#define DC_ASTAT_LINKCHECK 0x00006000
/*
* PHY reset register
*/
#define DC_SIA_RESET 0x00000001
#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */
/*
* 10baseT control register
*/
#define DC_TCTL_ENCODER_ENB 0x00000001
#define DC_TCTL_LOOPBACK 0x00000002
#define DC_TCTL_DRIVER_ENB 0x00000004
#define DC_TCTL_LNKPULSE_ENB 0x00000008
#define DC_TCTL_HALFDUPLEX 0x00000040
#define DC_TCTL_AUTONEGENBL 0x00000080
#define DC_TCTL_RX_SQUELCH 0x00000100
#define DC_TCTL_COLL_SQUELCH 0x00000200
#define DC_TCTL_COLL_DETECT 0x00000400
#define DC_TCTL_SQE_ENB 0x00000800
#define DC_TCTL_LINKTEST 0x00001000
#define DC_TCTL_AUTOPOLARITY 0x00002000
#define DC_TCTL_SET_POL_PLUS 0x00004000
#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */
#define DC_TCTL_100BTXHALF 0x00010000
#define DC_TCTL_100BTXFULL 0x00020000
#define DC_TCTL_100BT4 0x00040000
/*
* Watchdog timer register
*/
#define DC_WDOG_JABBERDIS 0x00000001
#define DC_WDOG_HOSTUNJAB 0x00000002
#define DC_WDOG_JABBERCLK 0x00000004
#define DC_WDOG_RXWDOGDIS 0x00000010
#define DC_WDOG_RXWDOGCLK 0x00000020
#define DC_WDOG_MUSTBEZERO 0x00000100
/*
* Size of a setup frame.
*/
#define DC_SFRAME_LEN 192
/*
* 21x4x TX/RX list structure.
*/
struct dc_desc {
u_int32_t dc_status;
u_int32_t dc_ctl;
u_int32_t dc_ptr1;
u_int32_t dc_ptr2;
};
#define dc_data dc_ptr1
#define dc_next dc_ptr2
#define DC_RXSTAT_FIFOOFLOW 0x00000001
#define DC_RXSTAT_CRCERR 0x00000002
#define DC_RXSTAT_DRIBBLE 0x00000004
#define DC_RXSTAT_WATCHDOG 0x00000010
#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
#define DC_RXSTAT_COLLSEEN 0x00000040
#define DC_RXSTAT_GIANT 0x00000080
#define DC_RXSTAT_LASTFRAG 0x00000100
#define DC_RXSTAT_FIRSTFRAG 0x00000200
#define DC_RXSTAT_MULTICAST 0x00000400
#define DC_RXSTAT_RUNT 0x00000800
#define DC_RXSTAT_RXTYPE 0x00003000
#define DC_RXSTAT_RXERR 0x00008000
#define DC_RXSTAT_RXLEN 0x3FFF0000
#define DC_RXSTAT_OWN 0x80000000
#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16)
#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN)
#define DC_RXCTL_BUFLEN1 0x00000FFF
#define DC_RXCTL_BUFLEN2 0x00FFF000
#define DC_RXCTL_RLINK 0x01000000
#define DC_RXCTL_RLAST 0x02000000
#define DC_TXSTAT_DEFER 0x00000001
#define DC_TXSTAT_UNDERRUN 0x00000002
#define DC_TXSTAT_LINKFAIL 0x00000003
#define DC_TXSTAT_COLLCNT 0x00000078
#define DC_TXSTAT_SQE 0x00000080
#define DC_TXSTAT_EXCESSCOLL 0x00000100
#define DC_TXSTAT_LATECOLL 0x00000200
#define DC_TXSTAT_NOCARRIER 0x00000400
#define DC_TXSTAT_CARRLOST 0x00000800
#define DC_TXSTAT_JABTIMEO 0x00004000
#define DC_TXSTAT_ERRSUM 0x00008000
#define DC_TXSTAT_OWN 0x80000000
#define DC_TXCTL_BUFLEN1 0x000007FF
#define DC_TXCTL_BUFLEN2 0x003FF800
#define DC_TXCTL_FILTTYPE0 0x00400000
#define DC_TXCTL_PAD 0x00800000
#define DC_TXCTL_TLINK 0x01000000
#define DC_TXCTL_TLAST 0x02000000
#define DC_TXCTL_NOCRC 0x04000000
#define DC_TXCTL_SETUP 0x08000000
#define DC_TXCTL_FILTTYPE1 0x10000000
#define DC_TXCTL_FIRSTFRAG 0x20000000
#define DC_TXCTL_LASTFRAG 0x40000000
#define DC_TXCTL_FINT 0x80000000
#define DC_FILTER_PERFECT 0x00000000
#define DC_FILTER_HASHPERF 0x00400000
#define DC_FILTER_INVERSE 0x10000000
#define DC_FILTER_HASHONLY 0x10400000
#define DC_MAXFRAGS 16
#define DC_RX_LIST_CNT 64
#define DC_TX_LIST_CNT 256
#define DC_MIN_FRAMELEN 60
#define DC_RXLEN 1536
#define DC_INC(x, y) (x) = (x + 1) % y
struct dc_list_data {
struct dc_desc dc_rx_list[DC_RX_LIST_CNT];
struct dc_desc dc_tx_list[DC_TX_LIST_CNT];
};
struct dc_chain_data {
struct mbuf *dc_rx_chain[DC_RX_LIST_CNT];
struct mbuf *dc_tx_chain[DC_TX_LIST_CNT];
u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)];
u_int8_t dc_pad[DC_MIN_FRAMELEN];
int dc_tx_prod;
int dc_tx_cons;
int dc_tx_cnt;
int dc_rx_prod;
};
struct dc_type {
u_int16_t dc_vid;
u_int16_t dc_did;
char *dc_name;
};
struct dc_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define DC_MII_STARTDELIM 0x01
#define DC_MII_READOP 0x02
#define DC_MII_WRITEOP 0x01
#define DC_MII_TURNAROUND 0x02
/*
* Registers specific to clone devices.
* This mainly relates to RX filter programming: not all 21x4x clones
* use the standard DEC filter programming mechanism.
*/
/*
* ADMtek specific registers and constants for the AL981 and AN985.
* The AN985 doesn't use the magic PHY registers.
*/
#define DC_AL_PAR0 0xA4 /* station address */
#define DC_AL_PAR1 0xA8 /* station address */
#define DC_AL_MAR0 0xAC /* multicast hash filter */
#define DC_AL_MAR1 0xB0 /* multicast hash filter */
#define DC_AL_BMCR 0xB4 /* built in PHY control */
#define DC_AL_BMSR 0xB8 /* built in PHY status */
#define DC_AL_VENID 0xBC /* built in PHY ID0 */
#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */
#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */
#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */
#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */
#define DC_ADMTEK_PHYADDR 0x1
#define DC_AL_EE_NODEADDR 4
/* End of ADMtek specific registers */
/*
* ASIX specific registers.
*/
#define DC_AX_FILTIDX 0x68 /* RX filter index */
#define DC_AX_FILTDATA 0x70 /* RX filter data */
/*
* Special ASIX-specific bits in the ASIX NETCFG register (CSR6).
*/
#define DC_AX_NETCFG_RX_BROAD 0x00000100
/*
* RX Filter Index Register values
*/
#define DC_AX_FILTIDX_PAR0 0x00000000
#define DC_AX_FILTIDX_PAR1 0x00000001
#define DC_AX_FILTIDX_MAR0 0x00000002
#define DC_AX_FILTIDX_MAR1 0x00000003
/* End of ASIX specific registers */
/*
* Macronix specific registers. The Macronix chips have a special
* register for reading the NWAY status, which we don't use, plus
* a magic packet register, which we need to tweak a bit per the
* Macronix application notes.
*/
#define DC_MX_MAGICPACKET 0x80
#define DC_MX_NWAYSTAT 0xA0
/*
* Magic packet register
*/
#define DC_MX_MPACK_DISABLE 0x00400000
/*
* NWAY status register.
*/
#define DC_MX_NWAY_10BTHALF 0x08000000
#define DC_MX_NWAY_10BTFULL 0x10000000
#define DC_MX_NWAY_100BTHALF 0x20000000
#define DC_MX_NWAY_100BTFULL 0x40000000
#define DC_MX_NWAY_100BT4 0x80000000
/*
* These are magic values that must be written into CSR16
* (DC_MX_MAGICPACKET) in order to put the chip into proper
* operating mode. The magic numbers are documented in the
* Macronix 98715 application notes.
*/
#define DC_MX_MAGIC_98713 0x0F370000
#define DC_MX_MAGIC_98713A 0x0B3C0000
#define DC_MX_MAGIC_98715 0x0B3C0000
#define DC_MX_MAGIC_98725 0x0B3C0000
/* End of Macronix specific registers */
/*
* PNIC 82c168/82c169 specific registers.
* The PNIC has its own special NWAY support, which doesn't work,
* and shortcut ways of reading the EEPROM and MII bus.
*/
#define DC_PN_GPIO 0x60 /* general purpose pins control */
#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */
#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */
#define DC_PN_MII 0xA0 /* MII access register */
#define DC_PN_NWAY 0xB8 /* Internal NWAY register */
/* Serial I/O EEPROM register */
#define DC_PN_SIOCTL_DATA 0x0000003F
#define DC_PN_SIOCTL_OPCODE 0x00000300
#define DC_PN_SIOCTL_BUSY 0x80000000
#define DC_PN_EEOPCODE_ERASE 0x00000300
#define DC_PN_EEOPCODE_READ 0x00000600
#define DC_PN_EEOPCODE_WRITE 0x00000100
/*
* The first two general purpose pins control speed selection and
* 100Mbps loopback on the 82c168 chip. The control bits should always
* be set (to make the data pins outputs) and the speed selction and
* loopback bits set accordingly when changing media. Physically, this
* will set the state of a relay mounted on the card.
*/
#define DC_PN_GPIO_DATA0 0x000000001
#define DC_PN_GPIO_DATA1 0x000000002
#define DC_PN_GPIO_DATA2 0x000000004
#define DC_PN_GPIO_DATA3 0x000000008
#define DC_PN_GPIO_CTL0 0x000000010
#define DC_PN_GPIO_CTL1 0x000000020
#define DC_PN_GPIO_CTL2 0x000000040
#define DC_PN_GPIO_CTL3 0x000000080
#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */
#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */
#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2
#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3
#define DC_PN_GPIO_SETBIT(sc, r) \
DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4)))
#define DC_PN_GPIO_CLRBIT(sc, r) \
{ \
DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \
DC_CLRBIT(sc, DC_PN_GPIO, (r)); \
}
/* shortcut MII access register */
#define DC_PN_MII_DATA 0x0000FFFF
#define DC_PN_MII_RESERVER 0x00020000
#define DC_PN_MII_REGADDR 0x007C0000
#define DC_PN_MII_PHYADDR 0x0F800000
#define DC_PN_MII_OPCODE 0x30000000
#define DC_PN_MII_BUSY 0x80000000
#define DC_PN_MIIOPCODE_READ 0x60020000
#define DC_PN_MIIOPCODE_WRITE 0x50020000
/* Internal NWAY bits */
#define DC_PN_NWAY_RESET 0x00000001 /* reset */
#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */
#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */
#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */
#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */
#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */
#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */
#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */
#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */
#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */
#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */
#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */
#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */
#define DC_PN_NWAY_CAP10HDX 0x00002000
#define DC_PN_NWAY_CAP10FDX 0x00004000
#define DC_PN_NWAY_CAP100FDX 0x00008000
#define DC_PN_NWAY_CAP100HDX 0x00010000
#define DC_PN_NWAY_CAP100T4 0x00020000
#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */
#define DC_PN_NWAY_REMFAULT 0x04000000
#define DC_PN_NWAY_LPAR10HDX 0x08000000
#define DC_PN_NWAY_LPAR10FDX 0x10000000
#define DC_PN_NWAY_LPAR100FDX 0x20000000
#define DC_PN_NWAY_LPAR100HDX 0x40000000
#define DC_PN_NWAY_LPAR100T4 0x80000000
/* End of PNIC specific registers */
struct dc_softc {
struct arpcom arpcom; /* interface info */
bus_space_handle_t dc_bhandle; /* bus space handle */
bus_space_tag_t dc_btag; /* bus space tag */
void *dc_intrhand;
struct resource *dc_irq;
struct resource *dc_res;
struct dc_type *dc_info; /* adapter info */
device_t dc_miibus;
u_int8_t dc_unit; /* interface number */
u_int8_t dc_type;
u_int8_t dc_pmode;
u_int8_t dc_link;
u_int8_t dc_cachesize;
int dc_pnic_rx_bug_save;
unsigned char *dc_pnic_rx_buf;
int dc_if_flags;
int dc_if_media;
u_int32_t dc_flags;
u_int32_t dc_txthresh;
struct dc_list_data *dc_ldata;
struct dc_chain_data dc_cdata;
struct callout_handle dc_stat_ch;
};
#define DC_TX_POLL 0x00000001
#define DC_TX_COALESCE 0x00000002
#define DC_TX_ADMTEK_WAR 0x00000004
#define DC_TX_USE_TX_INTR 0x00000008
#define DC_RX_FILTER_TULIP 0x00000010
#define DC_TX_INTR_FIRSTFRAG 0x00000020
#define DC_PNIC_RX_BUG_WAR 0x00000040
#define DC_TX_FIXED_RING 0x00000080
#define DC_TX_STORENFWD 0x00000100
#define DC_REDUCED_MII_POLL 0x00000200
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)
#define DC_TIMEOUT 1000
#define ETHER_ALIGN 2
/*
* General constants that are fun to know.
*/
/*
* DEC PCI vendor ID
*/
#define DC_VENDORID_DEC 0x1011
/*
* DEC/Intel 21143 PCI device ID
*/
#define DC_DEVICEID_21143 0x0019
/*
* Macronix PCI vendor ID
*/
#define DC_VENDORID_MX 0x10D9
/*
* Macronix PMAC device IDs.
*/
#define DC_DEVICEID_98713 0x0512
#define DC_DEVICEID_987x5 0x0531
/* Macronix PCI revision codes. */
#define DC_REVISION_98713 0x00
#define DC_REVISION_98713A 0x10
#define DC_REVISION_98715 0x20
#define DC_REVISION_98725 0x30
/*
* Compex PCI vendor ID.
*/
#define DC_VENDORID_CP 0x11F6
/*
* Compex PMAC PCI device IDs.
*/
#define DC_DEVICEID_98713_CP 0x9881
/*
* Lite-On PNIC PCI vendor ID
*/
#define DC_VENDORID_LO 0x11AD
/*
* 82c168/82c169 PNIC device IDs. Both chips have the same device
* ID but different revisions. Revision 0x10 is the 82c168, and
* 0x20 is the 82c169.
*/
#define DC_DEVICEID_82C168 0x0002
#define DC_REVISION_82C168 0x10
#define DC_REVISION_82C169 0x20
/*
* Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A
* with wake on lan/magic packet support.
*/
#define DC_DEVICEID_82C115 0xc115
/*
* Davicom vendor ID.
*/
#define DC_VENDORID_DAVICOM 0x1282
/*
* Davicom device IDs.
*/
#define DC_DEVICEID_DM9100 0x9100
#define DC_DEVICEID_DM9102 0x9102
/*
* ADMtek vendor ID.
*/
#define DC_VENDORID_ADMTEK 0x1317
/*
* ADMtek device IDs.
*/
#define DC_DEVICEID_AL981 0x0981
#define DC_DEVICEID_AN985 0x0985
/*
* ASIX vendor ID.
*/
#define DC_VENDORID_ASIX 0x125B
/*
* ASIX device IDs.
*/
#define DC_DEVICEID_AX88140A 0x1400
/*
* The ASIX AX88140 and ASIX AX88141 have the same vendor and
* device IDs but different revision values.
*/
#define DC_REVISION_88140 0x00
#define DC_REVISION_88141 0x10
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define DC_PCI_CFID 0x00 /* Id */
#define DC_PCI_CFCS 0x04 /* Command and status */
#define DC_PCI_CFRV 0x08 /* Revision */
#define DC_PCI_CFLT 0x0C /* Latency timer */
#define DC_PCI_CFBIO 0x10 /* Base I/O address */
#define DC_PCI_CFBMA 0x14 /* Base memory address */
#define DC_PCI_CCIS 0x28 /* Card info struct */
#define DC_PCI_CSID 0x2C /* Subsystem ID */
#define DC_PCI_CBER 0x30 /* Expansion ROM base address */
#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */
#define DC_PCI_CFIT 0x3C /* Interrupt */
#define DC_PCI_CFDD 0x40 /* Device and driver area */
#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */
#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */
#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */
#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */
#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */
#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */
#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */
/* PCI ID register */
#define DC_CFID_VENDOR 0x0000FFFF
#define DC_CFID_DEVICE 0xFFFF0000
/* PCI command/status register */
#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */
#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */
#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */
#define DC_CFCS_MWI_ENB 0x00000008 /* mem write and inval enable */
#define DC_CFCS_PARITYERR_ENB 0x00000020 /* parity error enable */
#define DC_CFCS_SYSERR_ENB 0x00000080 /* system error enable */
#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */
#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */
#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */
#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */
#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */
#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */
#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */
#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */
/* PCI revision register */
#define DC_CFRV_STEPPING 0x0000000F
#define DC_CFRV_REVISION 0x000000F0
#define DC_CFRV_SUBCLASS 0x00FF0000
#define DC_CFRV_BASECLASS 0xFF000000
#define DC_21143_PB_REV 0x00000030
#define DC_21143_TB_REV 0x00000030
#define DC_21143_PC_REV 0x00000030
#define DC_21143_TC_REV 0x00000030
#define DC_21143_PD_REV 0x00000041
#define DC_21143_TD_REV 0x00000041
/* PCI latency timer register */
#define DC_CFLT_CACHELINESIZE 0x000000FF
#define DC_CFLT_LATENCYTIMER 0x0000FF00
/* PCI subsystem ID register */
#define DC_CSID_VENDOR 0x0000FFFF
#define DC_CSID_DEVICE 0xFFFF0000
/* PCI cababilities pointer */
#define DC_CCAP_OFFSET 0x000000FF
/* PCI interrupt config register */
#define DC_CFIT_INTLINE 0x000000FF
#define DC_CFIT_INTPIN 0x0000FF00
#define DC_CFIT_MIN_GNT 0x00FF0000
#define DC_CFIT_MAX_LAT 0xFF000000
/* PCI capability register */
#define DC_CCID_CAPID 0x000000FF
#define DC_CCID_NEXTPTR 0x0000FF00
#define DC_CCID_PM_VERS 0x00070000
#define DC_CCID_PME_CLK 0x00080000
#define DC_CCID_DVSPEC_INT 0x00200000
#define DC_CCID_STATE_D1 0x02000000
#define DC_CCID_STATE_D2 0x04000000
#define DC_CCID_PME_D0 0x08000000
#define DC_CCID_PME_D1 0x10000000
#define DC_CCID_PME_D2 0x20000000
#define DC_CCID_PME_D3HOT 0x40000000
#define DC_CCID_PME_D3COLD 0x80000000
/* PCI power management control/status register */
#define DC_CPMC_STATE 0x00000003
#define DC_CPMC_PME_ENB 0x00000100
#define DC_CPMC_PME_STS 0x00008000
#define DC_PSTATE_D0 0x0
#define DC_PSTATE_D1 0x1
#define DC_PSTATE_D2 0x2
#define DC_PSTATE_D3 0x3
/* Device specific region */
/* Configuration and driver area */
#define DC_CFDD_DRVUSE 0x0000FFFF
#define DC_CFDD_SNOOZE_MODE 0x40000000
#define DC_CFDD_SLEEP_MODE 0x80000000
/* Configuration wake-up command register */
#define DC_CWUC_MUST_BE_ZERO 0x00000001
#define DC_CWUC_SECUREON_ENB 0x00000002
#define DC_CWUC_FORCE_WUL 0x00000004
#define DC_CWUC_BNC_ABILITY 0x00000008
#define DC_CWUC_AUI_ABILITY 0x00000010
#define DC_CWUC_TP10_ABILITY 0x00000020
#define DC_CWUC_MII_ABILITY 0x00000040
#define DC_CWUC_SYM_ABILITY 0x00000080
#define DC_CWUC_LOCK 0x00000100
#ifdef __alpha__
#undef vtophys
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
#endif

1709
sys/pci/if_dm.c
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419
sys/pci/if_dmreg.h
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@ -1,419 +0,0 @@
/*
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* Davicom register definitions.
*/
#define DM_BUSCTL 0x00 /* bus control */
#define DM_TXSTART 0x08 /* tx start demand */
#define DM_RXSTART 0x10 /* rx start demand */
#define DM_RXADDR 0x18 /* rx descriptor list start addr */
#define DM_TXADDR 0x20 /* tx descriptor list start addr */
#define DM_ISR 0x28 /* interrupt status register */
#define DM_NETCFG 0x30 /* network config register */
#define DM_IMR 0x38 /* interrupt mask */
#define DM_FRAMESDISCARDED 0x40 /* # of discarded frames */
#define DM_SIO 0x48 /* MII and ROM/EEPROM access */
#define DM_RESERVED 0x50
#define DM_GENTIMER 0x58 /* general timer */
#define DM_GENPORT 0x60 /* general purpose port */
/*
* Bus control bits.
*/
#define DM_BUSCTL_RESET 0x00000001
#define DM_BUSCTL_ARBITRATION 0x00000002
#define WB_BUSCTL_SKIPLEN 0x0000007C
#define DM_BUSCTL_BIGENDIAN 0x00000080
#define DM_BUSCTL_BURSTLEN 0x00003F00
#define DM_BUSCTL_CACHEALIGN 0x0000C000
#define DM_BUSCTL_BUF_BIGENDIAN 0x00100000
#define DM_BUSCTL_READMULTI 0x00200000
#define DM_SKIPLEN_1LONG 0x00000004
#define DM_SKIPLEN_2LONG 0x00000008
#define DM_SKIPLEN_3LONG 0x00000010
#define DM_SKIPLEN_4LONG 0x00000020
#define DM_SKIPLEN_5LONG 0x00000040
#define DM_CACHEALIGN_NONE 0x00000000
#define DM_CACHEALIGN_8LONG 0x00004000
#define DM_CACHEALIGN_16LONG 0x00008000
#define DM_CACHEALIGN_32LONG 0x0000C000
#define DM_BURSTLEN_UNLIMIT 0x00000000
#define DM_BURSTLEN_1LONG 0x00000100
#define DM_BURSTLEN_2LONG 0x00000200
#define DM_BURSTLEN_4LONG 0x00000400
#define DM_BURSTLEN_8LONG 0x00000800
#define DM_BURSTLEN_16LONG 0x00001000
#define DM_BURSTLEN_32LONG 0x00002000
/*
* Interrupt status bits.
*/
#define DM_ISR_TX_OK 0x00000001
#define DM_ISR_TX_IDLE 0x00000002
#define DM_ISR_TX_NOBUF 0x00000004
#define DM_ISR_TX_JABBERTIMEO 0x00000008
#define DM_ISR_TX_UNDERRUN 0x00000020
#define DM_ISR_RX_OK 0x00000040
#define DM_ISR_RX_NOBUF 0x00000080
#define DM_ISR_RX_IDLE 0x00000100
#define DM_ISR_RX_WATDOGTIMEO 0x00000200
#define DM_ISR_TX_EARLY 0x00000400
#define DM_ISR_TIMER_EXPIRED 0x00000800
#define DM_ISR_BUS_ERR 0x00002000
#define DM_ISR_ABNORMAL 0x00008000
#define DM_ISR_NORMAL 0x00010000
#define DM_ISR_RX_STATE 0x000E0000
#define DM_ISR_TX_STATE 0x00700000
#define DM_ISR_BUSERRTYPE 0x03800000
#define DM_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
#define DM_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
#define DM_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
#define DM_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
#define DM_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
#define DM_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
#define DM_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
#define DM_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
#define DM_TXSTATE_RESET 0x00000000 /* 000 - reset */
#define DM_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
#define DM_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
#define DM_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
#define DM_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
#define DM_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
#define DM_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
#define DM_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
/*
* Network config bits.
*/
#define DM_NETCFG_LINKSTAT_PCS 0x00000001
#define DM_NETCFG_RX_ON 0x00000002
#define DM_NETCFG_RX_BADFRAMES 0x00000008
#define DM_NETCFG_RX_PROMISC 0x00000040
#define DM_NETCFG_RX_ALLMULTI 0x00000080
#define DM_NETCFG_RX_BROAD 0x00000100
#define DM_NETCFG_FULLDUPLEX 0x00000200
#define DM_NETCFG_LOOPBACK 0x00000C00
#define DM_NETCFG_FORCECOLL 0x00001000
#define DM_NETCFG_TX_ON 0x00002000
#define DM_NETCFG_TX_THRESH 0x0000C000
#define DM_NETCFG_PORTSEL 0x00040000 /* 0 == SRL, 1 == MII/SYM */
#define DM_NETCFG_HEARTBEAT 0x00080000 /* 0 == ON, 1 == OFF */
#define DM_NETCFG_STORENFWD 0x00200000
#define DM_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
#define DM_NETCFG_PCS 0x00800000
#define DM_NETCFG_SCRAMBLER 0x01000000
#define DM_NETCFG_RX_ALL 0x40000000
#define DM_OPMODE_NORM 0x00000000
#define DM_OPMODE_INTLOOP 0x00000400
#define DM_OPMODE_EXTLOOP 0x00000800
#define DM_TXTHRESH_72BYTES 0x00000000
#define DM_TXTHRESH_96BYTES 0x00004000
#define DM_TXTHRESH_128BYTES 0x00008000
#define DM_TXTHRESH_160BYTES 0x0000C000
/*
* Interrupt mask bits.
*/
#define DM_IMR_TX_OK 0x00000001
#define DM_IMR_TX_IDLE 0x00000002
#define DM_IMR_TX_NOBUF 0x00000004
#define DM_IMR_TX_JABBERTIMEO 0x00000008
#define DM_IMR_TX_UNDERRUN 0x00000020
#define DM_IMR_RX_OK 0x00000040
#define DM_IMR_RX_NOBUF 0x00000080
#define DM_IMR_RX_IDLE 0x00000100
#define DM_IMR_RX_WATDOGTIMEO 0x00000200
#define DM_IMR_TX_EARLY 0x00000400
#define DM_IMR_TIMER_EXPIRED 0x00000800
#define DM_IMR_BUS_ERR 0x00002000
#define DM_IMR_RX_EARLY 0x00004000
#define DM_IMR_ABNORMAL 0x00008000
#define DM_IMR_NORMAL 0x00010000
#define DM_INTRS \
(DM_IMR_RX_OK|DM_IMR_TX_OK|DM_IMR_RX_NOBUF|DM_IMR_RX_WATDOGTIMEO|\
DM_IMR_TX_NOBUF|DM_IMR_TX_UNDERRUN|DM_IMR_BUS_ERR| \
DM_IMR_ABNORMAL|DM_IMR_NORMAL|/*DM_IMR_TX_EARLY*/ \
DM_IMR_TX_IDLE|DM_IMR_RX_IDLE)
/*
* Serial I/O (EEPROM/ROM) bits.
*/
#define DM_SIO_EE_CS 0x00000001 /* EEPROM chip select */
#define DM_SIO_EE_CLK 0x00000002 /* EEPROM clock */
#define DM_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
#define DM_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
#define DM_SIO_EESEL 0x00000800
#define DM_SIO_ROMSEL 0x00001000
#define DM_SIO_ROMCTL_WRITE 0x00002000
#define DM_SIO_ROMCTL_READ 0x00004000
#define DM_SIO_MII_CLK 0x00010000 /* MDIO clock */
#define DM_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
#define DM_SIO_MII_DIR 0x00040000 /* MDIO dir */
#define DM_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
#define DM_EECMD_WRITE 0x140
#define DM_EECMD_READ 0x180
#define DM_EECMD_ERASE 0x1c0
#define DM_EE_NODEADDR_OFFSET 0x70
#define DM_EE_NODEADDR 10
/*
* General purpose timer register
*/
#define DM_TIMER_VALUE 0x0000FFFF
#define DM_TIMER_CONTINUOUS 0x00010000
/*
* Size of a setup frame.
*/
#define DM_SFRAME_LEN 192
/*
* Davicom TX/RX list structure.
*/
struct dm_desc {
u_int32_t dm_status;
u_int32_t dm_ctl;
u_int32_t dm_ptr1;
u_int32_t dm_ptr2;
struct mbuf *dm_mbuf;
struct dm_desc *dm_nextdesc;
};
#define dm_data dm_ptr1
#define dm_next dm_ptr2
#define DM_RXSTAT_FIFOOFLOW 0x00000001
#define DM_RXSTAT_CRCERR 0x00000002
#define DM_RXSTAT_DRIBBLE 0x00000004
#define DM_RXSTAT_WATCHDOG 0x00000010
#define DM_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
#define DM_RXSTAT_COLLSEEN 0x00000040
#define DM_RXSTAT_GIANT 0x00000080
#define DM_RXSTAT_LASTFRAG 0x00000100
#define DM_RXSTAT_FIRSTFRAG 0x00000200
#define DM_RXSTAT_MULTICAST 0x00000400
#define DM_RXSTAT_RUNT 0x00000800
#define DM_RXSTAT_RXTYPE 0x00003000
#define DM_RXSTAT_RXERR 0x00008000
#define DM_RXSTAT_RXLEN 0x3FFF0000
#define DM_RXSTAT_OWN 0x80000000
#define DM_RXBYTES(x) ((x & DM_RXSTAT_RXLEN) >> 16)
#define DM_RXSTAT (DM_RXSTAT_FIRSTFRAG|DM_RXSTAT_LASTFRAG|DM_RXSTAT_OWN)
#define DM_RXCTL_BUFLEN1 0x00000FFF
#define DM_RXCTL_BUFLEN2 0x00FFF000
#define DM_RXCTL_RLINK 0x01000000
#define DM_RXCTL_RLAST 0x02000000
#define DM_TXSTAT_DEFER 0x00000001
#define DM_TXSTAT_UNDERRUN 0x00000002
#define DM_TXSTAT_LINKFAIL 0x00000003
#define DM_TXSTAT_COLLCNT 0x00000078
#define DM_TXSTAT_SQE 0x00000080
#define DM_TXSTAT_EXCESSCOLL 0x00000100
#define DM_TXSTAT_LATECOLL 0x00000200
#define DM_TXSTAT_NOCARRIER 0x00000400
#define DM_TXSTAT_CARRLOST 0x00000800
#define DM_TXSTAT_JABTIMEO 0x00004000
#define DM_TXSTAT_ERRSUM 0x00008000
#define DM_TXSTAT_OWN 0x80000000
#define DM_TXCTL_BUFLEN1 0x000007FF
#define DM_TXCTL_BUFLEN2 0x003FF800
#define DM_TXCTL_FILTTYPE0 0x00400000
#define DM_TXCTL_PAD 0x00800000
#define DM_TXCTL_TLINK 0x01000000
#define DM_TXCTL_TLAST 0x02000000
#define DM_TXCTL_NOCRC 0x04000000
#define DM_TXCTL_SETUP 0x08000000
#define DM_TXCTL_FILTTYPE1 0x10000000
#define DM_TXCTL_FIRSTFRAG 0x20000000
#define DM_TXCTL_LASTFRAG 0x40000000
#define DM_TXCTL_FINT 0x80000000
#define DM_FILTER_PERFECT 0x00000000
#define DM_FILTER_HASHPERF 0x00400000
#define DM_FILTER_INVERSE 0x10000000
#define DM_FILTER_HASHONLY 0x10400000
#define DM_MAXFRAGS 16
#define DM_RX_LIST_CNT 64
#define DM_TX_LIST_CNT 128
#define DM_MIN_FRAMELEN 60
#define DM_RXLEN 1536
#define DM_INC(x, y) (x) = (x + 1) % y
struct dm_list_data {
struct dm_desc dm_rx_list[DM_RX_LIST_CNT];
struct dm_desc dm_tx_list[DM_TX_LIST_CNT];
struct dm_desc dm_sframe;
};
struct dm_chain_data {
u_int32_t dm_sbuf[DM_SFRAME_LEN/sizeof(u_int32_t)];
u_int8_t dm_pad[DM_MIN_FRAMELEN];
int dm_tx_prod;
int dm_tx_cons;
int dm_tx_cnt;
int dm_rx_prod;
};
struct dm_type {
u_int16_t dm_vid;
u_int16_t dm_did;
char *dm_name;
};
struct dm_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define DM_MII_STARTDELIM 0x01
#define DM_MII_READOP 0x02
#define DM_MII_WRITEOP 0x01
#define DM_MII_TURNAROUND 0x02
struct dm_softc {
struct arpcom arpcom; /* interface info */
bus_space_handle_t dm_bhandle; /* bus space handle */
bus_space_tag_t dm_btag; /* bus space tag */
void *dm_intrhand;
struct resource *dm_irq;
struct resource *dm_res;
device_t dm_miibus;
u_int8_t dm_unit; /* interface number */
int dm_cachesize;
struct dm_list_data *dm_ldata;
struct dm_chain_data dm_cdata;
struct callout_handle dm_stat_ch;
};
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->dm_btag, sc->dm_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->dm_btag, sc->dm_bbhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->dm_btag, sc->dm_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->dm_btag, sc->dm_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->dm_btag, sc->dm_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->dm_btag, sc->dm_bhandle, reg)
#define DM_TIMEOUT 1000
#define ETHER_ALIGN 2
/*
* General constants that are fun to know.
*
* Davicom PCI vendor ID
*/
#define DM_VENDORID 0x1282
/*
* Davicom DM9102 device ID.
*/
#define DM_DEVICEID_DM9102 0x9102
#define DM_DEVICEID_DM9100 0x9100
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define DM_PCI_VENDOR_ID 0x00
#define DM_PCI_DEVICE_ID 0x02
#define DM_PCI_COMMAND 0x04
#define DM_PCI_STATUS 0x06
#define DM_PCI_REVID 0x08
#define DM_PCI_CLASSCODE 0x09
#define DM_PCI_CACHELEN 0x0C
#define DM_PCI_LATENCY_TIMER 0x0D
#define DM_PCI_HEADER_TYPE 0x0E
#define DM_PCI_LOIO 0x10
#define DM_PCI_LOMEM 0x14
#define DM_PCI_BIOSROM 0x30
#define DM_PCI_INTLINE 0x3C
#define DM_PCI_INTPIN 0x3D
#define DM_PCI_MINGNT 0x3E
#define DM_PCI_MINLAT 0x0F
#define DM_PCI_RESETOPT 0x48
#define DM_PCI_EEPROM_DATA 0x4C
/* power management registers */
#define DM_PCI_CAPID 0x50 /* 8 bits */
#define DM_PCI_NEXTPTR 0x51 /* 8 bits */
#define DM_PCI_PWRMGMTCAP 0x52 /* 16 bits */
#define DM_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
#define DM_PSTATE_MASK 0x0003
#define DM_PSTATE_D0 0x0000
#define DM_PSTATE_D1 0x0001
#define DM_PSTATE_D2 0x0002
#define DM_PSTATE_D3 0x0003
#define DM_PME_EN 0x0010
#define DM_PME_STATUS 0x8000
#ifdef __alpha__
#undef vtophys
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
#endif

1992
sys/pci/if_mx.c
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sys/pci/if_mxreg.h
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/*
* Copyright (c) 1997, 1998
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* Macronix register definitions.
*/
#define MX_BUSCTL 0x00 /* bus control */
#define MX_TXSTART 0x08 /* tx start demand */
#define MX_RXSTART 0x10 /* rx start demand */
#define MX_RXADDR 0x18 /* rx descriptor list start addr */
#define MX_TXADDR 0x20 /* tx descriptor list start addr */
#define MX_ISR 0x28 /* interrupt status register */
#define MX_NETCFG 0x30 /* network config register */
#define MX_IMR 0x38 /* interrupt mask */
#define MX_FRAMESDISCARDED 0x40 /* # of discarded frames */
#define MX_SIO 0x48 /* MII and ROM/EEPROM access */
#define MX_RESERVED 0x50
#define MX_TIMER 0x58 /* general timer */
#define MX_10BTSTAT 0x60
#define MX_SIARESET 0x68
#define MX_10BTCTRL 0x70
#define MX_WATCHDOG 0x78
#define MX_MAGICPACKET 0x80
#define MX_NWAYSTAT 0xA0
/*
* These are magic values that must be written into CSR16
* (MX_MAGICPACKET) in order to put the chip into proper
* operating mode. The magic numbers are documented in the
* Macronix 98715 application notes.
*/
#define MX_MAGIC_98713 0x0F370000
#define MX_MAGIC_98713A 0x0B3C0000
#define MX_MAGIC_98715 0x0B3C0000
#define MX_MAGIC_98725 0x0B3C0000
#define MX_REVISION_98713 0x00
#define MX_REVISION_98713A 0x10
#define MX_REVISION_98715 0x20
#define MX_REVISION_98725 0x30
/*
* As far as the driver is concerned, there are two 'types' of
* chips to be concerned with. One is a 98713 with an external
* PHY on the MII. The other covers pretty much everything else,
* since all the other Macronix chips have built-in transceivers.
* This type setting governs what which mode selection routines
* we use (MII or built-in). It also govers which of the 'magic'
* numbers we write into CSR16.
*/
#define MX_TYPE_98713 0x1
#define MX_TYPE_98713A 0x2
#define MX_TYPE_987x5 0x3
/*
* Bus control bits.
*/
#define MX_BUSCTL_RESET 0x00000001
#define MX_BUSCTL_ARBITRATION 0x00000002
#define MX_BUSCTL_SKIPLEN 0x0000007C
#define MX_BUSCTL_BUF_BIGENDIAN 0x00000080
#define MX_BUSCTL_BURSTLEN 0x00003F00
#define MX_BUSCTL_CACHEALIGN 0x0000C000
#define MX_BUSCTL_TXPOLL 0x000E0000
#define MX_BUSCTL_MUSTBEONE 0x04000000
#define MX_SKIPLEN_1LONG 0x00000004
#define MX_SKIPLEN_2LONG 0x00000008
#define MX_SKIPLEN_3LONG 0x00000010
#define MX_SKIPLEN_4LONG 0x00000020
#define MX_SKIPLEN_5LONG 0x00000040
#define MX_CACHEALIGN_NONE 0x00000000
#define MX_CACHEALIGN_8LONG 0x00004000
#define MX_CACHEALIGN_16LONG 0x00008000
#define MX_CACHEALIGN_32LONG 0x0000C000
#define MX_BURSTLEN_USECA 0x00000000
#define MX_BURSTLEN_1LONG 0x00000100
#define MX_BURSTLEN_2LONG 0x00000200
#define MX_BURSTLEN_4LONG 0x00000400
#define MX_BURSTLEN_8LONG 0x00000800
#define MX_BURSTLEN_16LONG 0x00001000
#define MX_BURSTLEN_32LONG 0x00002000
#define MX_TXPOLL_OFF 0x00000000
#define MX_TXPOLL_200U 0x00020000
#define MX_TXPOLL_800U 0x00040000
#define MX_TXPOLL_1600U 0x00060000
#define MX_BUSCTL_CONFIG (MX_BUSCTL_ARBITRATION|MX_CACHEALIGN_8LONG| \
MX_BURSTLEN_8LONG)
/*
* Interrupt status bits.
*/
#define MX_ISR_TX_OK 0x00000001
#define MX_ISR_TX_IDLE 0x00000002
#define MX_ISR_TX_NOBUF 0x00000004
#define MX_ISR_TX_JABBERTIMEO 0x00000008
#define MX_ISR_LINKGOOD 0x00000010
#define MX_ISR_TX_UNDERRUN 0x00000020
#define MX_ISR_RX_OK 0x00000040
#define MX_ISR_RX_NOBUF 0x00000080
#define MX_ISR_RX_READ 0x00000100
#define MX_ISR_RX_WATDOGTIMEO 0x00000200
#define MX_ISR_TX_EARLY 0x00000400
#define MX_ISR_TIMER_EXPIRED 0x00000800
#define MX_ISR_LINKFAIL 0x00001000
#define MX_ISR_BUS_ERR 0x00002000
#define MX_ISR_RX_EARLY 0x00004000
#define MX_ISR_ABNORMAL 0x00008000
#define MX_ISR_NORMAL 0x00010000
#define MX_ISR_RX_STATE 0x000E0000
#define MX_ISR_TX_STATE 0x00700000
#define MX_ISR_BUSERRTYPE 0x03800000
#define MX_ISR_100MBPSLINK 0x08000000
#define MX_ISR_MAGICKPACK 0x10000000
#define MX_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
#define MX_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
#define MX_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
#define MX_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
#define MX_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
#define MX_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
#define MX_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
#define MX_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
#define MX_TXSTATE_RESET 0x00000000 /* 000 - reset */
#define MX_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
#define MX_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
#define MX_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
#define MX_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
#define MX_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
#define MX_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
#define MX_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
/*
* Network config bits.
*/
#define MX_NETCFG_RX_HASHPERF 0x00000001
#define MX_NETCFG_RX_ON 0x00000002
#define MX_NETCFG_RX_HASHONLY 0x00000004
#define MX_NETCFG_RX_BADFRAMES 0x00000008
#define MX_NETCFG_RX_INVFILT 0x00000010
#define MX_NETCFG_BACKOFFCNT 0x00000020
#define MX_NETCFG_RX_PROMISC 0x00000040
#define MX_NETCFG_RX_ALLMULTI 0x00000080
#define MX_NETCFG_FULLDUPLEX 0x00000200
#define MX_NETCFG_LOOPBACK 0x00000C00
#define MX_NETCFG_FORCECOLL 0x00001000
#define MX_NETCFG_TX_ON 0x00002000
#define MX_NETCFG_TX_THRESH 0x0000C000
#define MX_NETCFG_TX_BACKOFF 0x00020000
#define MX_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
#define MX_NETCFG_HEARTBEAT 0x00080000
#define MX_NETCFG_STORENFWD 0x00200000
#define MX_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
#define MX_NETCFG_PCS 0x00800000
#define MX_NETCFG_SCRAMBLER 0x01000000
#define MX_NETCFG_NO_RXCRC 0x02000000
#define MX_OPMODE_NORM 0x00000000
#define MX_OPMODE_INTLOOP 0x00000400
#define MX_OPMODE_EXTLOOP 0x00000800
#define MX_TXTHRESH_72BYTES 0x00000000
#define MX_TXTHRESH_96BYTES 0x00004000
#define MX_TXTHRESH_128BYTES 0x00008000
#define MX_TXTHRESH_160BYTES 0x0000C000
/*
* Interrupt mask bits.
*/
#define MX_IMR_TX_OK 0x00000001
#define MX_IMR_TX_IDLE 0x00000002
#define MX_IMR_TX_NOBUF 0x00000004
#define MX_IMR_TX_JABBERTIMEO 0x00000008
#define MX_IMR_LINKGOOD 0x00000010
#define MX_IMR_TX_UNDERRUN 0x00000020
#define MX_IMR_RX_OK 0x00000040
#define MX_IMR_RX_NOBUF 0x00000080
#define MX_IMR_RX_READ 0x00000100
#define MX_IMR_RX_WATDOGTIMEO 0x00000200
#define MX_IMR_TX_EARLY 0x00000400
#define MX_IMR_TIMER_EXPIRED 0x00000800
#define MX_IMR_LINKFAIL 0x00001000
#define MX_IMR_BUS_ERR 0x00002000
#define MX_IMR_RX_EARLY 0x00004000
#define MX_IMR_ABNORMAL 0x00008000
#define MX_IMR_NORMAL 0x00010000
#define MX_IMR_100MBPSLINK 0x08000000
#define MX_IMR_MAGICKPACK 0x10000000
#define MX_INTRS \
(MX_IMR_RX_OK|MX_IMR_TX_OK|MX_IMR_RX_NOBUF|MX_IMR_RX_WATDOGTIMEO|\
MX_IMR_TX_NOBUF|MX_IMR_TX_UNDERRUN|MX_IMR_BUS_ERR| \
MX_IMR_ABNORMAL|MX_IMR_NORMAL/*|MX_IMR_TX_EARLY*/)
/*
* Serial I/O (EEPROM/ROM) bits.
*/
#define MX_SIO_EE_CS 0x00000001 /* EEPROM chip select */
#define MX_SIO_EE_CLK 0x00000002 /* EEPROM clock */
#define MX_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
#define MX_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
#define MX_SIO_ROMDATA4 0x00000010
#define MX_SIO_ROMDATA5 0x00000020
#define MX_SIO_ROMDATA6 0x00000040
#define MX_SIO_ROMDATA7 0x00000080
#define MX_SIO_EESEL 0x00000800
#define MX_SIO_ROMSEL 0x00001000
#define MX_SIO_ROMCTL_WRITE 0x00002000
#define MX_SIO_ROMCTL_READ 0x00004000
#define MX_SIO_MII_CLK 0x00010000 /* MDIO clock */
#define MX_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
#define MX_SIO_MII_DIR 0x00040000 /* MDIO dir */
#define MX_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
#define MX_EECMD_WRITE 0x140
#define MX_EECMD_READ 0x180
#define MX_EECMD_ERASE 0x1c0
#define MX_EE_NODEADDR_OFFSET 0x70
#define MX_EE_NODEADDR 10
/*
* General purpose timer register
*/
#define MX_TIMER_VALUE 0x0000FFFF
#define MX_TIMER_CONTINUUS 0x00010000
/*
* 10baseT status register
*/
#define MX_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
#define MX_TSTAT_LS10 0x00000004 /* link status of 10baseT */
#define MX_TSTAT_AUTOPOLARITY 0x00000008
#define MX_TSTAT_REMFAULT 0x00000800
#define MX_TSTAT_ANEGSTAT 0x00007000
#define MX_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
#define MX_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
#define MX_ASTAT_DISABLE 0x00000000
#define MX_ASTAT_TXDISABLE 0x00001000
#define MX_ASTAT_ABDETECT 0x00002000
#define MX_ASTAT_ACKDETECT 0x00003000
#define MX_ASTAT_CMPACKDETECT 0x00004000
#define MX_ASTAT_AUTONEGCMP 0x00005000
#define MX_ASTAT_LINKCHECK 0x00006000
/*
* PHY reset register
*/
#define MX_SIA_RESET_NWAY 0x00000001
#define MX_SIA_RESET_100TX 0x00000002
/*
* 10baseT control register
*/
#define MX_TCTL_LOOPBACK 0x00000002
#define MX_TCTL_POWERDOWN 0x00000004
#define MX_TCTL_HALFDUPLEX 0x00000040
#define MX_TCTL_AUTONEGENBL 0x00000080
#define MX_TCTL_RX_SQUELCH 0x00000100
#define MX_TCTL_LINKTEST 0x00001000
#define MX_TCTL_100BTXHALF 0x00010000
#define MX_TCTL_100BTXFULL 0x00020000
#define MX_TCTL_100BT4 0x00040000
/*
* Watchdog timer register
*/
#define MX_WDOG_JABBERDIS 0x00000001
#define MX_WDOG_HOSTUNJAB 0x00000002
#define MX_WDOG_JABBERCLK 0x00000004
#define MX_WDOG_RXWDOGDIS 0x00000010
#define MX_WDOG_RXWDOGCLK 0x00000020
#define MX_WDOG_MUSTBEZERO 0x00000100
/*
* Magic packet register
*/
#define MX_MPACK_DISABLE 0x00400000
/*
* NWAY status register.
*/
#define MX_NWAY_10BTHALF 0x08000000
#define MX_NWAY_10BTFULL 0x10000000
#define MX_NWAY_100BTHALF 0x20000000
#define MX_NWAY_100BTFULL 0x40000000
#define MX_NWAY_100BT4 0x80000000
/*
* Size of a setup frame.
*/
#define MX_SFRAME_LEN 192
/*
* Macronix TX/RX list structure.
*/
struct mx_desc {
u_int32_t mx_status;
u_int32_t mx_ctl;
u_int32_t mx_ptr1;
u_int32_t mx_ptr2;
};
#define mx_data mx_ptr1
#define mx_next mx_ptr2
#define MX_RXSTAT_FIFOOFLOW 0x00000001
#define MX_RXSTAT_CRCERR 0x00000002
#define MX_RXSTAT_DRIBBLE 0x00000004
#define MX_RXSTAT_WATCHDOG 0x00000010
#define MX_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
#define MX_RXSTAT_COLLSEEN 0x00000040
#define MX_RXSTAT_GIANT 0x00000080
#define MX_RXSTAT_LASTFRAG 0x00000100
#define MX_RXSTAT_FIRSTFRAG 0x00000200
#define MX_RXSTAT_MULTICAST 0x00000400
#define MX_RXSTAT_RUNT 0x00000800
#define MX_RXSTAT_RXTYPE 0x00003000
#define MX_RXSTAT_RXERR 0x00008000
#define MX_RXSTAT_RXLEN 0x3FFF0000
#define MX_RXSTAT_OWN 0x80000000
#define MX_RXBYTES(x) ((x & MX_RXSTAT_RXLEN) >> 16)
#define MX_RXSTAT (MX_RXSTAT_FIRSTFRAG|MX_RXSTAT_LASTFRAG|MX_RXSTAT_OWN)
#define MX_RXCTL_BUFLEN1 0x00000FFF
#define MX_RXCTL_BUFLEN2 0x00FFF000
#define MX_RXCTL_RLINK 0x01000000
#define MX_RXCTL_RLAST 0x02000000
#define MX_TXSTAT_DEFER 0x00000001
#define MX_TXSTAT_UNDERRUN 0x00000002
#define MX_TXSTAT_LINKFAIl 0x00000003
#define MX_TXSTAT_COLLCNT 0x00000078
#define MX_TXSTAT_SQE 0x00000080
#define MX_TXSTAT_EXCESSCOLL 0x00000100
#define MX_TXSTAT_LATECOLL 0x00000200
#define MX_TXSTAT_NOCARRIER 0x00000400
#define MX_TXSTAT_CARRLOST 0x00000800
#define MX_TXSTAT_JABTIMEO 0x00004000
#define MX_TXSTAT_ERRSUM 0x00008000
#define MX_TXSTAT_OWN 0x80000000
#define MX_TXCTL_BUFLEN1 0x000007FF
#define MX_TXCTL_BUFLEN2 0x003FF800
#define MX_TXCTL_FILTTYPE0 0x00400000
#define MX_TXCTL_PAD 0x00800000
#define MX_TXCTL_TLINK 0x01000000
#define MX_TXCTL_TLAST 0x02000000
#define MX_TXCTL_NOCRC 0x04000000
#define MX_TXCTL_SETUP 0x08000000
#define MX_TXCTL_FILTTYPE1 0x10000000
#define MX_TXCTL_FIRSTFRAG 0x20000000
#define MX_TXCTL_LASTFRAG 0x40000000
#define MX_TXCTL_FINT 0x80000000
#define MX_FILTER_PERFECT 0x00000000
#define MX_FILTER_HASHPERF 0x00400000
#define MX_FILTER_INVERSE 0x10000000
#define MX_FILTER_HASHONLY 0x10400000
#define MX_MAXFRAGS 16
#define MX_RX_LIST_CNT 64
#define MX_TX_LIST_CNT 128
#define MX_MIN_FRAMELEN 60
/*
* A tx 'super descriptor' is actually 16 regular descriptors
* back to back.
*/
struct mx_txdesc {
struct mx_desc mx_frag[MX_MAXFRAGS];
};
#define MX_TXNEXT(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_next
#define MX_TXSTATUS(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_status
#define MX_TXCTL(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_ctl
#define MX_TXDATA(x) x->mx_ptr->mx_frag[x->mx_lastdesc].mx_data
#define MX_TXOWN(x) x->mx_ptr->mx_frag[0].mx_status
struct mx_list_data {
struct mx_desc mx_rx_list[MX_RX_LIST_CNT];
struct mx_txdesc mx_tx_list[MX_TX_LIST_CNT];
};
struct mx_chain {
struct mx_txdesc *mx_ptr;
struct mbuf *mx_mbuf;
struct mx_chain *mx_nextdesc;
u_int8_t mx_lastdesc;
};
struct mx_chain_onefrag {
struct mx_desc *mx_ptr;
struct mbuf *mx_mbuf;
struct mx_chain_onefrag *mx_nextdesc;
};
struct mx_chain_data {
struct mx_desc mx_sframe;
u_int32_t mx_sbuf[MX_SFRAME_LEN/sizeof(u_int32_t)];
u_int8_t mx_pad[MX_MIN_FRAMELEN];
struct mx_chain_onefrag mx_rx_chain[MX_RX_LIST_CNT];
struct mx_chain mx_tx_chain[MX_TX_LIST_CNT];
struct mx_chain_onefrag *mx_rx_head;
struct mx_chain *mx_tx_head;
struct mx_chain *mx_tx_tail;
struct mx_chain *mx_tx_free;
};
struct mx_type {
u_int16_t mx_vid;
u_int16_t mx_did;
char *mx_name;
};
struct mx_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define MX_MII_STARTDELIM 0x01
#define MX_MII_READOP 0x02
#define MX_MII_WRITEOP 0x01
#define MX_MII_TURNAROUND 0x02
#define MX_FLAG_FORCEDELAY 1
#define MX_FLAG_SCHEDDELAY 2
#define MX_FLAG_DELAYTIMEO 3
struct mx_softc {
struct arpcom arpcom; /* interface info */
bus_space_handle_t mx_bhandle; /* bus space handle */
bus_space_tag_t mx_btag; /* bus space tag */
void *mx_intrhand;
struct resource *mx_irq;
struct resource *mx_res;
device_t mx_miibus;
struct mx_type *mx_info; /* Macronix adapter info */
u_int8_t mx_unit; /* interface number */
u_int8_t mx_type;
u_int8_t mx_cachesize;
u_int8_t mx_link;
int mx_if_flags;
caddr_t mx_ldata_ptr;
struct mx_list_data *mx_ldata;
struct mx_chain_data mx_cdata;
struct callout_handle mx_stat_ch;
};
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->mx_btag, sc->mx_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->mx_btag, sc->mx_bhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->mx_btag, sc->mx_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->mx_btag, sc->mx_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->mx_btag, sc->mx_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->mx_btag, sc->mx_bhandle, reg)
#define MX_TIMEOUT 1000
#define ETHER_ALIGN 2
/*
* General constants that are fun to know.
*
* Macronix PCI vendor ID
*/
#define MX_VENDORID 0x10D9
/*
* Macronix PMAC device IDs.
*/
#define MX_DEVICEID_98713 0x0512
#define MX_DEVICEID_987x5 0x0531
/*
* Compex PCI vendor ID.
*/
#define CP_VENDORID 0x11F6
/*
* Compex PMAC PCI device IDs.
*/
#define CP_DEVICEID_98713 0x9881
/*
* Lite-On PNIC PCI vendor ID
*/
#define PN_VENDORID 0x11AD
/*
* Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A
* with wake on lan/magic packet support.
*/
#define PN_DEVICEID_PNIC_II 0xc115
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define MX_PCI_VENDOR_ID 0x00
#define MX_PCI_DEVICE_ID 0x02
#define MX_PCI_COMMAND 0x04
#define MX_PCI_STATUS 0x06
#define MX_PCI_REVID 0x08
#define MX_PCI_CLASSCODE 0x09
#define MX_PCI_CACHELEN 0x0C
#define MX_PCI_LATENCY_TIMER 0x0D
#define MX_PCI_HEADER_TYPE 0x0E
#define MX_PCI_LOIO 0x10
#define MX_PCI_LOMEM 0x14
#define MX_PCI_BIOSROM 0x30
#define MX_PCI_INTLINE 0x3C
#define MX_PCI_INTPIN 0x3D
#define MX_PCI_MINGNT 0x3E
#define MX_PCI_MINLAT 0x0F
#define MX_PCI_RESETOPT 0x48
#define MX_PCI_EEPROM_DATA 0x4C
/* power management registers */
#define MX_PCI_CAPID 0x44 /* 8 bits */
#define MX_PCI_NEXTPTR 0x45 /* 8 bits */
#define MX_PCI_PWRMGMTCAP 0x46 /* 16 bits */
#define MX_PCI_PWRMGMTCTRL 0x48 /* 16 bits */
#define MX_PSTATE_MASK 0x0003
#define MX_PSTATE_D0 0x0000
#define MX_PSTATE_D1 0x0001
#define MX_PSTATE_D2 0x0002
#define MX_PSTATE_D3 0x0003
#define MX_PME_EN 0x0010
#define MX_PME_STATUS 0x8000
#ifdef __alpha__
#undef vtophys
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
#endif

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sys/pci/if_pn.c
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sys/pci/if_pnreg.h
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/*
* Copyright (c) 1997, 1998
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* PNIC register definitions.
*/
#define PN_BUSCTL 0x00 /* bus control */
#define PN_TXSTART 0x08 /* tx start demand */
#define PN_RXSTART 0x10 /* rx start demand */
#define PN_RXADDR 0x18 /* rx descriptor list start addr */
#define PN_TXADDR 0x20 /* tx descriptor list start addr */
#define PN_ISR 0x28 /* interrupt status register */
#define PN_NETCFG 0x30 /* network config register */
#define PN_IMR 0x38 /* interrupt mask */
#define PN_FRAMESDISCARDED 0x40 /* # of discarded frames */
#define PN_SIO 0x48 /* MII and ROM/EEPROM access */
#define PN_GEN 0x60 /* general purpose register */
#define PN_ENDEC 0x78 /* ENDEC general register */
#define PN_SIOPWR 0x90 /* serial eeprom power up */
#define PN_SIOCTL 0x98 /* EEPROM control register */
#define PN_MII 0xA0 /* MII access register */
#define PN_NWAY 0xB8 /* Internal NWAY register */
/*
* Bus control bits.
*/
#define PN_BUSCTL_RESET 0x00000001
#define PN_BUSCTL_ARBITRATION 0x00000002
#define PN_BUSCTL_SKIPLEN 0x0000007C
#define PN_BUSCTL_BUF_BIGENDIAN 0x00000080
#define PN_BUSCTL_BURSTLEN 0x00003F00
#define PN_BUSCTL_CACHEALIGN 0x0000C000
#define PN_BUSCTL_TXPOLL 0x000E0000
#define PN_BUSCTL_MUSTBEONE 0x04000000
#define PN_SKIPLEN_1LONG 0x00000004
#define PN_SKIPLEN_2LONG 0x00000008
#define PN_SKIPLEN_3LONG 0x00000010
#define PN_SKIPLEN_4LONG 0x00000020
#define PN_SKIPLEN_5LONG 0x00000040
#define PN_CACHEALIGN_NONE 0x00000000
#define PN_CACHEALIGN_8LONG 0x00004000
#define PN_CACHEALIGN_16LONG 0x00008000
#define PN_CACHEALIGN_32LONG 0x0000C000
#define PN_BURSTLEN_USECA 0x00000000
#define PN_BURSTLEN_1LONG 0x00000100
#define PN_BURSTLEN_2LONG 0x00000200
#define PN_BURSTLEN_4LONG 0x00000400
#define PN_BURSTLEN_8LONG 0x00000800
#define PN_BURSTLEN_16LONG 0x00001000
#define PN_BURSTLEN_32LONG 0x00002000
#define PN_TXPOLL_OFF 0x00000000
#define PN_TXPOLL_200U 0x00020000
#define PN_TXPOLL_800U 0x00040000
#define PN_TXPOLL_1600U 0x00060000
#define PN_TXPOLL_12_8M 0x00080000
#define PN_TXPOLL_25_6M 0x000A0000
#define PN_TXPOLL_51_2M 0x000C0000
#define PN_TXPOLL_102_4M 0x000E0000
#define PN_BUSCTL_CONFIG \
(PN_CACHEALIGN_8LONG|PN_BURSTLEN_8LONG)
/*
* Interrupt status bits.
*/
#define PN_ISR_TX_OK 0x00000001 /* packet tx ok */
#define PN_ISR_TX_IDLE 0x00000002 /* tx stopped */
#define PN_ISR_TX_NOBUF 0x00000004 /* no tx buffer available */
#define PN_ISR_TX_JABTIMEO 0x00000008 /* jabber timeout */
#define PN_ISR_LINKPASS 0x00000010 /* link test pass */
#define PN_ISR_TX_UNDERRUN 0x00000020 /* transmit underrun */
#define PN_ISR_RX_OK 0x00000040 /* packet rx ok */
#define PN_ISR_RX_NOBUF 0x00000080 /* rx buffer unavailable */
#define PN_ISR_RX_IDLE 0x00000100 /* rx stopped */
#define PN_ISR_RX_WATCHDOG 0x00000200 /* rx watchdog timeo */
#define PN_ISR_TX_EARLY 0x00000400 /* rx watchdog timeo */
#define PN_ISR_LINKFAIL 0x00001000
#define PN_ISR_BUS_ERR 0x00002000
#define PN_ISR_ABNORMAL 0x00008000
#define PN_ISR_NORMAL 0x00010000
#define PN_ISR_RX_STATE 0x000E0000
#define PN_ISR_TX_STATE 0x00700000
#define PN_ISR_BUSERRTYPE 0x03800000
#define PN_ISR_TXABORT 0x04000000 /* tx abort */
#define PN_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
#define PN_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
#define PN_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
#define PN_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
#define PN_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
#define PN_RXSTATE_CLOSE 0x000A0000 /* 101 - close rx desc */
#define PN_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
#define PN_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
#define PN_TXSTATE_RESET 0x00000000 /* 000 - reset */
#define PN_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
#define PN_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
#define PN_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
#define PN_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
#define PN_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
#define PN_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
#define PN_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
#define PN_BUSERR_PARITY 0x00000000
#define PN_BUSERR_MASTABRT 0x00800000
#define PN_BUSERR_TGTABRT 0x01000000
#define PN_BUSERR_RSVD1 0x01800000
#define PN_BUSERR_RSVD2 0x02000000
/*
* Network config bits.
*/
#define PN_NETCFG_HASHPERF 0x00000001 /* 0 == perf, 1 == hash */
#define PN_NETCFG_RX_ON 0x00000002
#define PN_NETCFG_HASHONLY 0x00000004 /* 1 == allhash */
#define PN_NETCFG_RX_PASSERR 0x00000008
#define PN_NETCFG_INVERSFILT 0x00000010
#define PN_NETCFG_BACKOFF 0x00000020
#define PN_NETCFG_RX_PROMISC 0x00000040
#define PN_NETCFG_RX_ALLMULTI 0x00000080
#define PN_NETCFG_FLAKYOSC 0x00000100
#define PN_NETCFG_FULLDUPLEX 0x00000200
#define PN_NETCFG_OPERMODE 0x00000C00
#define PN_NETCFG_FORCECOLL 0x00001000
#define PN_NETCFG_TX_ON 0x00002000
#define PN_NETCFG_TX_THRESH 0x0000C000
#define PN_NETCFG_TX_BACKOFF 0x00020000
#define PN_NETCFG_MIIENB 0x00040000 /* 1 == MII, 0 == internal */
#define PN_NETCFG_HEARTBEAT 0x00080000 /* 1 == disabled */
#define PN_NETCFG_TX_IMMEDIATE 0x00100000
#define PN_NETCFG_STORENFWD 0x00200000
#define PN_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10Mbps 0 == 100Mbps */
#define PN_NETCFG_PCS 0x00800000 /* 1 == 100baseTX */
#define PN_NETCFG_SCRAMBLER 0x01000000
#define PN_NETCFG_NO_RXCRC 0x20000000
#define PN_NETCFG_EXT_ENDEC 0x40000000 /* 1 == ext, 0 == int PHY */
#define PN_OPMODE_NORM 0x00000000
#define PN_OPMODE_INTLOOP 0x00000400
#define PN_OPMODE_EXTLOOP 0x00000800
#define PN_TXTHRESH_72BYTES 0x00000000
#define PN_TXTHRESH_96BYTES 0x00004000
#define PN_TXTHRESH_128BYTES 0x00008000
#define PN_TXTHRESH_160BYTES 0x0000C000
/*
* Interrupt mask bits.
*/
#define PN_IMR_TX_OK 0x00000001 /* packet tx ok */
#define PN_IMR_TX_IDLE 0x00000002 /* tx stopped */
#define PN_IMR_TX_NOBUF 0x00000004 /* no tx buffer available */
#define PN_IMR_TX_JABTIMEO 0x00000008 /* jabber timeout */
#define PN_IMR_LINKPASS 0x00000010 /* link test pass */
#define PN_IMR_TX_UNDERRUN 0x00000020 /* transmit underrun */
#define PN_IMR_RX_OK 0x00000040 /* packet rx ok */
#define PN_IMR_RX_NOBUF 0x00000080 /* rx buffer unavailable */
#define PN_IMR_RX_IDLE 0x00000100 /* rx stopped */
#define PN_IMR_RX_WATCHDOG 0x00000200 /* rx watchdog timeo */
#define PN_IMR_TX_EARLY 0x00000400 /* rx watchdog timeo */
#define PN_IMR_BUS_ERR 0x00002000
#define PN_IMR_ABNORMAL 0x00008000
#define PN_IMR_NORMAL 0x00010000
#define PN_ISR_TXABORT 0x04000000 /* tx abort */
#define PN_INTRS \
(PN_IMR_RX_OK|PN_IMR_TX_OK|PN_IMR_RX_NOBUF| \
PN_IMR_TX_NOBUF|PN_IMR_TX_UNDERRUN|PN_IMR_BUS_ERR| \
PN_IMR_ABNORMAL|PN_IMR_NORMAL)
/*
* Serial I/O (EEPROM/ROM) bits.
*/
#define PN_SIO_DATA 0x0000003F
#define PN_SIO_OPCODE 0x00000300
#define PN_SIO_BUSY 0x80000000
/*
* SIOCTL/EEPROM bits
*/
#define PN_EE_READ 0x600
/*
* General purpose register bits.
*/
#define PN_GEN_CTL 0x000000F0
#define PN_GEN_100TX_LINK 0x00000008
#define PN_GEN_BNC_ENB 0x00000004
#define PN_GEN_100TX_LOOP 0x00000002 /* 1 == normal, 0 == loop */
#define PN_GEN_SPEEDSEL 0x00000001 /* 1 == 100Mbps, 0 == 10Mbps */
#define PN_GEN_MUSTBEONE 0x00000030
/*
* General ENDEC bits.
*/
#define PN_ENDEC_JABBERDIS 0x000000001 /* 1 == disable, 0 == enable */
/*
* MII bits.
*/
#define PN_MII_DATA 0x0000FFFF
#define PN_MII_REGADDR 0x007C0000
#define PN_MII_PHYADDR 0x0F800000
#define PN_MII_OPCODE 0x30000000
#define PN_MII_RESERVED 0x00020000
#define PN_MII_BUSY 0x80000000
#define PN_MII_READ 0x60020000 /* read PHY command */
#define PN_MII_WRITE 0x50020000 /* write PHY command */
/*
* Internal PHY NWAY register bits.
*/
#define PN_NWAY_RESET 0x00000001 /* reset */
#define PN_NWAY_PDOWN 0x00000002 /* power down */
#define PN_NWAY_BYPASS 0x00000004 /* bypass */
#define PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */
#define PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */
#define PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */
#define PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */
#define PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */
#define PN_NWAY_DUPLEX 0x00000100 /* 1 == full, 0 == half */
#define PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */
#define PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */
#define PN_NWAY_SPEEDSEL 0x00000800 /* 0 == 10, 1 == 100 */
#define PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */
#define PN_NWAY_CAP10HALF 0x00002000
#define PN_NWAY_CAP10FULL 0x00004000
#define PN_NWAY_CAP100FULL 0x00008000
#define PN_NWAY_CAP100HALF 0x00010000
#define PN_NWAY_CAP100T4 0x00020000
#define PN_NWAY_AUTONEGRSTR 0x02000000
#define PN_NWAY_REMFAULT 0x04000000
#define PN_NWAY_LPAR10HALF 0x08000000
#define PN_NWAY_LPAR10FULL 0x10000000
#define PN_NWAY_LPAR100FULL 0x20000000
#define PN_NWAY_LPAR100HALF 0x40000000
#define PN_NWAY_LPAR100T4 0x80000000
/*
* Nway register bits that must be set to turn on to initiate
* an autoneg session with all modes advertized and AUI disabled.
*/
#define PN_NWAY_AUTOENB \
(PN_NWAY_AUILOWCUR|PN_NWAY_TPEXTEND|PN_NWAY_POLARITY|PN_NWAY_TP \
|PN_NWAY_NWAY_ENB|PN_NWAY_CAP10HALF|PN_NWAY_CAP10FULL| \
PN_NWAY_CAP100FULL|PN_NWAY_CAP100HALF|PN_NWAY_CAP100T4| \
PN_NWAY_AUTONEGRSTR)
#define PN_NWAY_MODE_10HD \
(PN_NWAY_CAP10HALF|PN_NWAY_CAP10FULL| \
PN_NWAY_CAP100FULL|PN_NWAY_CAP100HALF|PN_NWAY_CAP100T4| \
PN_NWAY_AUILOWCUR|PN_NWAY_TPEXTEND|PN_NWAY_POLARITY| \
PN_NWAY_TP)
#define PN_NWAY_MODE_10FD \
(PN_NWAY_CAP10HALF|PN_NWAY_CAP10FULL| \
PN_NWAY_CAP100FULL|PN_NWAY_CAP100HALF|PN_NWAY_CAP100T4| \
PN_NWAY_AUILOWCUR|PN_NWAY_TPEXTEND|PN_NWAY_POLARITY| \
PN_NWAY_TP|PN_NWAY_DUPLEX)
#define PN_NWAY_MODE_100HD \
(PN_NWAY_CAP10HALF|PN_NWAY_CAP10FULL| \
PN_NWAY_CAP100FULL|PN_NWAY_CAP100HALF|PN_NWAY_CAP100T4| \
PN_NWAY_AUILOWCUR|PN_NWAY_TPEXTEND|PN_NWAY_POLARITY| \
PN_NWAY_TP|PN_NWAY_SPEEDSEL)
#define PN_NWAY_MODE_100FD \
(PN_NWAY_CAP10HALF|PN_NWAY_CAP10FULL| \
PN_NWAY_CAP100FULL|PN_NWAY_CAP100HALF|PN_NWAY_CAP100T4| \
PN_NWAY_AUILOWCUR|PN_NWAY_TPEXTEND|PN_NWAY_POLARITY| \
PN_NWAY_TP|PN_NWAY_SPEEDSEL|PN_NWAY_DUPLEX)
#define PN_NWAY_MODE_100T4 PN_NWAY_MODE_100HD
#define PN_NWAY_LPAR \
(PN_NWAY_LPAR10HALF|PN_NWAY_LPAR10FULL|PN_NWAY_LPAR100HALF| \
PN_NWAY_LPAR100FULL|PN_NWAY_LPAR100T4)
/*
* Size of a setup frame.
*/
#define PN_SFRAME_LEN 192
/*
* PNIC TX/RX list structure.
*/
struct pn_desc {
u_int32_t pn_status;
u_int32_t pn_ctl;
u_int32_t pn_ptr1;
u_int32_t pn_ptr2;
};
#define pn_data pn_ptr1
#define pn_next pn_ptr2
#define RX_RXSTAT_FIFOOFLOW 0x00000001
#define PN_RXSTAT_CRCERR 0x00000002
#define PN_RXSTAT_DRIBBLE 0x00000004
#define PN_RXSTAT_WATCHDOG 0x00000010
#define PN_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
#define PN_RXSTAT_COLLSEEN 0x00000040
#define PN_RXSTAT_GIANT 0x00000080
#define PN_RXSTAT_LASTFRAG 0x00000100
#define PN_RXSTAT_FIRSTFRAG 0x00000200
#define PN_RXSTAT_MULTICAST 0x00000400
#define PN_RXSTAT_RUNT 0x00000800
#define PN_RXSTAT_RXTYPE 0x00003000
#define PN_RXSTAT_RXERR 0x00008000
#define PN_RXSTAT_RXLEN 0x7FFF0000
#define PN_RXSTAT_OWN 0x80000000
#define PN_RXBYTES(x) ((x & PN_RXSTAT_RXLEN) >> 16)
#define PN_RXSTAT (PN_RXSTAT_FIRSTFRAG|PN_RXSTAT_LASTFRAG|PN_RXSTAT_OWN)
#define PN_RXCTL_BUFLEN1 0x00000FFF
#define PN_RXCTL_BUFLEN2 0x00FFF000
#define PN_RXCTL_RLINK 0x01000000
#define PN_RXCTL_RLAST 0x02000000
#define PN_TXSTAT_DEFER 0x00000001
#define PN_TXSTAT_UNDERRUN 0x00000002
#define PN_TXSTAT_LINKFAIL 0x00000003
#define PN_TXSTAT_COLLCNT 0x00000078
#define PN_TXSTAT_SQE 0x00000080
#define PN_TXSTAT_EXCESSCOLL 0x00000100
#define PN_TXSTAT_LATECOLL 0x00000200
#define PN_TXSTAT_NOCARRIER 0x00000400
#define PN_TXSTAT_CARRLOST 0x00000800
#define PN_TXSTAT_JABTIMEO 0x00004000
#define PN_TXSTAT_ERRSUM 0x00008000
#define PN_TXSTAT_OWN 0x80000000
#define PN_TXCTL_BUFLEN1 0x000007FF
#define PN_TXCTL_BUFLEN2 0x003FF800
#define PN_TXCTL_FILTTYPE0 0x00400000
#define PN_TXCTL_PAD 0x00800000
#define PN_TXCTL_TLINK 0x01000000
#define PN_TXCTL_TLAST 0x02000000
#define PN_TXCTL_NOCRC 0x04000000
#define PN_TXCTL_SETUP 0x08000000
#define PN_TXCTL_FILTTYPE1 0x10000000
#define PN_TXCTL_FIRSTFRAG 0x20000000
#define PN_TXCTL_LASTFRAG 0x40000000
#define PN_TXCTL_FINT 0x80000000
#define PN_FILTER_PERFECT 0x00000000
#define PN_FILTER_HASHPERF 0x00400000
#define PN_FILTER_INVERSE 0x10000000
#define PN_FILTER_HASHONLY 0x10400000
#define PN_MAXFRAGS 16
#define PN_RX_LIST_CNT 64
#define PN_TX_LIST_CNT 128
#define PN_MIN_FRAMELEN 60
#define PN_FRAMELEN 1536
#define PN_RXLEN 1536
#define ETHER_ALIGN 2
/*
* A tx 'super descriptor' is actually 16 regular descriptors
* back to back.
*/
struct pn_txdesc {
struct pn_desc pn_frag[PN_MAXFRAGS];
};
#define PN_TXNEXT(x) x->pn_ptr->pn_frag[x->pn_lastdesc].pn_next
#define PN_TXSTATUS(x) x->pn_ptr->pn_frag[x->pn_lastdesc].pn_status
#define PN_TXCTL(x) x->pn_ptr->pn_frag[x->pn_lastdesc].pn_ctl
#define PN_TXDATA(x) x->pn_ptr->pn_frag[x->pn_lastdesc].pn_data
#define PN_TXOWN(x) x->pn_ptr->pn_frag[0].pn_status
struct pn_list_data {
struct pn_desc pn_rx_list[PN_RX_LIST_CNT];
struct pn_txdesc pn_tx_list[PN_TX_LIST_CNT];
};
struct pn_chain {
struct pn_txdesc *pn_ptr;
struct mbuf *pn_mbuf;
struct pn_chain *pn_nextdesc;
u_int8_t pn_lastdesc;
};
struct pn_chain_onefrag {
struct pn_desc *pn_ptr;
struct mbuf *pn_mbuf;
struct pn_chain_onefrag *pn_nextdesc;
};
struct pn_chain_data {
struct pn_desc pn_sframe;
u_int32_t pn_sbuf[PN_SFRAME_LEN/sizeof(u_int32_t)];
struct pn_chain_onefrag pn_rx_chain[PN_RX_LIST_CNT];
struct pn_chain pn_tx_chain[PN_TX_LIST_CNT];
struct pn_chain_onefrag *pn_rx_head;
struct pn_chain *pn_tx_head;
struct pn_chain *pn_tx_tail;
struct pn_chain *pn_tx_free;
};
struct pn_type {
u_int16_t pn_vid;
u_int16_t pn_did;
char *pn_name;
};
struct pn_mii_frame {
u_int8_t mii_stdelim;
u_int8_t mii_opcode;
u_int8_t mii_phyaddr;
u_int8_t mii_regaddr;
u_int8_t mii_turnaround;
u_int16_t mii_data;
};
/*
* MII constants
*/
#define PN_MII_STARTDELIM 0x01
#define PN_MII_READOP 0x02
#define PN_MII_WRITEOP 0x01
#define PN_MII_TURNAROUND 0x02
#define PN_FLAG_FORCEDELAY 1
#define PN_FLAG_SCHEDDELAY 2
#define PN_FLAG_DELAYTIMEO 3
struct pn_softc {
struct arpcom arpcom; /* interface info */
struct ifmedia ifmedia; /* media info */
bus_space_handle_t pn_bhandle; /* bus space handle */
bus_space_tag_t pn_btag; /* bus space tag */
void *pn_intrhand;
struct resource *pn_irq;
struct resource *pn_res;
struct pn_type *pn_info; /* PNIC adapter info */
struct pn_type *pn_pinfo; /* phy info */
u_int8_t pn_unit; /* interface number */
u_int8_t pn_type;
u_int8_t pn_phy_addr; /* PHY address */
u_int8_t pn_tx_pend; /* TX pending */
u_int8_t pn_want_auto;
u_int8_t pn_autoneg;
u_int8_t pn_cachesize;
#ifdef PN_RX_BUG_WAR
#define PN_168_REV 16
#define PN_169_REV 32
#define PN_169B_REV 33
u_int8_t pn_rx_war;
struct pn_chain_onefrag *pn_rx_bug_save;
unsigned char *pn_rx_buf;
#endif
caddr_t pn_ldata_ptr;
struct pn_list_data *pn_ldata;
struct pn_chain_data pn_cdata;
};
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->pn_btag, sc->pn_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->pn_btag, sc->pn_bhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->pn_btag, sc->pn_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->pn_btag, sc->pn_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->pn_btag, sc->pn_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->pn_btag, sc->pn_bhandle, reg)
#define PN_TIMEOUT 1000
/*
* General constants that are fun to know.
*
* Lite-On PNIC PCI vendor ID
*/
#define PN_VENDORID 0x11AD
/*
* Lite-On PNIC PCI device ID.
*/
#define PN_DEVICEID_PNIC 0x0002
/*
* The 82c168 chip has the same PCI vendor/device ID as the
* 82c169, but a different revision. Assume that any revision
* between 0x10 an 0x1F is an 82c168.
*/
#define PN_REVMASK 0xF0
#define PN_REVID_82C168 0x10
#define PN_REVID_82C169 0x20
/*
* Texas Instruments PHY identifiers
*/
#define TI_PHY_VENDORID 0x4000
#define TI_PHY_10BT 0x501F
#define TI_PHY_100VGPMI 0x502F
/*
* These ID values are for the NS DP83840A 10/100 PHY
*/
#define NS_PHY_VENDORID 0x2000
#define NS_PHY_83840A 0x5C0F
/*
* Level 1 10/100 PHY
*/
#define LEVEL1_PHY_VENDORID 0x7810
#define LEVEL1_PHY_LXT970 0x000F
/*
* Intel 82555 10/100 PHY
*/
#define INTEL_PHY_VENDORID 0x0A28
#define INTEL_PHY_82555 0x015F
/*
* SEEQ 80220 10/100 PHY
*/
#define SEEQ_PHY_VENDORID 0x0016
#define SEEQ_PHY_80220 0xF83F
/*
* PCI low memory base and low I/O base register, and
* other PCI registers.
*/
#define PN_PCI_VENDOR_ID 0x00
#define PN_PCI_DEVICE_ID 0x02
#define PN_PCI_COMMAND 0x04
#define PN_PCI_STATUS 0x06
#define PN_PCI_REVISION 0x08
#define PN_PCI_CLASSCODE 0x09
#define PN_PCI_CACHELEN 0x0C
#define PN_PCI_LATENCY_TIMER 0x0D
#define PN_PCI_HEADER_TYPE 0x0E
#define PN_PCI_LOIO 0x10
#define PN_PCI_LOMEM 0x14
#define PN_PCI_BIOSROM 0x30
#define PN_PCI_INTLINE 0x3C
#define PN_PCI_INTPIN 0x3D
#define PN_PCI_MINGNT 0x3E
#define PN_PCI_MINLAT 0x0F
#define PN_PCI_RESETOPT 0x48
#define PN_PCI_EEPROM_DATA 0x4C
/* power management registers */
#define PN_PCI_CAPID 0xDC /* 8 bits */
#define PN_PCI_NEXTPTR 0xDD /* 8 bits */
#define PN_PCI_PWRMGMTCAP 0xDE /* 16 bits */
#define PN_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
#define PN_PSTATE_MASK 0x0003
#define PN_PSTATE_D0 0x0000
#define PN_PSTATE_D1 0x0002
#define PN_PSTATE_D2 0x0002
#define PN_PSTATE_D3 0x0003
#define PN_PME_EN 0x0010
#define PN_PME_STATUS 0x8000
#define PHY_UNKNOWN 6
#define PN_PHYADDR_MIN 0x00
#define PN_PHYADDR_MAX 0x1F
#define PHY_BMCR 0x00
#define PHY_BMSR 0x01
#define PHY_VENID 0x02
#define PHY_DEVID 0x03
#define PHY_ANAR 0x04
#define PHY_LPAR 0x05
#define PHY_ANEXP 0x06
#define PHY_ANAR_NEXTPAGE 0x8000
#define PHY_ANAR_RSVD0 0x4000
#define PHY_ANAR_TLRFLT 0x2000
#define PHY_ANAR_RSVD1 0x1000
#define PHY_ANAR_RSVD2 0x0800
#define PHY_ANAR_RSVD3 0x0400
#define PHY_ANAR_100BT4 0x0200
#define PHY_ANAR_100BTXFULL 0x0100
#define PHY_ANAR_100BTXHALF 0x0080
#define PHY_ANAR_10BTFULL 0x0040
#define PHY_ANAR_10BTHALF 0x0020
#define PHY_ANAR_PROTO4 0x0010
#define PHY_ANAR_PROTO3 0x0008
#define PHY_ANAR_PROTO2 0x0004
#define PHY_ANAR_PROTO1 0x0002
#define PHY_ANAR_PROTO0 0x0001
/*
* These are the register definitions for the PHY (physical layer
* interface chip).
*/
/*
* PHY BMCR Basic Mode Control Register
*/
#define PHY_BMCR_RESET 0x8000
#define PHY_BMCR_LOOPBK 0x4000
#define PHY_BMCR_SPEEDSEL 0x2000
#define PHY_BMCR_AUTONEGENBL 0x1000
#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
#define PHY_BMCR_ISOLATE 0x0400
#define PHY_BMCR_AUTONEGRSTR 0x0200
#define PHY_BMCR_DUPLEX 0x0100
#define PHY_BMCR_COLLTEST 0x0080
#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
/*
* RESET: 1 == software reset, 0 == normal operation
* Resets status and control registers to default values.
* Relatches all hardware config values.
*
* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
*
* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
* Link speed is selected byt his bit or if auto-negotiation if bit
* 12 (AUTONEGENBL) is set (in which case the value of this register
* is ignored).
*
* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
* determine speed and mode. Should be cleared and then set if PHY configured
* for no autoneg on startup.
*
* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
*
* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
*
* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
*
* COLLTEST: 1 == collision test enabled, 0 == normal operation
*/
/*
* PHY, BMSR Basic Mode Status Register
*/
#define PHY_BMSR_100BT4 0x8000
#define PHY_BMSR_100BTXFULL 0x4000
#define PHY_BMSR_100BTXHALF 0x2000
#define PHY_BMSR_10BTFULL 0x1000
#define PHY_BMSR_10BTHALF 0x0800
#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
#define PHY_BMSR_MFPRESUP 0x0040
#define PHY_BMSR_AUTONEGCOMP 0x0020
#define PHY_BMSR_REMFAULT 0x0010
#define PHY_BMSR_CANAUTONEG 0x0008
#define PHY_BMSR_LINKSTAT 0x0004
#define PHY_BMSR_JABBER 0x0002
#define PHY_BMSR_EXTENDED 0x0001
#ifdef __alpha__
#undef vtophys
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
#endif

6
usr.sbin/sade/devices.c
View File

@ -91,14 +91,12 @@ static struct _devname {
{ DEVICE_TYPE_FLOPPY, "fd%d", "floppy drive unit A", 2, 0, 64, 4, 'b' },
{ DEVICE_TYPE_FLOPPY, "wfd%d", "ATAPI floppy drive unit A", 1, 0, 8, 4, 'b' },
{ DEVICE_TYPE_FLOPPY, "worm%d", "SCSI optical disk / CDR", 23, 0, 1, 4, 'b' },
{ DEVICE_TYPE_NETWORK, "al", "ADMtek AL981/AN985 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "ax", "ASIX AX88140A PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "fpa", "DEC DEFPA PCI FDDI card" },
{ DEVICE_TYPE_NETWORK, "sr", "SDL T1/E1 sync serial PCI card" },
{ DEVICE_TYPE_NETWORK, "cc3i", "SDL HSSI sync serial PCI card" },
{ DEVICE_TYPE_NETWORK, "en", "Efficient Networks ATM PCI card" },
{ DEVICE_TYPE_NETWORK, "dc", "DEC/Intel 21143 (and clones) PCI fast ethernet card" },
{ DEVICE_TYPE_NETWORK, "de", "DEC DE435 PCI NIC or other DC21040-AA based card" },
{ DEVICE_TYPE_NETWORK, "dm", "Davicom DM9100/DM9102 PCI fast ethernet card" },
{ DEVICE_TYPE_NETWORK, "fxp", "Intel EtherExpress Pro/100B PCI Fast Ethernet card" },
{ DEVICE_TYPE_NETWORK, "ed", "Novell NE1000/2000; 3C503; NE2000-compatible PCMCIA" },
{ DEVICE_TYPE_NETWORK, "ep", "3Com 3C509 ethernet card/3C589 PCMCIA" },
@ -109,8 +107,6 @@ static struct _devname {
{ DEVICE_TYPE_NETWORK, "ix", "Intel Etherexpress ethernet card" },
{ DEVICE_TYPE_NETWORK, "le", "DEC EtherWorks 2 or 3 ethernet card" },
{ DEVICE_TYPE_NETWORK, "lnc", "Lance/PCnet (Isolan/Novell NE2100/NE32-VL) ethernet" },
{ DEVICE_TYPE_NETWORK, "mx", "Macronix 98713/98715/98725 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "pn", "Lite-On 82168/82169 PNIC PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "rl", "RealTek 8129/8139 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "sf", "Adaptec AIC-6915 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "sis", "SiS 900/SiS 7016 PCI ethernet card" },

6
usr.sbin/sysinstall/devices.c
View File

@ -91,14 +91,12 @@ static struct _devname {
{ DEVICE_TYPE_FLOPPY, "fd%d", "floppy drive unit A", 2, 0, 64, 4, 'b' },
{ DEVICE_TYPE_FLOPPY, "wfd%d", "ATAPI floppy drive unit A", 1, 0, 8, 4, 'b' },
{ DEVICE_TYPE_FLOPPY, "worm%d", "SCSI optical disk / CDR", 23, 0, 1, 4, 'b' },
{ DEVICE_TYPE_NETWORK, "al", "ADMtek AL981/AN985 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "ax", "ASIX AX88140A PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "fpa", "DEC DEFPA PCI FDDI card" },
{ DEVICE_TYPE_NETWORK, "sr", "SDL T1/E1 sync serial PCI card" },
{ DEVICE_TYPE_NETWORK, "cc3i", "SDL HSSI sync serial PCI card" },
{ DEVICE_TYPE_NETWORK, "en", "Efficient Networks ATM PCI card" },
{ DEVICE_TYPE_NETWORK, "dc", "DEC/Intel 21143 (and clones) PCI fast ethernet card" },
{ DEVICE_TYPE_NETWORK, "de", "DEC DE435 PCI NIC or other DC21040-AA based card" },
{ DEVICE_TYPE_NETWORK, "dm", "Davicom DM9100/DM9102 PCI fast ethernet card" },
{ DEVICE_TYPE_NETWORK, "fxp", "Intel EtherExpress Pro/100B PCI Fast Ethernet card" },
{ DEVICE_TYPE_NETWORK, "ed", "Novell NE1000/2000; 3C503; NE2000-compatible PCMCIA" },
{ DEVICE_TYPE_NETWORK, "ep", "3Com 3C509 ethernet card/3C589 PCMCIA" },
@ -109,8 +107,6 @@ static struct _devname {
{ DEVICE_TYPE_NETWORK, "ix", "Intel Etherexpress ethernet card" },
{ DEVICE_TYPE_NETWORK, "le", "DEC EtherWorks 2 or 3 ethernet card" },
{ DEVICE_TYPE_NETWORK, "lnc", "Lance/PCnet (Isolan/Novell NE2100/NE32-VL) ethernet" },
{ DEVICE_TYPE_NETWORK, "mx", "Macronix 98713/98715/98725 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "pn", "Lite-On 82168/82169 PNIC PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "rl", "RealTek 8129/8139 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "sf", "Adaptec AIC-6915 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "sis", "SiS 900/SiS 7016 PCI ethernet card" },