Remove dead errata fixup code
This code caused more problems than it should have fixed (boot failures) on the machines I tested, so has been commented out for a while now. Remove it, and assume the errata fixups were done by the bootloader where they belong.
This commit is contained in:
Justin Hibbits
parent
ee900504cf
commit
971b5e4da8
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=333135
@ -906,68 +906,6 @@ ENTRY(bpred_enable)
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isync
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blr
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ENTRY(dataloss_erratum_access)
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/* Lock two cache lines into I-Cache */
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sync
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mfspr %r11, SPR_L1CSR1
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rlwinm %r11, %r11, 0, ~L1CSR1_ICUL
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sync
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isync
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mtspr SPR_L1CSR1, %r11
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isync
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lis %r8, 2f@h
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ori %r8, %r8, 2f@l
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icbtls 0, 0, %r8
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addi %r9, %r8, 64
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sync
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mfspr %r11, SPR_L1CSR1
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3: andi. %r11, %r11, L1CSR1_ICUL
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bne 3b
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icbtls 0, 0, %r9
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sync
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mfspr %r11, SPR_L1CSR1
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3: andi. %r11, %r11, L1CSR1_ICUL
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bne 3b
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b 2f
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.align 6
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/* Inside a locked cacheline, wait a while, write, then wait a while */
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2: sync
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mfspr %r5, TBR_TBL
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4: addis %r11, %r5, 0x100000@h /* wait around one million timebase ticks */
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mfspr %r5, TBR_TBL
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subf. %r5, %r5, %r11
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bgt 4b
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stw %r4, 0(%r3)
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mfspr %r5, TBR_TBL
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4: addis %r11, %r5, 0x100000@h /* wait around one million timebase ticks */
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mfspr %r5, TBR_TBL
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subf. %r5, %r5, %r11
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bgt 4b
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sync
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/*
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* Fill out the rest of this cache line and the next with nops,
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* to ensure that nothing outside the locked area will be
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* fetched due to a branch.
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*/
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.rept 19
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nop
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.endr
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icblc 0, 0, %r8
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icblc 0, 0, %r9
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blr
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/*
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* XXX: This should be moved to a shared AIM/booke asm file, if one ever is
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* created.
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@ -329,120 +329,6 @@ mpc85xx_is_qoriq(void)
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return (0);
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}
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static void
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mpc85xx_dataloss_erratum_spr976(void)
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{
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uint32_t svr = SVR_VER(mfspr(SPR_SVR));
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/* Ignore whether it's the E variant */
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svr &= ~0x8;
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if (svr != SVR_P3041 && svr != SVR_P4040 &&
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svr != SVR_P4080 && svr != SVR_P5020)
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return;
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mb();
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isync();
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mtspr(976, (mfspr(976) & ~0x1f8) | 0x48);
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isync();
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}
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static vm_offset_t
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mpc85xx_map_dcsr(void)
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{
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phandle_t node;
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u_long b, s;
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int err;
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/*
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* Try to access the dcsr node directly i.e. through /aliases/.
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*/
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if ((node = OF_finddevice("dcsr")) != -1)
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if (fdt_is_compatible_strict(node, "fsl,dcsr"))
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goto moveon;
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/*
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* Find the node the long way.
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*/
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if ((node = OF_finddevice("/")) == -1)
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return (0);
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if ((node = ofw_bus_find_compatible(node, "fsl,dcsr")) == 0)
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return (0);
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moveon:
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err = fdt_get_range(node, 0, &b, &s);
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if (err != 0)
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return (0);
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law_enable(OCP85XX_TGTIF_DCSR, b, 0x400000);
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return pmap_early_io_map(b, 0x400000);
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}
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void
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mpc85xx_fix_errata(vm_offset_t va_ccsr)
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{
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uint32_t svr = SVR_VER(mfspr(SPR_SVR));
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vm_offset_t va_dcsr;
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/* Ignore whether it's the E variant */
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svr &= ~0x8;
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if (svr != SVR_P3041 && svr != SVR_P4040 &&
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svr != SVR_P4080 && svr != SVR_P5020)
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return;
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if (mfmsr() & PSL_EE)
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return;
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/*
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* dcsr region need to be mapped thus patch can refer to.
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* Align dcsr right after ccsbar.
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*/
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va_dcsr = mpc85xx_map_dcsr();
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if (va_dcsr == 0)
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goto err;
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/*
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* As A004510 errata specify, special purpose register 976
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* SPR976[56:60] = 6'b001001 must be set. e500mc core reference manual
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* does not document SPR976 register.
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*/
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mpc85xx_dataloss_erratum_spr976();
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/*
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* Specific settings in the CCF and core platform cache (CPC)
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* are required to reconfigure the CoreNet coherency fabric.
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* The register settings that should be updated are described
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* in errata and relay on base address, offset and updated value.
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* Special conditions must be used to update these registers correctly.
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*/
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dataloss_erratum_access(va_dcsr + 0xb0e08, 0xe0201800);
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dataloss_erratum_access(va_dcsr + 0xb0e18, 0xe0201800);
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dataloss_erratum_access(va_dcsr + 0xb0e38, 0xe0400000);
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dataloss_erratum_access(va_dcsr + 0xb0008, 0x00900000);
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dataloss_erratum_access(va_dcsr + 0xb0e40, 0xe00a0000);
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switch (svr) {
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case SVR_P5020:
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dataloss_erratum_access(va_ccsr + 0x18600, 0xc0000000);
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break;
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case SVR_P4040:
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case SVR_P4080:
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dataloss_erratum_access(va_ccsr + 0x18600, 0xff000000);
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break;
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case SVR_P3041:
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dataloss_erratum_access(va_ccsr + 0x18600, 0xf0000000);
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}
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dataloss_erratum_access(va_ccsr + 0x10f00, 0x415e5000);
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dataloss_erratum_access(va_ccsr + 0x11f00, 0x415e5000);
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err:
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return;
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}
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uint32_t
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mpc85xx_get_platform_clock(void)
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{
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@ -170,8 +170,6 @@ DECLARE_CLASS(mpc85xx_platform);
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int mpc85xx_attach(platform_t);
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void mpc85xx_enable_l3_cache(void);
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void mpc85xx_fix_errata(vm_offset_t);
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void dataloss_erratum_access(vm_offset_t, uint32_t);
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int mpc85xx_is_qoriq(void);
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uint32_t mpc85xx_get_platform_clock(void);
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uint32_t mpc85xx_get_system_clock(void);
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@ -199,9 +199,6 @@ mpc85xx_attach(platform_t plat)
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ccsrbar_pa = ccsrbar;
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ccsrbar_size = ccsrsize;
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#if 0
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mpc85xx_fix_errata(ccsrbar_va);
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#endif
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mpc85xx_enable_l3_cache();
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return (0);
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