- Remove bus-dependent addresses from `ic' file.
- Special registers of IO-DATA device's RSA series are defined in ic/rsa.h (new file). Pointed out by: Bruce Evans <bde@zeta.org.au> Submitted by: Takahashi Yoshihiro <nyan@wyvern.cc.kogakuin.ac.jp>
This commit is contained in:
kato
parent
93792c25ef
commit
97a0b2ee1f
@ -26,7 +26,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: esp.h,v 1.3 1997/02/22 09:38:00 peter Exp $
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* $Id: esp.h,v 1.4 1999/01/03 05:03:46 kato Exp $
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*/
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#ifndef _IC_ESP_H_
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@ -39,13 +39,8 @@
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/*
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* CMD1 and CMD2 are the command ports, offsets from <esp_iobase>.
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*/
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#ifdef PC98
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#define ESP_CMD1 0x400
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#define ESP_CMD2 0x500
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#else
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#define ESP_CMD1 4
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#define ESP_CMD2 5
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#endif
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/*
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* STAT1 and STAT2 are to get return values and status bytes;
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@ -31,7 +31,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91
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* $Id: ns16550.h,v 1.5 1997/02/22 09:38:05 peter Exp $
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* $Id: ns16550.h,v 1.6 1999/01/03 05:03:46 kato Exp $
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*/
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/*
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@ -48,108 +48,3 @@
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#define com_mcr 4 /* modem control register (R/W) */
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#define com_lsr 5 /* line status register (R/W) */
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#define com_msr 6 /* modem status register (R/W) */
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#ifdef PC98
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#define com_emr com_msr /* Extension mode register for RSB-2000/3000. */
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/* I/O-DATA RSA Serise Exrension Register */
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#define rsa_msr 0 /* Mode Status Register (R/W) */
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#define rsa_ier 1 /* Interrupt Enable Register (R/W) */
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#define rsa_srr 2 /* Status Read Register (R) */
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#define rsa_frr 2 /* FIFO Reset Register (W) */
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#define rsa_tivsr 3 /* Timer Interval Value Set Register (R/W) */
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#define rsa_tcr 4 /* Timer Control Register (W) */
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/*
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* RSA-98III RSA Mode Driver Data Sheet
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*
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* <<Register Map>>
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* Base + 0x00
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* Mode Select Register(Read/Write)
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* bit4=interrupt type(1: level, 0: edge)
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* bit3=Auto RTS-CTS Flow Control Enable
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* bit2=External FIFO Enable
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* bit1=Reserved(Default 0)Don't Change!!
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* bit0=Swap Upper 8byte and Lower 8byte in 16byte space.
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*
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* Base + 0x01
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* Interrupt Enable Register(Read/Write)
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* bit4=Hardware Timer Interrupt Enable
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* bit3=Character Time-Out Interrupt Enable
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* bit2=Tx FIFO Empty Interrupt Enable
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* bit1=Tx FIFO Half Full Interrupt Enable
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* bit0=Rx FIFO Half Full Interrupt Enable
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*
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* Base + 0x02
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* Status Read Register(Read)
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* bit7=Hardware Time Out Interrupt Status(1: True, 0: False)
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* bit6=Character Time Out Interrupt Status
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* bit5=Rx FIFO Full Flag(0: True, 1: False)
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* bit4=Rx FIFO Half Full Flag
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* bit3=Rx FIFO Empty Flag
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* bit2=Tx FIFO Full Flag
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* bit1=Tx FIFO Half Full Flag
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* bit0=Tx FIFO Empty Flag
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*
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* Base + 0x02
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* FIFO Reset Register(Write)
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* Reset Extrnal FIFO
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*
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* Base + 0x03
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* Timer Interval Value Set Register(Read/Write)
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* Range of n: 1-255
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* Interval Value: n * 0.2ms
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*
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* Base + 0x04
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* Timer Control Register(Read/Write)
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* bit0=Timer Enable
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*
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* Base + 0x08 - 0x0f
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* Same as UART 16550
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*
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* Special Regisgter in RSA Mode
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* UART Data Register(Base + 0x08)
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* Data transfer between Extrnal FIFO
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*
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* UART MCR(Base + 0x0c)
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* bit3(OUT2[MCR_IENABLE])=1: Diable 16550 to Rx FIFO transfer
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* bit2(OUT1[MCR_DRS])=1: Diable Tx FIFO to 16550 transfer
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*
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* <<Intrrupt and Intrrupt Reset>>
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* o Reciver Line Status(from UART16550)
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* Reset: Read LSR
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*
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* o Modem Status(from UART16550)
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* Reset: Read MSR
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*
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* o Rx FIFO Half Full(from Extrnal FIFO)
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* Reset: Read Rx FIFO under Hall Full
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*
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* o Character Time Out(from Extrnal FIFO)
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* Reset: Read Rx FIFO or SRR
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*
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* o Tx FIFO Empty(from Extrnal FIFO)
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* Reset: Write Tx FIFO or Read SRR
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*
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* o Tx FIFO Half Full(from Extrnal FIFO)
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* Reset: Write Tx FIFO until Hall Full or Read SRR
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*
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* o Hardware Timer(from Extrnal FIFO)
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* Reset: Disable Timer in TCR
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* Notes: If you want to use Timer for next intrrupt,
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* you must enable Timer in TCR
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*
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* <<Used Setting>>
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* Auto RTS-CTS: Enable or Disable
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* External FIFO: Enable
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* Swap 8bytes: Disable
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* Haredware Timer: Disable
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* interrupt type: edge
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* interrupt source:
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* Hareware Timer
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* Character Time Out
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* Tx FIFO Empty
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* Rx FIFO Half Full
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*
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*/
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#endif /* PC98 */
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128
sys/i386/isa/ic/rsa.h
Normal file
128
sys/i386/isa/ic/rsa.h
Normal file
@ -0,0 +1,128 @@
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/*-
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* Copyright (c) 1999 FreeBSD Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: $
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*/
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/*
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* RSA Mode Driver Data Sheet
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*
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* <<Register Map>>
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* Base + 0x00
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* Mode Select Register(Read/Write)
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* bit4=interrupt type(1: level, 0: edge)
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* bit3=Auto RTS-CTS Flow Control Enable
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* bit2=External FIFO Enable
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* bit1=Reserved(Default 0)Don't Change!!
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* bit0=Swap Upper 8byte and Lower 8byte in 16byte space.
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*
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* Base + 0x01
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* Interrupt Enable Register(Read/Write)
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* bit4=Hardware Timer Interrupt Enable
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* bit3=Character Time-Out Interrupt Enable
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* bit2=Tx FIFO Empty Interrupt Enable
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* bit1=Tx FIFO Half Full Interrupt Enable
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* bit0=Rx FIFO Half Full Interrupt Enable
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*
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* Base + 0x02
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* Status Read Register(Read)
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* bit7=Hardware Time Out Interrupt Status(1: True, 0: False)
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* bit6=Character Time Out Interrupt Status
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* bit5=Rx FIFO Full Flag(0: True, 1: False)
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* bit4=Rx FIFO Half Full Flag
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* bit3=Rx FIFO Empty Flag
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* bit2=Tx FIFO Full Flag
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* bit1=Tx FIFO Half Full Flag
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* bit0=Tx FIFO Empty Flag
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*
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* Base + 0x02
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* FIFO Reset Register(Write)
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* Reset Extrnal FIFO
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*
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* Base + 0x03
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* Timer Interval Value Set Register(Read/Write)
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* Range of n: 1-255
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* Interval Value: n * 0.2ms
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*
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* Base + 0x04
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* Timer Control Register(Read/Write)
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* bit0=Timer Enable
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*
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* Base + 0x08 - 0x0f
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* Same as UART 16550
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*
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* Special Regisgter in RSA Mode
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* UART Data Register(Base + 0x08)
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* Data transfer between Extrnal FIFO
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*
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* UART MCR(Base + 0x0c)
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* bit3(OUT2[MCR_IENABLE])=1: Diable 16550 to Rx FIFO transfer
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* bit2(OUT1[MCR_DRS])=1: Diable Tx FIFO to 16550 transfer
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*
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* <<Intrrupt and Intrrupt Reset>>
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* o Reciver Line Status(from UART16550)
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* Reset: Read LSR
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*
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* o Modem Status(from UART16550)
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* Reset: Read MSR
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*
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* o Rx FIFO Half Full(from Extrnal FIFO)
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* Reset: Read Rx FIFO under Hall Full
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*
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* o Character Time Out(from Extrnal FIFO)
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* Reset: Read Rx FIFO or SRR
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*
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* o Tx FIFO Empty(from Extrnal FIFO)
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* Reset: Write Tx FIFO or Read SRR
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*
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* o Tx FIFO Half Full(from Extrnal FIFO)
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* Reset: Write Tx FIFO until Hall Full or Read SRR
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*
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* o Hardware Timer(from Extrnal FIFO)
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* Reset: Disable Timer in TCR
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* Notes: If you want to use Timer for next intrrupt,
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* you must enable Timer in TCR
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*
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* <<Used Setting>>
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* Auto RTS-CTS: Enable or Disable
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* External FIFO: Enable
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* Swap 8bytes: Disable
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* Haredware Timer: Disable
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* interrupt type: edge
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* interrupt source:
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* Hareware Timer
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* Character Time Out
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* Tx FIFO Empty
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* Rx FIFO Half Full
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*
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*/
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/* I/O-DATA RSA Serise Exrension Register */
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#define rsa_msr 0 /* Mode Status Register (R/W) */
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#define rsa_ier 1 /* Interrupt Enable Register (R/W) */
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#define rsa_srr 2 /* Status Read Register (R) */
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#define rsa_frr 2 /* FIFO Reset Register (W) */
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#define rsa_tivsr 3 /* Timer Interval Value Set Register (R/W) */
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#define rsa_tcr 4 /* Timer Control Register (W) */
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@ -31,7 +31,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)com.c 7.5 (Berkeley) 5/16/91
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* $Id: sio.c,v 1.71 1998/12/30 08:09:11 kato Exp $
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* $Id: sio.c,v 1.72 1999/01/03 05:03:47 kato Exp $
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*/
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#include "opt_comconsole.h"
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@ -171,6 +171,9 @@
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#include <i386/isa/ic/esp.h>
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#endif
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#include <i386/isa/ic/ns16550.h>
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#ifdef PC98
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#include <i386/isa/ic/rsa.h>
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#endif
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#include "card.h"
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#if NCARD > 0
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@ -229,9 +232,11 @@
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#define COM_IIR_TXRDYBUG(dev) ((dev)->id_flags & COM_C_IIR_TXRDYBUG)
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#define COM_FIFOSIZE(dev) (((dev)->id_flags & 0xff000000) >> 24)
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#ifndef PC98
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#ifdef PC98
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#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
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#else
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#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
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#endif /* !PC98 */
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#endif
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/*
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* Input buffer watermarks.
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@ -768,13 +773,23 @@ struct {
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#endif /* PC98 */
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#ifdef COM_ESP
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/* XXX configure this properly. */
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#ifdef PC98
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/* XXX configure this properly. */
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static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
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static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
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#else
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#define ESP98_CMD1 (ESP_CMD1 * 0x100)
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#define ESP98_CMD2 (ESP_CMD2 * 0x100)
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#define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
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#define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
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#else /* PC98 */
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/* XXX configure this properly. */
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static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
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static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
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#endif /* PC98 */
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#endif
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@ -1424,8 +1439,13 @@ espattach(isdp, com, esp_port)
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*/
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/* Get the dip-switch configuration */
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#ifdef PC98
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outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
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dips = inb(esp_port + ESP98_STATUS1);
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#else
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outb(esp_port + ESP_CMD1, ESP_GETDIPS);
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dips = inb(esp_port + ESP_STATUS1);
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#endif
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/*
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* Bits 0,1 of dips say which COM port we are.
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@ -1444,9 +1464,15 @@ espattach(isdp, com, esp_port)
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/*
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* Check for ESP version 2.0 or later: bits 4,5,6 = 010.
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*/
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#ifdef PC98
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outb(esp_port + ESP98_CMD1, ESP_GETTEST);
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val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
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val = inb(esp_port + ESP98_STATUS2);
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#else
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outb(esp_port + ESP_CMD1, ESP_GETTEST);
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val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
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val = inb(esp_port + ESP_STATUS2);
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#endif
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if ((val & 0x70) < 0x20) {
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printf("-old (%o)", val & 0x70);
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return (0);
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@ -1715,24 +1741,44 @@ sioattach(isdp)
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* bursts of input.
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* XXX flow control should be set in comparam(), not here.
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*/
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#ifdef PC98
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outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
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outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
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#else
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outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
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outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
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#endif
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/* Set RTS/CTS flow control. */
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#ifdef PC98
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outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
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outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
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outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
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#else
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outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
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outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
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outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
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#endif
|
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|
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/* Set flow-control levels. */
|
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#ifdef PC98
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outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
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outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
|
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outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
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outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
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outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
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#else
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outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
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outb(com->esp_port + ESP_CMD2, HIBYTE(768));
|
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outb(com->esp_port + ESP_CMD2, LOBYTE(768));
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outb(com->esp_port + ESP_CMD2, HIBYTE(512));
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outb(com->esp_port + ESP_CMD2, LOBYTE(512));
|
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#endif
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#ifdef PC98
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/* Set UART clock prescaler. */
|
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outb(com->esp_port + ESP_CMD1, ESP_SETCLOCK);
|
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outb(com->esp_port + ESP_CMD2, 2); /* 4 times */
|
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outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
|
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outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
|
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#endif
|
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}
|
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#endif /* COM_ESP */
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|
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@ -31,7 +31,7 @@
|
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* SUCH DAMAGE.
|
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*
|
||||
* from: @(#)com.c 7.5 (Berkeley) 5/16/91
|
||||
* $Id: sio.c,v 1.71 1998/12/30 08:09:11 kato Exp $
|
||||
* $Id: sio.c,v 1.72 1999/01/03 05:03:47 kato Exp $
|
||||
*/
|
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|
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#include "opt_comconsole.h"
|
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@ -171,6 +171,9 @@
|
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#include <i386/isa/ic/esp.h>
|
||||
#endif
|
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#include <i386/isa/ic/ns16550.h>
|
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#ifdef PC98
|
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#include <i386/isa/ic/rsa.h>
|
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#endif
|
||||
|
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#include "card.h"
|
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#if NCARD > 0
|
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@ -229,9 +232,11 @@
|
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#define COM_IIR_TXRDYBUG(dev) ((dev)->id_flags & COM_C_IIR_TXRDYBUG)
|
||||
#define COM_FIFOSIZE(dev) (((dev)->id_flags & 0xff000000) >> 24)
|
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|
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#ifndef PC98
|
||||
#ifdef PC98
|
||||
#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
|
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#else
|
||||
#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
|
||||
#endif /* !PC98 */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Input buffer watermarks.
|
||||
@ -768,13 +773,23 @@ struct {
|
||||
#endif /* PC98 */
|
||||
|
||||
#ifdef COM_ESP
|
||||
/* XXX configure this properly. */
|
||||
#ifdef PC98
|
||||
|
||||
/* XXX configure this properly. */
|
||||
static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
|
||||
static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
|
||||
#else
|
||||
|
||||
#define ESP98_CMD1 (ESP_CMD1 * 0x100)
|
||||
#define ESP98_CMD2 (ESP_CMD2 * 0x100)
|
||||
#define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
|
||||
#define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
|
||||
|
||||
#else /* PC98 */
|
||||
|
||||
/* XXX configure this properly. */
|
||||
static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
|
||||
static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
|
||||
|
||||
#endif /* PC98 */
|
||||
#endif
|
||||
|
||||
@ -1424,8 +1439,13 @@ espattach(isdp, com, esp_port)
|
||||
*/
|
||||
|
||||
/* Get the dip-switch configuration */
|
||||
#ifdef PC98
|
||||
outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
|
||||
dips = inb(esp_port + ESP98_STATUS1);
|
||||
#else
|
||||
outb(esp_port + ESP_CMD1, ESP_GETDIPS);
|
||||
dips = inb(esp_port + ESP_STATUS1);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Bits 0,1 of dips say which COM port we are.
|
||||
@ -1444,9 +1464,15 @@ espattach(isdp, com, esp_port)
|
||||
/*
|
||||
* Check for ESP version 2.0 or later: bits 4,5,6 = 010.
|
||||
*/
|
||||
#ifdef PC98
|
||||
outb(esp_port + ESP98_CMD1, ESP_GETTEST);
|
||||
val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
|
||||
val = inb(esp_port + ESP98_STATUS2);
|
||||
#else
|
||||
outb(esp_port + ESP_CMD1, ESP_GETTEST);
|
||||
val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
|
||||
val = inb(esp_port + ESP_STATUS2);
|
||||
#endif
|
||||
if ((val & 0x70) < 0x20) {
|
||||
printf("-old (%o)", val & 0x70);
|
||||
return (0);
|
||||
@ -1715,24 +1741,44 @@ sioattach(isdp)
|
||||
* bursts of input.
|
||||
* XXX flow control should be set in comparam(), not here.
|
||||
*/
|
||||
#ifdef PC98
|
||||
outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
|
||||
outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
|
||||
#else
|
||||
outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
|
||||
outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
|
||||
#endif
|
||||
|
||||
/* Set RTS/CTS flow control. */
|
||||
#ifdef PC98
|
||||
outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
|
||||
outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
|
||||
outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
|
||||
#else
|
||||
outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
|
||||
outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
|
||||
outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
|
||||
#endif
|
||||
|
||||
/* Set flow-control levels. */
|
||||
#ifdef PC98
|
||||
outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
|
||||
outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
|
||||
outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
|
||||
outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
|
||||
outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
|
||||
#else
|
||||
outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
|
||||
outb(com->esp_port + ESP_CMD2, HIBYTE(768));
|
||||
outb(com->esp_port + ESP_CMD2, LOBYTE(768));
|
||||
outb(com->esp_port + ESP_CMD2, HIBYTE(512));
|
||||
outb(com->esp_port + ESP_CMD2, LOBYTE(512));
|
||||
#endif
|
||||
|
||||
#ifdef PC98
|
||||
/* Set UART clock prescaler. */
|
||||
outb(com->esp_port + ESP_CMD1, ESP_SETCLOCK);
|
||||
outb(com->esp_port + ESP_CMD2, 2); /* 4 times */
|
||||
outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
|
||||
outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
|
||||
#endif
|
||||
}
|
||||
#endif /* COM_ESP */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user