- Factor out the common and generic parts of the sparc64 host-PCI-bridge
drivers into the revived sys/sparc64/pci/ofw_pci.c, previously already serving a similar purpose. This has been done with sun4v in mind, which explains a) the otherwise not that obvious scheme employed and b) why reusing sys/powerpc/ofw/ofw_pci.c was even lesser an option. - Add a workaround for QEMU once again not emulating real machines, in this case by not providing the OFW_PCI_CS_MEM64 range. [1] Submitted by: jhb [1] MFC after: 1 week
This commit is contained in:
parent
30811e70d9
commit
9888f86a16
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=287726
@ -82,6 +82,7 @@ sparc64/isa/isa_dma.c optional isa
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sparc64/isa/ofw_isa.c optional ebus | isa
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sparc64/pci/apb.c optional pci
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sparc64/pci/fire.c optional pci
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sparc64/pci/ofw_pci.c optional pci
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sparc64/pci/ofw_pcib.c optional pci
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sparc64/pci/ofw_pcib_subr.c optional pci
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sparc64/pci/ofw_pcibus.c optional pci
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@ -59,7 +59,6 @@ __FBSDID("$FreeBSD$");
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#include <sys/timetc.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/openfirm.h>
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#include <vm/vm.h>
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@ -68,7 +67,6 @@ __FBSDID("$FreeBSD$");
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#include <machine/bus.h>
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#include <machine/bus_common.h>
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#include <machine/bus_private.h>
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#include <machine/fsr.h>
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#include <machine/iommureg.h>
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#include <machine/iommuvar.h>
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#include <machine/pmap.h>
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@ -111,19 +109,14 @@ static driver_filter_t fire_xcb;
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/*
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* Methods
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*/
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static bus_activate_resource_t fire_activate_resource;
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static bus_adjust_resource_t fire_adjust_resource;
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static pcib_alloc_msi_t fire_alloc_msi;
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static pcib_alloc_msix_t fire_alloc_msix;
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static bus_alloc_resource_t fire_alloc_resource;
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static device_attach_t fire_attach;
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static bus_get_dma_tag_t fire_get_dma_tag;
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static ofw_bus_get_node_t fire_get_node;
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static pcib_map_msi_t fire_map_msi;
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static pcib_maxslots_t fire_maxslots;
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static device_probe_t fire_probe;
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static pcib_read_config_t fire_read_config;
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static bus_read_ivar_t fire_read_ivar;
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static pcib_release_msi_t fire_release_msi;
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static pcib_release_msix_t fire_release_msix;
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static pcib_route_interrupt_t fire_route_interrupt;
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@ -140,15 +133,15 @@ static device_method_t fire_methods[] = {
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DEVMETHOD(device_resume, bus_generic_resume),
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/* Bus interface */
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DEVMETHOD(bus_read_ivar, fire_read_ivar),
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DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar),
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DEVMETHOD(bus_setup_intr, fire_setup_intr),
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DEVMETHOD(bus_teardown_intr, fire_teardown_intr),
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DEVMETHOD(bus_alloc_resource, fire_alloc_resource),
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DEVMETHOD(bus_activate_resource, fire_activate_resource),
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DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_adjust_resource, fire_adjust_resource),
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DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_get_dma_tag, fire_get_dma_tag),
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DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, fire_maxslots),
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@ -162,7 +155,7 @@ static device_method_t fire_methods[] = {
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DEVMETHOD(pcib_map_msi, fire_map_msi),
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/* ofw_bus interface */
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DEVMETHOD(ofw_bus_get_node, fire_get_node),
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DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node),
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DEVMETHOD_END
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};
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@ -296,7 +289,7 @@ fire_attach(device_t dev)
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struct ofw_pci_msi_eq_to_devino msi_eq_to_devino;
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struct fire_msiqarg *fmqa;
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struct timecounter *tc;
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struct ofw_pci_ranges *range;
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bus_dma_tag_t dmat;
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uint64_t ino_bitmap, val;
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phandle_t node;
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uint32_t prop, prop_array[2];
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@ -310,7 +303,6 @@ fire_attach(device_t dev)
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mode = desc->fd_mode;
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sc->sc_dev = dev;
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sc->sc_node = node;
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sc->sc_mode = mode;
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sc->sc_flags = 0;
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@ -715,79 +707,21 @@ fire_attach(device_t dev)
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sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[FIRE_PCI]);
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sc->sc_is.is_iommu = FO_PCI_MMU;
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val = FIRE_PCI_READ_8(sc, FO_PCI_MMU + IMR_CTL);
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iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, 7, -1, 0);
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iommu_init(device_get_nameunit(dev), &sc->sc_is, 7, -1, 0);
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#ifdef FIRE_DEBUG
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device_printf(dev, "FO_PCI_MMU + IMR_CTL 0x%016llx -> 0x%016llx\n",
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(long long unsigned)val, (long long unsigned)sc->sc_is.is_cr);
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#endif
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/* Initialize memory and I/O rmans. */
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sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
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sc->sc_pci_io_rman.rm_descr = "Fire PCI I/O Ports";
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if (rman_init(&sc->sc_pci_io_rman) != 0 ||
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rman_manage_region(&sc->sc_pci_io_rman, 0, FO_IO_SIZE) != 0)
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panic("%s: failed to set up I/O rman", __func__);
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sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
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sc->sc_pci_mem_rman.rm_descr = "Fire PCI Memory";
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if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
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rman_manage_region(&sc->sc_pci_mem_rman, 0, FO_MEM_SIZE) != 0)
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panic("%s: failed to set up memory rman", __func__);
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i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
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/*
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* Make sure that the expected ranges are present. The
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* OFW_PCI_CS_MEM64 one is not currently used though.
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*/
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if (i != FIRE_NRANGE)
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panic("%s: unsupported number of ranges", __func__);
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/*
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* Find the addresses of the various bus spaces.
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* There should not be multiple ones of one kind.
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* The physical start addresses of the ranges are the configuration,
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* memory and I/O handles.
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*/
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for (i = 0; i < FIRE_NRANGE; i++) {
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j = OFW_PCI_RANGE_CS(&range[i]);
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if (sc->sc_pci_bh[j] != 0)
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panic("%s: duplicate range for space %d",
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__func__, j);
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sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
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}
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free(range, M_OFWPROP);
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/* Allocate our tags. */
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sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, PCI_IO_BUS_SPACE);
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if (sc->sc_pci_iot == NULL)
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panic("%s: could not allocate PCI I/O tag", __func__);
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sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, PCI_CONFIG_BUS_SPACE);
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if (sc->sc_pci_cfgt == NULL)
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panic("%s: could not allocate PCI configuration space tag",
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__func__);
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/* Create our DMA tag. */
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if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0x100000000,
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sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr,
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0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
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0xff, 0xffffffff, 0, NULL, NULL, &dmat) != 0)
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panic("%s: could not create PCI DMA tag", __func__);
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/* Customize the tag. */
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sc->sc_pci_dmat->dt_cookie = &sc->sc_is;
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sc->sc_pci_dmat->dt_mt = &sc->sc_dma_methods;
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dmat->dt_cookie = &sc->sc_is;
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dmat->dt_mt = &sc->sc_dma_methods;
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/*
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* Get the bus range from the firmware.
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* NB: Neither Fire nor Oberon support PCI bus reenumeration.
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*/
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i = OF_getprop(node, "bus-range", (void *)prop_array,
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sizeof(prop_array));
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if (i == -1)
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panic("%s: could not get bus-range", __func__);
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if (i != sizeof(prop_array))
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panic("%s: broken bus-range (%d)", __func__, i);
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sc->sc_pci_secbus = prop_array[0];
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sc->sc_pci_subbus = prop_array[1];
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if (bootverbose != 0)
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device_printf(dev, "bus range %u to %u; PCI bus %d\n",
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sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
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ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
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if (ofw_pci_attach_common(dev, dmat, FO_IO_SIZE, FO_MEM_SIZE) != 0)
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panic("%s: ofw_pci_attach_common() failed", __func__);
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#define FIRE_SYSCTL_ADD_UINT(name, arg, desc) \
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SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \
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@ -1390,136 +1324,44 @@ static uint32_t
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fire_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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int width)
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{
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struct fire_softc *sc;
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bus_space_handle_t bh;
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u_long offset = 0;
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uint32_t r, wrd;
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int i;
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uint16_t shrt;
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uint8_t byte;
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sc = device_get_softc(dev);
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if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
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slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
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return (-1);
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offset = FO_CONF_OFF(bus, slot, func, reg);
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bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
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switch (width) {
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case 1:
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i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
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r = byte;
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break;
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case 2:
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i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
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r = shrt;
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break;
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case 4:
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i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
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r = wrd;
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break;
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default:
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panic("%s: bad width", __func__);
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/* NOTREACHED */
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}
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if (i) {
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#ifdef FIRE_DEBUG
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printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
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__func__, bus, slot, func, reg);
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#endif
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r = -1;
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}
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return (r);
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return (ofw_pci_read_config_common(dev, PCIE_REGMAX, FO_CONF_OFF(bus,
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slot, func, reg), bus, slot, func, reg, width));
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}
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static void
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fire_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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uint32_t val, int width)
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{
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struct fire_softc *sc;
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bus_space_handle_t bh;
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u_long offset = 0;
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sc = device_get_softc(dev);
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if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
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slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
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return;
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offset = FO_CONF_OFF(bus, slot, func, reg);
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bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
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switch (width) {
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case 1:
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bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
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break;
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case 2:
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bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
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break;
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case 4:
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bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
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break;
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default:
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panic("%s: bad width", __func__);
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/* NOTREACHED */
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}
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ofw_pci_write_config_common(dev, PCIE_REGMAX, FO_CONF_OFF(bus, slot,
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func, reg), bus, slot, func, reg, val, width);
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}
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static int
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fire_route_interrupt(device_t bridge, device_t dev, int pin)
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{
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struct fire_softc *sc;
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struct ofw_pci_register reg;
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ofw_pci_intr_t pintr, mintr;
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ofw_pci_intr_t mintr;
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sc = device_get_softc(bridge);
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pintr = pin;
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if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
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®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
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NULL) != 0)
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return (mintr);
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device_printf(bridge, "could not route pin %d for device %d.%d\n",
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pin, pci_get_slot(dev), pci_get_function(dev));
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return (PCI_INVALID_IRQ);
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}
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static int
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fire_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct fire_softc *sc;
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sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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*result = device_get_unit(dev);
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return (0);
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case PCIB_IVAR_BUS:
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*result = sc->sc_pci_secbus;
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return (0);
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}
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return (ENOENT);
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mintr = ofw_pci_route_interrupt_common(bridge, dev, pin);
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if (!PCI_INTERRUPT_VALID(mintr))
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device_printf(bridge,
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"could not route pin %d for device %d.%d\n",
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pin, pci_get_slot(dev), pci_get_function(dev));
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return (mintr);
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}
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static void
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fire_dmamap_sync(bus_dma_tag_t dt __unused, bus_dmamap_t map,
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bus_dmasync_op_t op)
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{
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static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE);
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register_t reg, s;
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if ((map->dm_flags & DMF_LOADED) == 0)
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return;
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if ((op & BUS_DMASYNC_POSTREAD) != 0) {
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s = intr_disable();
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reg = rd(fprs);
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wr(fprs, reg | FPRS_FEF, 0);
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__asm __volatile("stda %%f0, [%0] %1"
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: : "r" (buf), "n" (ASI_BLK_COMMIT_S));
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membar(Sync);
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wr(fprs, reg, 0);
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intr_restore(s);
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} else if ((op & BUS_DMASYNC_PREWRITE) != 0)
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if ((op & BUS_DMASYNC_POSTREAD) != 0)
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ofw_pci_dmamap_sync_stst_order_common();
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else if ((op & BUS_DMASYNC_PREWRITE) != 0)
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membar(Sync);
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}
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@ -2013,121 +1855,13 @@ fire_alloc_resource(device_t bus, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct fire_softc *sc;
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struct resource *rv;
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struct rman *rm;
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sc = device_get_softc(bus);
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switch (type) {
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case SYS_RES_IRQ:
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/*
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* XXX: Don't accept blank ranges for now, only single
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* interrupts. The other case should not happen with
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* the MI PCI code...
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* XXX: This may return a resource that is out of the
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* range that was specified. Is this correct...?
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*/
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if (start != end)
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panic("%s: XXX: interrupt range", __func__);
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if (*rid == 0)
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start = end = INTMAP_VEC(sc->sc_ign, end);
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return (bus_generic_alloc_resource(bus, child, type, rid,
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start, end, count, flags));
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case SYS_RES_MEMORY:
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rm = &sc->sc_pci_mem_rman;
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break;
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case SYS_RES_IOPORT:
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rm = &sc->sc_pci_io_rman;
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break;
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default:
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return (NULL);
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if (type == SYS_RES_IRQ && *rid == 0) {
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sc = device_get_softc(bus);
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start = end = INTMAP_VEC(sc->sc_ign, end);
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}
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rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
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child);
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if (rv == NULL)
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return (NULL);
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rman_set_rid(rv, *rid);
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|
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if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type,
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*rid, rv) != 0) {
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rman_release_resource(rv);
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return (NULL);
|
||||
}
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return (rv);
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}
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|
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static int
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fire_activate_resource(device_t bus, device_t child, int type, int rid,
|
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struct resource *r)
|
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{
|
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struct fire_softc *sc;
|
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struct bus_space_tag *tag;
|
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|
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sc = device_get_softc(bus);
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switch (type) {
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case SYS_RES_IRQ:
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return (bus_generic_activate_resource(bus, child, type, rid,
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r));
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case SYS_RES_MEMORY:
|
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tag = sparc64_alloc_bus_tag(r, PCI_MEMORY_BUS_SPACE);
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if (tag == NULL)
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return (ENOMEM);
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rman_set_bustag(r, tag);
|
||||
rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] +
|
||||
rman_get_start(r));
|
||||
break;
|
||||
case SYS_RES_IOPORT:
|
||||
rman_set_bustag(r, sc->sc_pci_iot);
|
||||
rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] +
|
||||
rman_get_start(r));
|
||||
break;
|
||||
}
|
||||
return (rman_activate_resource(r));
|
||||
}
|
||||
|
||||
static int
|
||||
fire_adjust_resource(device_t bus, device_t child, int type,
|
||||
struct resource *r, u_long start, u_long end)
|
||||
{
|
||||
struct fire_softc *sc;
|
||||
struct rman *rm;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
return (bus_generic_adjust_resource(bus, child, type, r,
|
||||
start, end));
|
||||
case SYS_RES_MEMORY:
|
||||
rm = &sc->sc_pci_mem_rman;
|
||||
break;
|
||||
case SYS_RES_IOPORT:
|
||||
rm = &sc->sc_pci_io_rman;
|
||||
break;
|
||||
default:
|
||||
return (EINVAL);
|
||||
}
|
||||
if (rman_is_region_manager(r, rm) == 0)
|
||||
return (EINVAL);
|
||||
return (rman_adjust_resource(r, start, end));
|
||||
}
|
||||
|
||||
static bus_dma_tag_t
|
||||
fire_get_dma_tag(device_t bus, device_t child __unused)
|
||||
{
|
||||
struct fire_softc *sc;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
return (sc->sc_pci_dmat);
|
||||
}
|
||||
|
||||
static phandle_t
|
||||
fire_get_node(device_t bus, device_t child __unused)
|
||||
{
|
||||
struct fire_softc *sc;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
/* We only have one child, the PCI bus, which needs our own node. */
|
||||
return (sc->sc_node);
|
||||
return (ofw_pci_alloc_resource(bus, child, type, rid, start, end,
|
||||
count, flags));
|
||||
}
|
||||
|
||||
static u_int
|
||||
|
@ -30,7 +30,6 @@
|
||||
#define _SPARC64_PCI_FIREREG_H_
|
||||
|
||||
#define FIRE_NINTR 3 /* 2 OFW + 1 MSIq */
|
||||
#define FIRE_NRANGE 4
|
||||
#define FIRE_NREG 2
|
||||
|
||||
#define FIRE_PCI 0
|
||||
|
@ -32,6 +32,12 @@
|
||||
#define _SPARC64_PCI_FIREVAR_H_
|
||||
|
||||
struct fire_softc {
|
||||
/*
|
||||
* This is here so that we can hook up the common bus interface
|
||||
* methods in ofw_pci.c directly.
|
||||
*/
|
||||
struct ofw_pci_softc sc_ops;
|
||||
|
||||
struct iommu_state sc_is;
|
||||
struct bus_dma_methods sc_dma_methods;
|
||||
|
||||
@ -42,13 +48,6 @@ struct fire_softc {
|
||||
struct resource *sc_irq_res[FIRE_NINTR];
|
||||
void *sc_ihand[FIRE_NINTR];
|
||||
|
||||
struct rman sc_pci_mem_rman;
|
||||
struct rman sc_pci_io_rman;
|
||||
bus_space_handle_t sc_pci_bh[FIRE_NRANGE];
|
||||
bus_space_tag_t sc_pci_cfgt;
|
||||
bus_space_tag_t sc_pci_iot;
|
||||
bus_dma_tag_t sc_pci_dmat;
|
||||
|
||||
device_t sc_dev;
|
||||
|
||||
uint64_t *sc_msiq;
|
||||
@ -66,8 +65,6 @@ struct fire_softc {
|
||||
uint32_t sc_msiq_first;
|
||||
uint32_t sc_msiq_ino_first;
|
||||
|
||||
phandle_t sc_node;
|
||||
|
||||
u_int sc_mode;
|
||||
#define FIRE_MODE_FIRE 0
|
||||
#define FIRE_MODE_OBERON 1
|
||||
@ -87,11 +84,6 @@ struct fire_softc {
|
||||
uint32_t sc_stats_tlu_oe_rx_err;
|
||||
uint32_t sc_stats_tlu_oe_tx_err;
|
||||
uint32_t sc_stats_ubc_dmardue;
|
||||
|
||||
uint8_t sc_pci_secbus;
|
||||
uint8_t sc_pci_subbus;
|
||||
|
||||
struct ofw_bus_iinfo sc_pci_iinfo;
|
||||
};
|
||||
|
||||
#endif /* !_SPARC64_PCI_FIREVAR_H_ */
|
||||
|
406
sys/sparc64/pci/ofw_pci.c
Normal file
406
sys/sparc64/pci/ofw_pci.c
Normal file
@ -0,0 +1,406 @@
|
||||
/*-
|
||||
* Copyright (c) 1999, 2000 Matthew R. Green
|
||||
* Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
|
||||
* Copyright (c) 2005 - 2015 by Marius Strobl <marius@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* from: NetBSD: psycho.c,v 1.35 2001/09/10 16:17:06 eeh Exp
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include "opt_ofw_pci.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/rman.h>
|
||||
|
||||
#include <dev/ofw/ofw_bus.h>
|
||||
#include <dev/ofw/ofw_pci.h>
|
||||
#include <dev/ofw/openfirm.h>
|
||||
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <dev/pci/pcivar.h>
|
||||
|
||||
#include <machine/asi.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/bus_private.h>
|
||||
#include <machine/cpufunc.h>
|
||||
#include <machine/fsr.h>
|
||||
#include <machine/resource.h>
|
||||
|
||||
#include <sparc64/pci/ofw_pci.h>
|
||||
|
||||
int
|
||||
ofw_pci_attach_common(device_t dev, bus_dma_tag_t dmat, u_long iosize,
|
||||
u_long memsize)
|
||||
{
|
||||
struct ofw_pci_softc *sc;
|
||||
struct ofw_pci_ranges *range;
|
||||
phandle_t node;
|
||||
uint32_t prop_array[2];
|
||||
u_int i, j, nrange;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
node = ofw_bus_get_node(dev);
|
||||
sc->sc_node = node;
|
||||
sc->sc_pci_dmat = dmat;
|
||||
|
||||
/* Initialize memory and I/O rmans. */
|
||||
sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
|
||||
sc->sc_pci_io_rman.rm_descr = "PCI I/O Ports";
|
||||
if (rman_init(&sc->sc_pci_io_rman) != 0 ||
|
||||
rman_manage_region(&sc->sc_pci_io_rman, 0, iosize) != 0) {
|
||||
device_printf(dev, "failed to set up I/O rman\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
|
||||
sc->sc_pci_mem_rman.rm_descr = "PCI Memory";
|
||||
if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
|
||||
rman_manage_region(&sc->sc_pci_mem_rman, 0, memsize) != 0) {
|
||||
device_printf(dev, "failed to set up memory rman\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
/*
|
||||
* Find the addresses of the various bus spaces. The physical
|
||||
* start addresses of the ranges are the configuration, I/O and
|
||||
* memory handles. There should not be multiple ones of one kind.
|
||||
*/
|
||||
nrange = OF_getprop_alloc(node, "ranges", sizeof(*range),
|
||||
(void **)&range);
|
||||
for (i = 0; i < nrange; i++) {
|
||||
j = OFW_PCI_RANGE_CS(&range[i]);
|
||||
if (sc->sc_pci_bh[j] != 0) {
|
||||
device_printf(dev, "duplicate range for space %d\n",
|
||||
j);
|
||||
free(range, M_OFWPROP);
|
||||
return (EINVAL);
|
||||
}
|
||||
sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
|
||||
}
|
||||
free(range, M_OFWPROP);
|
||||
|
||||
/*
|
||||
* Make sure that the expected ranges are actually present.
|
||||
* The OFW_PCI_CS_MEM64 one is not currently used.
|
||||
*/
|
||||
if (sc->sc_pci_bh[OFW_PCI_CS_CONFIG] == 0) {
|
||||
device_printf(dev, "missing CONFIG range\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
if (sc->sc_pci_bh[OFW_PCI_CS_IO] == 0) {
|
||||
device_printf(dev, "missing IO range\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
if (sc->sc_pci_bh[OFW_PCI_CS_MEM32] == 0) {
|
||||
device_printf(dev, "missing MEM32 range\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
/* Allocate our tags. */
|
||||
sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, PCI_IO_BUS_SPACE);
|
||||
if (sc->sc_pci_iot == NULL) {
|
||||
device_printf(dev, "could not allocate PCI I/O tag\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, PCI_CONFIG_BUS_SPACE);
|
||||
if (sc->sc_pci_cfgt == NULL) {
|
||||
device_printf(dev,
|
||||
"could not allocate PCI configuration space tag\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the bus range from the firmware.
|
||||
*/
|
||||
i = OF_getprop(node, "bus-range", (void *)prop_array,
|
||||
sizeof(prop_array));
|
||||
if (i == -1) {
|
||||
device_printf(dev, "could not get bus-range\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
if (i != sizeof(prop_array)) {
|
||||
device_printf(dev, "broken bus-range (%d)", i);
|
||||
return (EINVAL);
|
||||
}
|
||||
sc->sc_pci_secbus = prop_array[0];
|
||||
sc->sc_pci_subbus = prop_array[1];
|
||||
if (bootverbose != 0)
|
||||
device_printf(dev, "bus range %u to %u; PCI bus %d\n",
|
||||
sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
|
||||
|
||||
ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
ofw_pci_read_config_common(device_t dev, u_int regmax, u_long offset,
|
||||
u_int bus, u_int slot, u_int func, u_int reg, int width)
|
||||
{
|
||||
struct ofw_pci_softc *sc;
|
||||
bus_space_handle_t bh;
|
||||
uint32_t r, wrd;
|
||||
int i;
|
||||
uint16_t shrt;
|
||||
uint8_t byte;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
|
||||
slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > regmax)
|
||||
return (-1);
|
||||
|
||||
bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
|
||||
switch (width) {
|
||||
case 1:
|
||||
i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
|
||||
r = byte;
|
||||
break;
|
||||
case 2:
|
||||
i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
|
||||
r = shrt;
|
||||
break;
|
||||
case 4:
|
||||
i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
|
||||
r = wrd;
|
||||
break;
|
||||
default:
|
||||
panic("%s: bad width %d", __func__, width);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
if (i) {
|
||||
#ifdef OFW_PCI_DEBUG
|
||||
printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
|
||||
__func__, bus, slot, func, reg);
|
||||
#endif
|
||||
r = -1;
|
||||
}
|
||||
return (r);
|
||||
}
|
||||
|
||||
void
|
||||
ofw_pci_write_config_common(device_t dev, u_int regmax, u_long offset,
|
||||
u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int width)
|
||||
{
|
||||
struct ofw_pci_softc *sc;
|
||||
bus_space_handle_t bh;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
|
||||
slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > regmax)
|
||||
return;
|
||||
|
||||
bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
|
||||
switch (width) {
|
||||
case 1:
|
||||
bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
|
||||
break;
|
||||
case 2:
|
||||
bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
|
||||
break;
|
||||
case 4:
|
||||
bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
|
||||
break;
|
||||
default:
|
||||
panic("%s: bad width %d", __func__, width);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
}
|
||||
|
||||
ofw_pci_intr_t
|
||||
ofw_pci_route_interrupt_common(device_t bridge, device_t dev, int pin)
|
||||
{
|
||||
struct ofw_pci_softc *sc;
|
||||
struct ofw_pci_register reg;
|
||||
ofw_pci_intr_t pintr, mintr;
|
||||
|
||||
sc = device_get_softc(bridge);
|
||||
pintr = pin;
|
||||
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
|
||||
®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
|
||||
NULL) != 0)
|
||||
return (mintr);
|
||||
return (PCI_INVALID_IRQ);
|
||||
}
|
||||
|
||||
void
|
||||
ofw_pci_dmamap_sync_stst_order_common(void)
|
||||
{
|
||||
static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE);
|
||||
register_t reg, s;
|
||||
|
||||
s = intr_disable();
|
||||
reg = rd(fprs);
|
||||
wr(fprs, reg | FPRS_FEF, 0);
|
||||
__asm __volatile("stda %%f0, [%0] %1"
|
||||
: : "r" (buf), "n" (ASI_BLK_COMMIT_S));
|
||||
membar(Sync);
|
||||
wr(fprs, reg, 0);
|
||||
intr_restore(s);
|
||||
}
|
||||
|
||||
int
|
||||
ofw_pci_read_ivar(device_t dev, device_t child __unused, int which,
|
||||
uintptr_t *result)
|
||||
{
|
||||
struct ofw_pci_softc *sc;
|
||||
|
||||
switch (which) {
|
||||
case PCIB_IVAR_DOMAIN:
|
||||
*result = device_get_unit(dev);
|
||||
return (0);
|
||||
case PCIB_IVAR_BUS:
|
||||
sc = device_get_softc(dev);
|
||||
*result = sc->sc_pci_secbus;
|
||||
return (0);
|
||||
}
|
||||
return (ENOENT);
|
||||
}
|
||||
|
||||
struct resource *
|
||||
ofw_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
|
||||
u_long start, u_long end, u_long count, u_int flags)
|
||||
{
|
||||
struct ofw_pci_softc *sc;
|
||||
struct resource *rv;
|
||||
struct rman *rm;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
/*
|
||||
* XXX: Don't accept blank ranges for now, only single
|
||||
* interrupts. The other case should not happen with
|
||||
* the MI PCI code ...
|
||||
* XXX: This may return a resource that is out of the
|
||||
* range that was specified. Is this correct ...?
|
||||
*/
|
||||
if (start != end)
|
||||
panic("%s: XXX: interrupt range", __func__);
|
||||
return (bus_generic_alloc_resource(bus, child, type, rid,
|
||||
start, end, count, flags));
|
||||
case SYS_RES_MEMORY:
|
||||
rm = &sc->sc_pci_mem_rman;
|
||||
break;
|
||||
case SYS_RES_IOPORT:
|
||||
rm = &sc->sc_pci_io_rman;
|
||||
break;
|
||||
default:
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
|
||||
child);
|
||||
if (rv == NULL)
|
||||
return (NULL);
|
||||
rman_set_rid(rv, *rid);
|
||||
|
||||
if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type,
|
||||
*rid, rv) != 0) {
|
||||
rman_release_resource(rv);
|
||||
return (NULL);
|
||||
}
|
||||
return (rv);
|
||||
}
|
||||
|
||||
int
|
||||
ofw_pci_activate_resource(device_t bus, device_t child, int type, int rid,
|
||||
struct resource *r)
|
||||
{
|
||||
struct ofw_pci_softc *sc;
|
||||
struct bus_space_tag *tag;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
return (bus_generic_activate_resource(bus, child, type, rid,
|
||||
r));
|
||||
case SYS_RES_MEMORY:
|
||||
tag = sparc64_alloc_bus_tag(r, PCI_MEMORY_BUS_SPACE);
|
||||
if (tag == NULL)
|
||||
return (ENOMEM);
|
||||
rman_set_bustag(r, tag);
|
||||
rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] +
|
||||
rman_get_start(r));
|
||||
break;
|
||||
case SYS_RES_IOPORT:
|
||||
rman_set_bustag(r, sc->sc_pci_iot);
|
||||
rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] +
|
||||
rman_get_start(r));
|
||||
break;
|
||||
}
|
||||
return (rman_activate_resource(r));
|
||||
}
|
||||
|
||||
int
|
||||
ofw_pci_adjust_resource(device_t bus, device_t child, int type,
|
||||
struct resource *r, u_long start, u_long end)
|
||||
{
|
||||
struct ofw_pci_softc *sc;
|
||||
struct rman *rm;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
return (bus_generic_adjust_resource(bus, child, type, r,
|
||||
start, end));
|
||||
case SYS_RES_MEMORY:
|
||||
rm = &sc->sc_pci_mem_rman;
|
||||
break;
|
||||
case SYS_RES_IOPORT:
|
||||
rm = &sc->sc_pci_io_rman;
|
||||
break;
|
||||
default:
|
||||
return (EINVAL);
|
||||
}
|
||||
if (rman_is_region_manager(r, rm) == 0)
|
||||
return (EINVAL);
|
||||
return (rman_adjust_resource(r, start, end));
|
||||
}
|
||||
|
||||
bus_dma_tag_t
|
||||
ofw_pci_get_dma_tag(device_t bus, device_t child __unused)
|
||||
{
|
||||
struct ofw_pci_softc *sc;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
return (sc->sc_pci_dmat);
|
||||
}
|
||||
|
||||
phandle_t
|
||||
ofw_pci_get_node(device_t bus, device_t child __unused)
|
||||
{
|
||||
struct ofw_pci_softc *sc;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
/* We only have one child, the PCI bus, which needs our own node. */
|
||||
return (sc->sc_node);
|
||||
}
|
@ -62,6 +62,8 @@
|
||||
#ifndef _SPARC64_PCI_OFW_PCI_H_
|
||||
#define _SPARC64_PCI_OFW_PCI_H_
|
||||
|
||||
#include <sys/rman.h>
|
||||
|
||||
#include <dev/ofw/ofw_bus_subr.h>
|
||||
|
||||
#include "ofw_pci_if.h"
|
||||
@ -73,6 +75,7 @@ typedef uint32_t ofw_pci_intr_t;
|
||||
#define OFW_PCI_CS_IO 0x01
|
||||
#define OFW_PCI_CS_MEM32 0x02
|
||||
#define OFW_PCI_CS_MEM64 0x03
|
||||
#define OFW_PCI_NUM_CS 4
|
||||
|
||||
/* OFW device types */
|
||||
#define OFW_TYPE_PCI "pci"
|
||||
@ -124,4 +127,44 @@ struct ofw_pci_ranges {
|
||||
/* default values */
|
||||
#define OFW_PCI_LATENCY 64
|
||||
|
||||
/*
|
||||
* Common and generic parts of host-PCI-bridge support
|
||||
*/
|
||||
|
||||
struct ofw_pci_softc {
|
||||
struct rman sc_pci_mem_rman;
|
||||
struct rman sc_pci_io_rman;
|
||||
|
||||
bus_space_handle_t sc_pci_bh[OFW_PCI_NUM_CS];
|
||||
bus_space_tag_t sc_pci_cfgt;
|
||||
bus_space_tag_t sc_pci_iot;
|
||||
bus_dma_tag_t sc_pci_dmat;
|
||||
|
||||
struct ofw_bus_iinfo sc_pci_iinfo;
|
||||
|
||||
phandle_t sc_node;
|
||||
|
||||
uint8_t sc_pci_secbus;
|
||||
uint8_t sc_pci_subbus;
|
||||
};
|
||||
|
||||
int ofw_pci_attach_common(device_t dev, bus_dma_tag_t dmat, u_long iosize,
|
||||
u_long memsize);
|
||||
uint32_t ofw_pci_read_config_common(device_t dev, u_int regmax, u_long offset,
|
||||
u_int bus, u_int slot, u_int func, u_int reg, int width);
|
||||
void ofw_pci_write_config_common(device_t dev, u_int regmax, u_long offset,
|
||||
u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int width);
|
||||
ofw_pci_intr_t ofw_pci_route_interrupt_common(device_t bridge, device_t dev,
|
||||
int pin);
|
||||
|
||||
void ofw_pci_dmamap_sync_stst_order_common(void);
|
||||
|
||||
bus_activate_resource_t ofw_pci_activate_resource;
|
||||
bus_adjust_resource_t ofw_pci_adjust_resource;
|
||||
bus_alloc_resource_t ofw_pci_alloc_resource;
|
||||
bus_get_dma_tag_t ofw_pci_get_dma_tag;
|
||||
bus_read_ivar_t ofw_pci_read_ivar;
|
||||
|
||||
ofw_bus_get_node_t ofw_pci_get_node;
|
||||
|
||||
#endif /* ! _SPARC64_PCI_OFW_PCI_H_ */
|
||||
|
@ -57,7 +57,6 @@ __FBSDID("$FreeBSD$");
|
||||
#include <sys/sysctl.h>
|
||||
|
||||
#include <dev/ofw/ofw_bus.h>
|
||||
#include <dev/ofw/ofw_pci.h>
|
||||
#include <dev/ofw/openfirm.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
@ -110,17 +109,12 @@ static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
|
||||
*/
|
||||
static device_probe_t psycho_probe;
|
||||
static device_attach_t psycho_attach;
|
||||
static bus_read_ivar_t psycho_read_ivar;
|
||||
static bus_setup_intr_t psycho_setup_intr;
|
||||
static bus_alloc_resource_t psycho_alloc_resource;
|
||||
static bus_activate_resource_t psycho_activate_resource;
|
||||
static bus_adjust_resource_t psycho_adjust_resource;
|
||||
static bus_get_dma_tag_t psycho_get_dma_tag;
|
||||
static pcib_maxslots_t psycho_maxslots;
|
||||
static pcib_read_config_t psycho_read_config;
|
||||
static pcib_write_config_t psycho_write_config;
|
||||
static pcib_route_interrupt_t psycho_route_interrupt;
|
||||
static ofw_bus_get_node_t psycho_get_node;
|
||||
static ofw_pci_setup_device_t psycho_setup_device;
|
||||
|
||||
static device_method_t psycho_methods[] = {
|
||||
@ -132,15 +126,15 @@ static device_method_t psycho_methods[] = {
|
||||
DEVMETHOD(device_resume, bus_generic_resume),
|
||||
|
||||
/* Bus interface */
|
||||
DEVMETHOD(bus_read_ivar, psycho_read_ivar),
|
||||
DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar),
|
||||
DEVMETHOD(bus_setup_intr, psycho_setup_intr),
|
||||
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
||||
DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
|
||||
DEVMETHOD(bus_activate_resource, psycho_activate_resource),
|
||||
DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource),
|
||||
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
||||
DEVMETHOD(bus_adjust_resource, psycho_adjust_resource),
|
||||
DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource),
|
||||
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
||||
DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag),
|
||||
DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag),
|
||||
|
||||
/* pcib interface */
|
||||
DEVMETHOD(pcib_maxslots, psycho_maxslots),
|
||||
@ -149,7 +143,7 @@ static device_method_t psycho_methods[] = {
|
||||
DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
|
||||
|
||||
/* ofw_bus interface */
|
||||
DEVMETHOD(ofw_bus_get_node, psycho_get_node),
|
||||
DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node),
|
||||
|
||||
/* ofw_pci interface */
|
||||
DEVMETHOD(ofw_pci_setup_device, psycho_setup_device),
|
||||
@ -287,12 +281,12 @@ psycho_attach(device_t dev)
|
||||
{
|
||||
struct psycho_icarg *pica;
|
||||
struct psycho_softc *asc, *sc, *osc;
|
||||
struct ofw_pci_ranges *range;
|
||||
const struct psycho_desc *desc;
|
||||
bus_addr_t intrclr, intrmap;
|
||||
bus_dma_tag_t dmat;
|
||||
uint64_t csr, dr;
|
||||
phandle_t node;
|
||||
uint32_t dvmabase, prop, prop_array[2];
|
||||
uint32_t dvmabase, prop;
|
||||
u_int rerun, ver;
|
||||
int i, j;
|
||||
|
||||
@ -300,7 +294,6 @@ psycho_attach(device_t dev)
|
||||
sc = device_get_softc(dev);
|
||||
desc = psycho_get_desc(dev);
|
||||
|
||||
sc->sc_node = node;
|
||||
sc->sc_dev = dev;
|
||||
sc->sc_mode = desc->pd_mode;
|
||||
|
||||
@ -366,6 +359,7 @@ psycho_attach(device_t dev)
|
||||
panic("%s: mutex not initialized", __func__);
|
||||
sc->sc_mtx = osc->sc_mtx;
|
||||
}
|
||||
SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
|
||||
|
||||
csr = PSYCHO_READ8(sc, PSR_CS);
|
||||
ver = PSYCHO_GCSR_VERS(csr);
|
||||
@ -434,43 +428,6 @@ psycho_attach(device_t dev)
|
||||
} else
|
||||
dvmabase = -1;
|
||||
|
||||
/* Initialize memory and I/O rmans. */
|
||||
sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
|
||||
sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports";
|
||||
if (rman_init(&sc->sc_pci_io_rman) != 0 ||
|
||||
rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0)
|
||||
panic("%s: failed to set up I/O rman", __func__);
|
||||
sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
|
||||
sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory";
|
||||
if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
|
||||
rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
|
||||
panic("%s: failed to set up memory rman", __func__);
|
||||
|
||||
i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
|
||||
/*
|
||||
* Make sure that the expected ranges are present. The
|
||||
* OFW_PCI_CS_MEM64 one is not currently used though.
|
||||
*/
|
||||
if (i != PSYCHO_NRANGE)
|
||||
panic("%s: unsupported number of ranges", __func__);
|
||||
/*
|
||||
* Find the addresses of the various bus spaces.
|
||||
* There should not be multiple ones of one kind.
|
||||
* The physical start addresses of the ranges are the configuration,
|
||||
* memory and I/O handles.
|
||||
*/
|
||||
for (i = 0; i < PSYCHO_NRANGE; i++) {
|
||||
j = OFW_PCI_RANGE_CS(&range[i]);
|
||||
if (sc->sc_pci_bh[j] != 0)
|
||||
panic("%s: duplicate range for space %d",
|
||||
__func__, j);
|
||||
sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
|
||||
}
|
||||
free(range, M_OFWPROP);
|
||||
|
||||
/* Register the softc, this is needed for paired Psychos. */
|
||||
SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
|
||||
|
||||
/*
|
||||
* If we're a Hummingbird/Sabre or the first of a pair of Psychos
|
||||
* to arrive here, do the interrupt setup and start up the IOMMU.
|
||||
@ -571,37 +528,21 @@ psycho_attach(device_t dev)
|
||||
iommu_reset(sc->sc_is);
|
||||
}
|
||||
|
||||
/* Allocate our tags. */
|
||||
sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, PCI_IO_BUS_SPACE);
|
||||
if (sc->sc_pci_iot == NULL)
|
||||
panic("%s: could not allocate PCI I/O tag", __func__);
|
||||
sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, PCI_CONFIG_BUS_SPACE);
|
||||
if (sc->sc_pci_cfgt == NULL)
|
||||
panic("%s: could not allocate PCI configuration space tag",
|
||||
__func__);
|
||||
/* Create our DMA tag. */
|
||||
if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
|
||||
sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
|
||||
0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
|
||||
0xff, 0xffffffff, 0, NULL, NULL, &dmat) != 0)
|
||||
panic("%s: could not create PCI DMA tag", __func__);
|
||||
/* Customize the tag. */
|
||||
sc->sc_pci_dmat->dt_cookie = sc->sc_is;
|
||||
sc->sc_pci_dmat->dt_mt = sc->sc_dma_methods;
|
||||
dmat->dt_cookie = sc->sc_is;
|
||||
dmat->dt_mt = sc->sc_dma_methods;
|
||||
|
||||
i = OF_getprop(node, "bus-range", (void *)prop_array,
|
||||
sizeof(prop_array));
|
||||
if (i == -1)
|
||||
panic("%s: could not get bus-range", __func__);
|
||||
if (i != sizeof(prop_array))
|
||||
panic("%s: broken bus-range (%d)", __func__, i);
|
||||
sc->sc_pci_secbus = prop_array[0];
|
||||
sc->sc_pci_subbus = prop_array[1];
|
||||
if (bootverbose)
|
||||
device_printf(dev, "bus range %u to %u; PCI bus %d\n",
|
||||
sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
|
||||
if (ofw_pci_attach_common(dev, dmat, PSYCHO_IO_SIZE,
|
||||
PSYCHO_MEM_SIZE) != 0)
|
||||
panic("%s: ofw_pci_attach_common() failed", __func__);
|
||||
|
||||
/* Clear any pending PCI error bits. */
|
||||
PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
|
||||
PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
|
||||
PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
|
||||
PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_ops.sc_pci_secbus,
|
||||
PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
|
||||
PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
|
||||
PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
|
||||
@ -664,20 +605,20 @@ psycho_attach(device_t dev)
|
||||
* Set the latency timer register as this isn't always done by the
|
||||
* firmware.
|
||||
*/
|
||||
PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
|
||||
PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
|
||||
PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
|
||||
|
||||
for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t))
|
||||
le16enc(&sc->sc_pci_hpbcfg[i], bus_space_read_2(
|
||||
sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
|
||||
PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
|
||||
le16enc(&sc->sc_pci_hpbcfg[i],
|
||||
bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
|
||||
sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
|
||||
PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus, PCS_DEVICE,
|
||||
PCS_FUNC, i)));
|
||||
for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t))
|
||||
sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_pci_cfgt,
|
||||
sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
|
||||
sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
|
||||
sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_ops.sc_pci_cfgt,
|
||||
sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
|
||||
sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
|
||||
|
||||
ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
|
||||
/*
|
||||
* On E250 the interrupt map entry for the EBus bridge is wrong,
|
||||
* causing incorrect interrupts to be assigned to some devices on
|
||||
@ -688,9 +629,9 @@ psycho_attach(device_t dev)
|
||||
* EBus devices will be used directly instead.
|
||||
*/
|
||||
if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
|
||||
sc->sc_pci_iinfo.opi_imapmsk != NULL)
|
||||
*(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[
|
||||
sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
|
||||
sc->sc_ops.sc_pci_iinfo.opi_imapmsk != NULL)
|
||||
*(ofw_pci_intr_t *)(&sc->sc_ops.sc_pci_iinfo.opi_imapmsk[
|
||||
sc->sc_ops.sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
|
||||
|
||||
device_add_child(dev, "pci", -1);
|
||||
return (bus_generic_attach(dev));
|
||||
@ -924,20 +865,8 @@ psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
|
||||
int width)
|
||||
{
|
||||
struct psycho_softc *sc;
|
||||
bus_space_handle_t bh;
|
||||
u_long offset = 0;
|
||||
uint8_t byte;
|
||||
uint16_t shrt;
|
||||
uint32_t r, wrd;
|
||||
int i;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
|
||||
slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
|
||||
return (-1);
|
||||
|
||||
bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
|
||||
|
||||
/*
|
||||
* The Hummingbird and Sabre bridges are picky in that they
|
||||
* only allow their config space to be accessed using the
|
||||
@ -953,9 +882,9 @@ psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
|
||||
* The Psycho bridges contain a dupe of their header at 0x80
|
||||
* which we nullify that way also.
|
||||
*/
|
||||
if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE &&
|
||||
if (bus == sc->sc_ops.sc_pci_secbus && slot == PCS_DEVICE &&
|
||||
func == PCS_FUNC) {
|
||||
if (offset % width != 0)
|
||||
if (reg % width != 0)
|
||||
return (-1);
|
||||
|
||||
if (reg >= sizeof(sc->sc_pci_hpbcfg))
|
||||
@ -964,8 +893,9 @@ psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
|
||||
if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
|
||||
reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
|
||||
le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
|
||||
bus_space_read_2(sc->sc_pci_cfgt, bh,
|
||||
PSYCHO_CONF_OFF(sc->sc_pci_secbus,
|
||||
bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
|
||||
sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
|
||||
PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus,
|
||||
PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
|
||||
|
||||
switch (width) {
|
||||
@ -978,79 +908,29 @@ psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
|
||||
}
|
||||
}
|
||||
|
||||
offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
|
||||
switch (width) {
|
||||
case 1:
|
||||
i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
|
||||
r = byte;
|
||||
break;
|
||||
case 2:
|
||||
i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
|
||||
r = shrt;
|
||||
break;
|
||||
case 4:
|
||||
i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
|
||||
r = wrd;
|
||||
break;
|
||||
default:
|
||||
panic("%s: bad width", __func__);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
if (i) {
|
||||
#ifdef PSYCHO_DEBUG
|
||||
printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
|
||||
__func__, bus, slot, func, reg);
|
||||
#endif
|
||||
r = -1;
|
||||
}
|
||||
return (r);
|
||||
return (ofw_pci_read_config_common(dev, PCI_REGMAX,
|
||||
PSYCHO_CONF_OFF(bus, slot, func, reg), bus, slot, func, reg,
|
||||
width));
|
||||
}
|
||||
|
||||
static void
|
||||
psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
|
||||
u_int reg, uint32_t val, int width)
|
||||
{
|
||||
struct psycho_softc *sc;
|
||||
bus_space_handle_t bh;
|
||||
u_long offset = 0;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
|
||||
slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
|
||||
return;
|
||||
|
||||
offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
|
||||
bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
|
||||
switch (width) {
|
||||
case 1:
|
||||
bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
|
||||
break;
|
||||
case 2:
|
||||
bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
|
||||
break;
|
||||
case 4:
|
||||
bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
|
||||
break;
|
||||
default:
|
||||
panic("%s: bad width", __func__);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
ofw_pci_write_config_common(dev, PCI_REGMAX, PSYCHO_CONF_OFF(bus,
|
||||
slot, func, reg), bus, slot, func, reg, val, width);
|
||||
}
|
||||
|
||||
static int
|
||||
psycho_route_interrupt(device_t bridge, device_t dev, int pin)
|
||||
{
|
||||
struct psycho_softc *sc;
|
||||
struct ofw_pci_register reg;
|
||||
bus_addr_t intrmap;
|
||||
ofw_pci_intr_t pintr, mintr;
|
||||
ofw_pci_intr_t mintr;
|
||||
|
||||
sc = device_get_softc(bridge);
|
||||
pintr = pin;
|
||||
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
|
||||
®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
|
||||
NULL))
|
||||
mintr = ofw_pci_route_interrupt_common(bridge, dev, pin);
|
||||
if (PCI_INTERRUPT_VALID(mintr))
|
||||
return (mintr);
|
||||
/*
|
||||
* If this is outside of the range for an intpin, it's likely a full
|
||||
@ -1069,6 +949,7 @@ psycho_route_interrupt(device_t bridge, device_t dev, int pin)
|
||||
* for bus A are one-based, while those for bus B seemingly have an
|
||||
* offset of 2 (hence the factor of 3 below).
|
||||
*/
|
||||
sc = device_get_softc(dev);
|
||||
intrmap = PSR_PCIA0_INT_MAP +
|
||||
8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
|
||||
mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
|
||||
@ -1078,23 +959,6 @@ psycho_route_interrupt(device_t bridge, device_t dev, int pin)
|
||||
return (mintr);
|
||||
}
|
||||
|
||||
static int
|
||||
psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
|
||||
{
|
||||
struct psycho_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
switch (which) {
|
||||
case PCIB_IVAR_DOMAIN:
|
||||
*result = device_get_unit(dev);
|
||||
return (0);
|
||||
case PCIB_IVAR_BUS:
|
||||
*result = sc->sc_pci_secbus;
|
||||
return (0);
|
||||
}
|
||||
return (ENOENT);
|
||||
}
|
||||
|
||||
static void
|
||||
sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
|
||||
{
|
||||
@ -1177,120 +1041,13 @@ psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
|
||||
u_long start, u_long end, u_long count, u_int flags)
|
||||
{
|
||||
struct psycho_softc *sc;
|
||||
struct resource *rv;
|
||||
struct rman *rm;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
/*
|
||||
* XXX: Don't accept blank ranges for now, only single
|
||||
* interrupts. The other case should not happen with
|
||||
* the MI PCI code...
|
||||
* XXX: This may return a resource that is out of the
|
||||
* range that was specified. Is this correct...?
|
||||
*/
|
||||
if (start != end)
|
||||
panic("%s: XXX: interrupt range", __func__);
|
||||
if (type == SYS_RES_IRQ) {
|
||||
sc = device_get_softc(bus);
|
||||
start = end = INTMAP_VEC(sc->sc_ign, end);
|
||||
return (bus_generic_alloc_resource(bus, child, type, rid,
|
||||
start, end, count, flags));
|
||||
case SYS_RES_MEMORY:
|
||||
rm = &sc->sc_pci_mem_rman;
|
||||
break;
|
||||
case SYS_RES_IOPORT:
|
||||
rm = &sc->sc_pci_io_rman;
|
||||
break;
|
||||
default:
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
|
||||
child);
|
||||
if (rv == NULL)
|
||||
return (NULL);
|
||||
rman_set_rid(rv, *rid);
|
||||
|
||||
if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type,
|
||||
*rid, rv) != 0) {
|
||||
rman_release_resource(rv);
|
||||
return (NULL);
|
||||
}
|
||||
return (rv);
|
||||
}
|
||||
|
||||
static int
|
||||
psycho_activate_resource(device_t bus, device_t child, int type, int rid,
|
||||
struct resource *r)
|
||||
{
|
||||
struct psycho_softc *sc;
|
||||
struct bus_space_tag *tag;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
return (bus_generic_activate_resource(bus, child, type, rid,
|
||||
r));
|
||||
case SYS_RES_MEMORY:
|
||||
tag = sparc64_alloc_bus_tag(r, PCI_MEMORY_BUS_SPACE);
|
||||
if (tag == NULL)
|
||||
return (ENOMEM);
|
||||
rman_set_bustag(r, tag);
|
||||
rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] +
|
||||
rman_get_start(r));
|
||||
break;
|
||||
case SYS_RES_IOPORT:
|
||||
rman_set_bustag(r, sc->sc_pci_iot);
|
||||
rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] +
|
||||
rman_get_start(r));
|
||||
break;
|
||||
}
|
||||
return (rman_activate_resource(r));
|
||||
}
|
||||
|
||||
static int
|
||||
psycho_adjust_resource(device_t bus, device_t child, int type,
|
||||
struct resource *r, u_long start, u_long end)
|
||||
{
|
||||
struct psycho_softc *sc;
|
||||
struct rman *rm;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
return (bus_generic_adjust_resource(bus, child, type, r,
|
||||
start, end));
|
||||
case SYS_RES_MEMORY:
|
||||
rm = &sc->sc_pci_mem_rman;
|
||||
break;
|
||||
case SYS_RES_IOPORT:
|
||||
rm = &sc->sc_pci_io_rman;
|
||||
break;
|
||||
default:
|
||||
return (EINVAL);
|
||||
}
|
||||
if (rman_is_region_manager(r, rm) == 0)
|
||||
return (EINVAL);
|
||||
return (rman_adjust_resource(r, start, end));
|
||||
}
|
||||
|
||||
static bus_dma_tag_t
|
||||
psycho_get_dma_tag(device_t bus, device_t child __unused)
|
||||
{
|
||||
struct psycho_softc *sc;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
return (sc->sc_pci_dmat);
|
||||
}
|
||||
|
||||
static phandle_t
|
||||
psycho_get_node(device_t bus, device_t child __unused)
|
||||
{
|
||||
struct psycho_softc *sc;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
/* We only have one child, the PCI bus, which needs our own node. */
|
||||
return (sc->sc_node);
|
||||
return (ofw_pci_alloc_resource(bus, child, type, rid, start, end,
|
||||
count, flags));
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -73,7 +73,6 @@
|
||||
*/
|
||||
|
||||
#define PSYCHO_NINTR 6
|
||||
#define PSYCHO_NRANGE 4
|
||||
|
||||
/*
|
||||
* Psycho register offsets
|
||||
@ -121,7 +120,7 @@
|
||||
#define PSR_PWRMGT_INT_MAP 0x1090 /* power mgmt wake interrupt map reg */
|
||||
#define PSR_FFB0_INT_MAP 0x1098 /* FFB0 graphics interrupt map reg */
|
||||
#define PSR_FFB1_INT_MAP 0x10a0 /* FFB1 graphics interrupt map reg */
|
||||
/* Note: clear interrupt 0 registers are not really used */
|
||||
/* Note: Clear interrupt 0 registers are not really used. */
|
||||
#define PSR_PCIA0_INT_CLR 0x1400 /* PCI a slot 0 clear int regs 0..3 */
|
||||
#define PSR_PCIA1_INT_CLR 0x1420 /* PCI a slot 1 clear int regs 0..3 */
|
||||
#define PSR_PCIA2_INT_CLR 0x1440 /* PCI a slot 2 clear int regs 0..3 */
|
||||
@ -165,6 +164,7 @@
|
||||
#define PSR_PCI_INT_DIAG 0xa800 /* PCI int state diag reg */
|
||||
#define PSR_OBIO_INT_DIAG 0xa808 /* OBIO and misc int state diag reg */
|
||||
#define PSR_STRBUF_DIAG 0xb000 /* Streaming buffer diag regs */
|
||||
|
||||
/*
|
||||
* Here is the rest of the map, which we're not specifying:
|
||||
*
|
||||
@ -176,7 +176,7 @@
|
||||
* 1ff.0000.0000 - 1ff.7fff.ffff PCI A memory space
|
||||
* 1ff.8000.0000 - 1ff.ffff.ffff PCI B memory space
|
||||
*
|
||||
* NB: config and I/O space can use 1-4 byte accesses, not 8 byte
|
||||
* NB: Config and I/O space can use 1-4 byte accesses, not 8 byte
|
||||
* accesses. Memory space can use any sized accesses.
|
||||
*
|
||||
* Note that the SUNW,sabre/SUNW,simba combinations found on the
|
||||
|
@ -36,18 +36,29 @@
|
||||
* per pair of psychos.
|
||||
*/
|
||||
struct psycho_softc {
|
||||
struct bus_dma_methods *sc_dma_methods;
|
||||
/*
|
||||
* This is here so that we can hook up the common bus interface
|
||||
* methods in ofw_pci.c directly.
|
||||
*/
|
||||
struct ofw_pci_softc sc_ops;
|
||||
|
||||
device_t sc_dev;
|
||||
struct iommu_state *sc_is;
|
||||
struct bus_dma_methods *sc_dma_methods;
|
||||
|
||||
struct mtx *sc_mtx;
|
||||
|
||||
/* Interrupt Group Number for this device */
|
||||
uint32_t sc_ign;
|
||||
struct resource *sc_mem_res;
|
||||
struct resource *sc_irq_res[PSYCHO_NINTR];
|
||||
void *sc_ihand[PSYCHO_NINTR];
|
||||
|
||||
uint8_t sc_pci_hpbcfg[16];
|
||||
|
||||
SLIST_ENTRY(psycho_softc) sc_link;
|
||||
|
||||
device_t sc_dev;
|
||||
|
||||
bus_addr_t sc_pcictl;
|
||||
|
||||
phandle_t sc_node; /* Firmware node */
|
||||
u_int sc_mode;
|
||||
#define PSYCHO_MODE_SABRE 0
|
||||
#define PSYCHO_MODE_PSYCHO 1
|
||||
@ -55,30 +66,8 @@ struct psycho_softc {
|
||||
/* Bus A or B of a psycho pair? */
|
||||
u_int sc_half;
|
||||
|
||||
struct iommu_state *sc_is;
|
||||
|
||||
struct resource *sc_mem_res;
|
||||
struct resource *sc_irq_res[PSYCHO_NINTR];
|
||||
void *sc_ihand[PSYCHO_NINTR];
|
||||
|
||||
struct ofw_bus_iinfo sc_pci_iinfo;
|
||||
|
||||
/* Tags for PCI access */
|
||||
bus_space_tag_t sc_pci_cfgt;
|
||||
bus_space_tag_t sc_pci_iot;
|
||||
bus_dma_tag_t sc_pci_dmat;
|
||||
|
||||
bus_space_handle_t sc_pci_bh[PSYCHO_NRANGE];
|
||||
|
||||
struct rman sc_pci_mem_rman;
|
||||
struct rman sc_pci_io_rman;
|
||||
|
||||
uint8_t sc_pci_secbus;
|
||||
uint8_t sc_pci_subbus;
|
||||
|
||||
uint8_t sc_pci_hpbcfg[16];
|
||||
|
||||
SLIST_ENTRY(psycho_softc) sc_link;
|
||||
/* Interrupt Group Number for this device */
|
||||
uint32_t sc_ign;
|
||||
};
|
||||
|
||||
#endif /* !_SPARC64_PCI_PSYCHOVAR_H_ */
|
||||
|
@ -57,13 +57,11 @@ __FBSDID("$FreeBSD$");
|
||||
#include <sys/timetc.h>
|
||||
|
||||
#include <dev/ofw/ofw_bus.h>
|
||||
#include <dev/ofw/ofw_pci.h>
|
||||
#include <dev/ofw/openfirm.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/bus_common.h>
|
||||
#include <machine/bus_private.h>
|
||||
#include <machine/fsr.h>
|
||||
#include <machine/iommureg.h>
|
||||
#include <machine/iommuvar.h>
|
||||
#include <machine/resource.h>
|
||||
@ -108,17 +106,12 @@ static void schizo_iommu_init(struct schizo_softc *, int, uint32_t);
|
||||
*/
|
||||
static device_probe_t schizo_probe;
|
||||
static device_attach_t schizo_attach;
|
||||
static bus_read_ivar_t schizo_read_ivar;
|
||||
static bus_setup_intr_t schizo_setup_intr;
|
||||
static bus_alloc_resource_t schizo_alloc_resource;
|
||||
static bus_activate_resource_t schizo_activate_resource;
|
||||
static bus_adjust_resource_t schizo_adjust_resource;
|
||||
static bus_get_dma_tag_t schizo_get_dma_tag;
|
||||
static pcib_maxslots_t schizo_maxslots;
|
||||
static pcib_read_config_t schizo_read_config;
|
||||
static pcib_write_config_t schizo_write_config;
|
||||
static pcib_route_interrupt_t schizo_route_interrupt;
|
||||
static ofw_bus_get_node_t schizo_get_node;
|
||||
static ofw_pci_setup_device_t schizo_setup_device;
|
||||
|
||||
static device_method_t schizo_methods[] = {
|
||||
@ -130,15 +123,15 @@ static device_method_t schizo_methods[] = {
|
||||
DEVMETHOD(device_resume, bus_generic_resume),
|
||||
|
||||
/* Bus interface */
|
||||
DEVMETHOD(bus_read_ivar, schizo_read_ivar),
|
||||
DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar),
|
||||
DEVMETHOD(bus_setup_intr, schizo_setup_intr),
|
||||
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
||||
DEVMETHOD(bus_alloc_resource, schizo_alloc_resource),
|
||||
DEVMETHOD(bus_activate_resource, schizo_activate_resource),
|
||||
DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource),
|
||||
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
||||
DEVMETHOD(bus_adjust_resource, schizo_adjust_resource),
|
||||
DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource),
|
||||
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
||||
DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag),
|
||||
DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag),
|
||||
|
||||
/* pcib interface */
|
||||
DEVMETHOD(pcib_maxslots, schizo_maxslots),
|
||||
@ -147,7 +140,7 @@ static device_method_t schizo_methods[] = {
|
||||
DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt),
|
||||
|
||||
/* ofw_bus interface */
|
||||
DEVMETHOD(ofw_bus_get_node, schizo_get_node),
|
||||
DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node),
|
||||
|
||||
/* ofw_pci interface */
|
||||
DEVMETHOD(ofw_pci_setup_device, schizo_setup_device),
|
||||
@ -270,10 +263,10 @@ schizo_probe(device_t dev)
|
||||
static int
|
||||
schizo_attach(device_t dev)
|
||||
{
|
||||
struct ofw_pci_ranges *range;
|
||||
const struct schizo_desc *desc;
|
||||
struct schizo_softc *asc, *sc, *osc;
|
||||
struct timecounter *tc;
|
||||
bus_dma_tag_t dmat;
|
||||
uint64_t ino_bitmap, reg;
|
||||
phandle_t node;
|
||||
uint32_t prop, prop_array[2];
|
||||
@ -285,7 +278,6 @@ schizo_attach(device_t dev)
|
||||
mode = desc->sd_mode;
|
||||
|
||||
sc->sc_dev = dev;
|
||||
sc->sc_node = node;
|
||||
sc->sc_mode = mode;
|
||||
sc->sc_flags = 0;
|
||||
|
||||
@ -347,6 +339,7 @@ schizo_attach(device_t dev)
|
||||
panic("%s: mutex not initialized", __func__);
|
||||
sc->sc_mtx = osc->sc_mtx;
|
||||
}
|
||||
SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link);
|
||||
|
||||
if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1)
|
||||
panic("%s: could not determine IGN", __func__);
|
||||
@ -542,80 +535,23 @@ schizo_attach(device_t dev)
|
||||
|
||||
#undef TSBCASE
|
||||
|
||||
/* Initialize memory and I/O rmans. */
|
||||
sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
|
||||
sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports";
|
||||
if (rman_init(&sc->sc_pci_io_rman) != 0 ||
|
||||
rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0)
|
||||
panic("%s: failed to set up I/O rman", __func__);
|
||||
sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
|
||||
sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory";
|
||||
if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
|
||||
rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0)
|
||||
panic("%s: failed to set up memory rman", __func__);
|
||||
|
||||
i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
|
||||
/*
|
||||
* Make sure that the expected ranges are present. The
|
||||
* OFW_PCI_CS_MEM64 one is not currently used though.
|
||||
*/
|
||||
if (i != STX_NRANGE)
|
||||
panic("%s: unsupported number of ranges", __func__);
|
||||
/*
|
||||
* Find the addresses of the various bus spaces.
|
||||
* There should not be multiple ones of one kind.
|
||||
* The physical start addresses of the ranges are the configuration,
|
||||
* memory and I/O handles.
|
||||
*/
|
||||
for (i = 0; i < STX_NRANGE; i++) {
|
||||
j = OFW_PCI_RANGE_CS(&range[i]);
|
||||
if (sc->sc_pci_bh[j] != 0)
|
||||
panic("%s: duplicate range for space %d",
|
||||
__func__, j);
|
||||
sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
|
||||
}
|
||||
free(range, M_OFWPROP);
|
||||
|
||||
/* Register the softc, this is needed for paired Schizos. */
|
||||
SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link);
|
||||
|
||||
/* Allocate our tags. */
|
||||
sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, PCI_IO_BUS_SPACE);
|
||||
if (sc->sc_pci_iot == NULL)
|
||||
panic("%s: could not allocate PCI I/O tag", __func__);
|
||||
sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, PCI_CONFIG_BUS_SPACE);
|
||||
if (sc->sc_pci_cfgt == NULL)
|
||||
panic("%s: could not allocate PCI configuration space tag",
|
||||
__func__);
|
||||
/* Create our DMA tag. */
|
||||
if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
|
||||
sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL,
|
||||
sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL,
|
||||
&sc->sc_pci_dmat) != 0)
|
||||
&dmat) != 0)
|
||||
panic("%s: could not create PCI DMA tag", __func__);
|
||||
/* Customize the tag. */
|
||||
sc->sc_pci_dmat->dt_cookie = &sc->sc_is;
|
||||
sc->sc_pci_dmat->dt_mt = &sc->sc_dma_methods;
|
||||
dmat->dt_cookie = &sc->sc_is;
|
||||
dmat->dt_mt = &sc->sc_dma_methods;
|
||||
|
||||
/*
|
||||
* Get the bus range from the firmware.
|
||||
* NB: Tomatillos don't support PCI bus reenumeration.
|
||||
*/
|
||||
i = OF_getprop(node, "bus-range", (void *)prop_array,
|
||||
sizeof(prop_array));
|
||||
if (i == -1)
|
||||
panic("%s: could not get bus-range", __func__);
|
||||
if (i != sizeof(prop_array))
|
||||
panic("%s: broken bus-range (%d)", __func__, i);
|
||||
sc->sc_pci_secbus = prop_array[0];
|
||||
sc->sc_pci_subbus = prop_array[1];
|
||||
if (bootverbose)
|
||||
device_printf(dev, "bus range %u to %u; PCI bus %d\n",
|
||||
sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
|
||||
if (ofw_pci_attach_common(dev, dmat, STX_IO_SIZE, STX_MEM_SIZE) != 0)
|
||||
panic("%s: ofw_pci_attach_common() failed", __func__);
|
||||
|
||||
/* Clear any pending PCI error bits. */
|
||||
PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
|
||||
PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
|
||||
STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2);
|
||||
PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE,
|
||||
STX_CS_FUNC, PCIR_STATUS, PCIB_READ_CONFIG(dev,
|
||||
sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS,
|
||||
2), 2);
|
||||
SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL));
|
||||
SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR));
|
||||
|
||||
@ -743,10 +679,8 @@ schizo_attach(device_t dev)
|
||||
* Set the latency timer register as this isn't always done by the
|
||||
* firmware.
|
||||
*/
|
||||
PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
|
||||
PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
|
||||
|
||||
ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
|
||||
PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE,
|
||||
STX_CS_FUNC, PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
|
||||
|
||||
#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \
|
||||
SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \
|
||||
@ -870,7 +804,7 @@ schizo_pci_bus(void *arg)
|
||||
xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT);
|
||||
else
|
||||
xstat = 0;
|
||||
status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus,
|
||||
status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus,
|
||||
STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
|
||||
|
||||
/*
|
||||
@ -911,7 +845,7 @@ schizo_pci_bus(void *arg)
|
||||
(unsigned long long)iommu, (unsigned long long)xstat, status);
|
||||
|
||||
/* Clear the error bits that we caught. */
|
||||
PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE,
|
||||
PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE,
|
||||
STX_CS_FUNC, PCIR_STATUS, status, 2);
|
||||
SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
|
||||
SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
|
||||
@ -1032,121 +966,40 @@ schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
|
||||
int width)
|
||||
{
|
||||
struct schizo_softc *sc;
|
||||
bus_space_handle_t bh;
|
||||
u_long offset = 0;
|
||||
uint32_t r, wrd;
|
||||
int i;
|
||||
uint16_t shrt;
|
||||
uint8_t byte;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
|
||||
slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
|
||||
return (-1);
|
||||
|
||||
/*
|
||||
* The Schizo bridges contain a dupe of their header at 0x80.
|
||||
*/
|
||||
if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus &&
|
||||
slot == STX_CS_DEVICE && func == STX_CS_FUNC &&
|
||||
reg + width > 0x80)
|
||||
if (sc->sc_mode == SCHIZO_MODE_SCZ &&
|
||||
bus == sc->sc_ops.sc_pci_secbus && slot == STX_CS_DEVICE &&
|
||||
func == STX_CS_FUNC && reg + width > 0x80)
|
||||
return (0);
|
||||
|
||||
offset = STX_CONF_OFF(bus, slot, func, reg);
|
||||
bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
|
||||
switch (width) {
|
||||
case 1:
|
||||
i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
|
||||
r = byte;
|
||||
break;
|
||||
case 2:
|
||||
i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
|
||||
r = shrt;
|
||||
break;
|
||||
case 4:
|
||||
i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
|
||||
r = wrd;
|
||||
break;
|
||||
default:
|
||||
panic("%s: bad width", __func__);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
if (i) {
|
||||
#ifdef SCHIZO_DEBUG
|
||||
printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
|
||||
__func__, bus, slot, func, reg);
|
||||
#endif
|
||||
r = -1;
|
||||
}
|
||||
return (r);
|
||||
return (ofw_pci_read_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus,
|
||||
slot, func, reg), bus, slot, func, reg, width));
|
||||
}
|
||||
|
||||
static void
|
||||
schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func,
|
||||
u_int reg, uint32_t val, int width)
|
||||
{
|
||||
struct schizo_softc *sc;
|
||||
bus_space_handle_t bh;
|
||||
u_long offset = 0;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
|
||||
slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
|
||||
return;
|
||||
|
||||
offset = STX_CONF_OFF(bus, slot, func, reg);
|
||||
bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
|
||||
switch (width) {
|
||||
case 1:
|
||||
bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
|
||||
break;
|
||||
case 2:
|
||||
bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
|
||||
break;
|
||||
case 4:
|
||||
bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
|
||||
break;
|
||||
default:
|
||||
panic("%s: bad width", __func__);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
ofw_pci_write_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus, slot,
|
||||
func, reg), bus, slot, func, reg, val, width);
|
||||
}
|
||||
|
||||
static int
|
||||
schizo_route_interrupt(device_t bridge, device_t dev, int pin)
|
||||
{
|
||||
struct schizo_softc *sc;
|
||||
struct ofw_pci_register reg;
|
||||
ofw_pci_intr_t pintr, mintr;
|
||||
ofw_pci_intr_t mintr;
|
||||
|
||||
sc = device_get_softc(bridge);
|
||||
pintr = pin;
|
||||
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
|
||||
®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
|
||||
NULL))
|
||||
return (mintr);
|
||||
|
||||
device_printf(bridge, "could not route pin %d for device %d.%d\n",
|
||||
pin, pci_get_slot(dev), pci_get_function(dev));
|
||||
return (PCI_INVALID_IRQ);
|
||||
}
|
||||
|
||||
static int
|
||||
schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
|
||||
{
|
||||
struct schizo_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
switch (which) {
|
||||
case PCIB_IVAR_DOMAIN:
|
||||
*result = device_get_unit(dev);
|
||||
return (0);
|
||||
case PCIB_IVAR_BUS:
|
||||
*result = sc->sc_pci_secbus;
|
||||
return (0);
|
||||
}
|
||||
return (ENOENT);
|
||||
mintr = ofw_pci_route_interrupt_common(bridge, dev, pin);
|
||||
if (!PCI_INTERRUPT_VALID(mintr))
|
||||
device_printf(bridge,
|
||||
"could not route pin %d for device %d.%d\n",
|
||||
pin, pci_get_slot(dev), pci_get_function(dev));
|
||||
return (mintr);
|
||||
}
|
||||
|
||||
static void
|
||||
@ -1214,11 +1067,10 @@ schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
|
||||
static void
|
||||
ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
|
||||
{
|
||||
static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE);
|
||||
struct timeval cur, end;
|
||||
struct schizo_iommu_state *sis = dt->dt_cookie;
|
||||
struct schizo_softc *sc = sis->sis_sc;
|
||||
register_t reg, s;
|
||||
uint64_t reg;
|
||||
|
||||
if ((map->dm_flags & DMF_STREAMED) != 0) {
|
||||
iommu_dma_methods.dm_dmamap_sync(dt, map, op);
|
||||
@ -1246,14 +1098,7 @@ ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
|
||||
if (sc->sc_mode == SCHIZO_MODE_XMS)
|
||||
mtx_unlock_spin(&sc->sc_sync_mtx);
|
||||
else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) {
|
||||
s = intr_disable();
|
||||
reg = rd(fprs);
|
||||
wr(fprs, reg | FPRS_FEF, 0);
|
||||
__asm __volatile("stda %%f0, [%0] %1"
|
||||
: : "r" (buf), "n" (ASI_BLK_COMMIT_S));
|
||||
membar(Sync);
|
||||
wr(fprs, reg, 0);
|
||||
intr_restore(s);
|
||||
ofw_pci_dmamap_sync_stst_order_common();
|
||||
return;
|
||||
}
|
||||
}
|
||||
@ -1354,120 +1199,13 @@ schizo_alloc_resource(device_t bus, device_t child, int type, int *rid,
|
||||
u_long start, u_long end, u_long count, u_int flags)
|
||||
{
|
||||
struct schizo_softc *sc;
|
||||
struct resource *rv;
|
||||
struct rman *rm;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
/*
|
||||
* XXX: Don't accept blank ranges for now, only single
|
||||
* interrupts. The other case should not happen with
|
||||
* the MI PCI code...
|
||||
* XXX: This may return a resource that is out of the
|
||||
* range that was specified. Is this correct...?
|
||||
*/
|
||||
if (start != end)
|
||||
panic("%s: XXX: interrupt range", __func__);
|
||||
if (type == SYS_RES_IRQ) {
|
||||
sc = device_get_softc(bus);
|
||||
start = end = INTMAP_VEC(sc->sc_ign, end);
|
||||
return (bus_generic_alloc_resource(bus, child, type, rid,
|
||||
start, end, count, flags));
|
||||
case SYS_RES_MEMORY:
|
||||
rm = &sc->sc_pci_mem_rman;
|
||||
break;
|
||||
case SYS_RES_IOPORT:
|
||||
rm = &sc->sc_pci_io_rman;
|
||||
break;
|
||||
default:
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
|
||||
child);
|
||||
if (rv == NULL)
|
||||
return (NULL);
|
||||
rman_set_rid(rv, *rid);
|
||||
|
||||
if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type,
|
||||
*rid, rv) != 0) {
|
||||
rman_release_resource(rv);
|
||||
return (NULL);
|
||||
}
|
||||
return (rv);
|
||||
}
|
||||
|
||||
static int
|
||||
schizo_activate_resource(device_t bus, device_t child, int type, int rid,
|
||||
struct resource *r)
|
||||
{
|
||||
struct schizo_softc *sc;
|
||||
struct bus_space_tag *tag;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
return (bus_generic_activate_resource(bus, child, type, rid,
|
||||
r));
|
||||
case SYS_RES_MEMORY:
|
||||
tag = sparc64_alloc_bus_tag(r, PCI_MEMORY_BUS_SPACE);
|
||||
if (tag == NULL)
|
||||
return (ENOMEM);
|
||||
rman_set_bustag(r, tag);
|
||||
rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] +
|
||||
rman_get_start(r));
|
||||
break;
|
||||
case SYS_RES_IOPORT:
|
||||
rman_set_bustag(r, sc->sc_pci_iot);
|
||||
rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] +
|
||||
rman_get_start(r));
|
||||
break;
|
||||
}
|
||||
return (rman_activate_resource(r));
|
||||
}
|
||||
|
||||
static int
|
||||
schizo_adjust_resource(device_t bus, device_t child, int type,
|
||||
struct resource *r, u_long start, u_long end)
|
||||
{
|
||||
struct schizo_softc *sc;
|
||||
struct rman *rm;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
return (bus_generic_adjust_resource(bus, child, type, r,
|
||||
start, end));
|
||||
case SYS_RES_MEMORY:
|
||||
rm = &sc->sc_pci_mem_rman;
|
||||
break;
|
||||
case SYS_RES_IOPORT:
|
||||
rm = &sc->sc_pci_io_rman;
|
||||
break;
|
||||
default:
|
||||
return (EINVAL);
|
||||
}
|
||||
if (rman_is_region_manager(r, rm) == 0)
|
||||
return (EINVAL);
|
||||
return (rman_adjust_resource(r, start, end));
|
||||
}
|
||||
|
||||
static bus_dma_tag_t
|
||||
schizo_get_dma_tag(device_t bus, device_t child __unused)
|
||||
{
|
||||
struct schizo_softc *sc;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
return (sc->sc_pci_dmat);
|
||||
}
|
||||
|
||||
static phandle_t
|
||||
schizo_get_node(device_t bus, device_t child __unused)
|
||||
{
|
||||
struct schizo_softc *sc;
|
||||
|
||||
sc = device_get_softc(bus);
|
||||
/* We only have one child, the PCI bus, which needs our own node. */
|
||||
return (sc->sc_node);
|
||||
return (ofw_pci_alloc_resource(bus, child, type, rid, start, end,
|
||||
count, flags));
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -32,7 +32,6 @@
|
||||
#define _SPARC64_PCI_SCHIZOREG_H_
|
||||
|
||||
#define STX_NINTR 5 /* 4 via OFW + 1 CDMA */
|
||||
#define STX_NRANGE 4
|
||||
#define SCZ_NREG 3
|
||||
#define TOM_NREG 4
|
||||
|
||||
@ -279,7 +278,7 @@
|
||||
|
||||
/*
|
||||
* Safari/JBus performance control register
|
||||
* NB: for Tomatillo only events 0x00 through 0x08 are documented as
|
||||
* NB: For Tomatillo only events 0x00 through 0x08 are documented as
|
||||
* implemented.
|
||||
*/
|
||||
#define SCZ_CTRL_PERF_ZDATA_OUT 0x0000000000000016ULL
|
||||
@ -345,7 +344,7 @@
|
||||
|
||||
/* Non-Standard registers in the configration space */
|
||||
/*
|
||||
* NB: for Tomatillo the secondary and subordinate bus number registers
|
||||
* NB: For Tomatillo the secondary and subordinate bus number registers
|
||||
* apparently are read-only although documented otherwise; writing to
|
||||
* them just triggers a PCI bus error interrupt or has no effect at best.
|
||||
*/
|
||||
|
@ -39,16 +39,27 @@ struct schizo_iommu_state {
|
||||
};
|
||||
|
||||
struct schizo_softc {
|
||||
struct bus_dma_methods sc_dma_methods;
|
||||
/*
|
||||
* This is here so that we can hook up the common bus interface
|
||||
* methods in ofw_pci.c directly.
|
||||
*/
|
||||
struct ofw_pci_softc sc_ops;
|
||||
|
||||
device_t sc_dev;
|
||||
struct schizo_iommu_state sc_is;
|
||||
struct bus_dma_methods sc_dma_methods;
|
||||
|
||||
struct mtx sc_sync_mtx;
|
||||
uint64_t sc_sync_val;
|
||||
|
||||
struct mtx *sc_mtx;
|
||||
|
||||
phandle_t sc_node;
|
||||
struct resource *sc_mem_res[TOM_NREG];
|
||||
struct resource *sc_irq_res[STX_NINTR];
|
||||
void *sc_ihand[STX_NINTR];
|
||||
|
||||
SLIST_ENTRY(schizo_softc) sc_link;
|
||||
|
||||
device_t sc_dev;
|
||||
|
||||
u_int sc_mode;
|
||||
#define SCHIZO_MODE_SCZ 0
|
||||
@ -72,28 +83,8 @@ struct schizo_softc {
|
||||
uint32_t sc_ver;
|
||||
uint32_t sc_mrev;
|
||||
|
||||
struct resource *sc_mem_res[TOM_NREG];
|
||||
struct resource *sc_irq_res[STX_NINTR];
|
||||
void *sc_ihand[STX_NINTR];
|
||||
|
||||
struct schizo_iommu_state sc_is;
|
||||
|
||||
struct rman sc_pci_mem_rman;
|
||||
struct rman sc_pci_io_rman;
|
||||
bus_space_handle_t sc_pci_bh[STX_NRANGE];
|
||||
bus_space_tag_t sc_pci_cfgt;
|
||||
bus_space_tag_t sc_pci_iot;
|
||||
bus_dma_tag_t sc_pci_dmat;
|
||||
|
||||
uint32_t sc_stats_dma_ce;
|
||||
uint32_t sc_stats_pci_non_fatal;
|
||||
|
||||
uint8_t sc_pci_secbus;
|
||||
uint8_t sc_pci_subbus;
|
||||
|
||||
struct ofw_bus_iinfo sc_pci_iinfo;
|
||||
|
||||
SLIST_ENTRY(schizo_softc) sc_link;
|
||||
};
|
||||
|
||||
#endif /* !_SPARC64_PCI_SCHIZOVAR_H_ */
|
||||
|
Loading…
Reference in New Issue
Block a user