Adjust the code to probe for the PCI config mechanism to use.
- On amd64, just assume type #1 is always used. PCI 2.0 mandated deprecated type #2 and required type #1 for all future bridges which was well before amd64 existed. - For i386, ignore whatever value was in 0xcf8 before testing for type #1 and instead rely on the other tests to determine if type #1 works. Some newer machines leave garbage in 0xcf8 during boot and as a result the kernel doesn't find PCI at all (which greatly confuses ACPI which expects PCI to exist when PCI busses are in the namespace). MFC after: 3 days Discussed with: scottl
This commit is contained in:
John Baldwin
parent
b468fe2bce
commit
98bbce55fa
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=174050
@ -37,11 +37,6 @@
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#define CONF1_ENABLE_MSK1 0x80000001ul
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#define CONF1_ENABLE_RES1 0x80000000ul
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#define CONF2_ENABLE_PORT 0x0cf8
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#define CONF2_FORWARD_PORT 0x0cfa
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#define CONF2_ENABLE_CHK 0x0e
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#define CONF2_ENABLE_RES 0x0e
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int pci_cfgregopen(void);
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u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes);
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void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes);
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@ -38,12 +38,8 @@ __FBSDID("$FreeBSD$");
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#include <dev/pci/pcireg.h>
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#include <machine/pci_cfgreg.h>
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static int cfgmech;
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static int devmax;
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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static int pcireg_cfgopen(void);
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static struct mtx pcicfg_mtx;
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@ -57,8 +53,6 @@ pci_cfgregopen(void)
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if (opened)
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return (1);
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if (pcireg_cfgopen() == 0)
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return (0);
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mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
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opened = 1;
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return (1);
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@ -109,26 +103,12 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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{
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int dataport = 0;
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if (bus <= PCI_BUSMAX
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&& slot < devmax
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&& func <= PCI_FUNCMAX
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&& reg <= PCI_REGMAX
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&& bytes != 3
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&& (unsigned) bytes <= 4
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&& (reg & (bytes - 1)) == 0) {
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, (1 << 31)
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| (bus << 16) | (slot << 11)
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| (func << 8) | (reg & ~0x03));
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dataport = CONF1_DATA_PORT + (reg & 0x03);
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break;
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case 2:
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outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
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outb(CONF2_FORWARD_PORT, bus);
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dataport = 0xc000 | (slot << 8) | reg;
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break;
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}
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if (bus <= PCI_BUSMAX && slot < 32 && func <= PCI_FUNCMAX &&
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reg <= PCI_REGMAX && bytes != 3 && (unsigned) bytes <= 4 &&
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(reg & (bytes - 1)) == 0) {
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outl(CONF1_ADDR_PORT, (1 << 31) | (bus << 16) | (slot << 11)
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| (func << 8) | (reg & ~0x03));
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dataport = CONF1_DATA_PORT + (reg & 0x03);
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}
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return (dataport);
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}
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@ -137,19 +117,11 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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static void
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pci_cfgdisable(void)
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{
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switch (cfgmech) {
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case 1:
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/*
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* Do nothing for the config mechanism 1 case.
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* Writing a 0 to the address port can apparently
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* confuse some bridges and cause spurious
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* access failures.
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*/
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break;
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case 2:
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outb(CONF2_ENABLE_PORT, 0);
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break;
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}
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/*
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* Do nothing. Writing a 0 to the address port can apparently
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* confuse some bridges and cause spurious access failures.
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*/
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}
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static int
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@ -201,131 +173,3 @@ pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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}
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mtx_unlock_spin(&pcicfg_mtx);
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}
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/* check whether the configuration mechanism has been correctly identified */
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static int
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pci_cfgcheck(int maxdev)
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{
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uint32_t id, class;
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uint8_t header;
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uint8_t device;
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int port;
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if (bootverbose)
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printf("pci_cfgcheck:\tdevice ");
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for (device = 0; device < maxdev; device++) {
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if (bootverbose)
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printf("%d ", device);
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port = pci_cfgenable(0, device, 0, 0, 4);
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id = inl(port);
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if (id == 0 || id == 0xffffffff)
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continue;
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port = pci_cfgenable(0, device, 0, 8, 4);
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class = inl(port) >> 8;
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if (bootverbose)
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printf("[class=%06x] ", class);
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if (class == 0 || (class & 0xf870ff) != 0)
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continue;
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port = pci_cfgenable(0, device, 0, 14, 1);
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header = inb(port);
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if (bootverbose)
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printf("[hdr=%02x] ", header);
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if ((header & 0x7e) != 0)
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continue;
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if (bootverbose)
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printf("is there (id=%08x)\n", id);
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pci_cfgdisable();
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return (1);
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}
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if (bootverbose)
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printf("-- nothing found\n");
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pci_cfgdisable();
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return (0);
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}
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static int
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pcireg_cfgopen(void)
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{
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uint32_t mode1res, oldval1;
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uint8_t mode2res, oldval2;
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oldval1 = inl(CONF1_ADDR_PORT);
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if (bootverbose) {
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printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
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oldval1);
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}
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if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
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cfgmech = 1;
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devmax = 32;
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
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DELAY(1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK);
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if (mode1res) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK1);
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if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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}
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oldval2 = inb(CONF2_ENABLE_PORT);
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if (bootverbose) {
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printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
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oldval2);
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}
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if ((oldval2 & 0xf0) == 0) {
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cfgmech = 2;
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devmax = 16;
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outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
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mode2res = inb(CONF2_ENABLE_PORT);
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outb(CONF2_ENABLE_PORT, oldval2);
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if (bootverbose)
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printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
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mode2res, CONF2_ENABLE_CHK);
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if (mode2res == CONF2_ENABLE_RES) {
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if (bootverbose)
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printf("pci_open(2a):\tnow trying mechanism 2\n");
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if (pci_cfgcheck(16))
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return (cfgmech);
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}
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}
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cfgmech = 0;
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devmax = 0;
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return (cfgmech);
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}
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@ -403,6 +403,7 @@ pcireg_cfgopen(void)
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uint32_t mode1res, oldval1;
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uint8_t mode2res, oldval2;
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/* Check for type #1 first. */
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oldval1 = inl(CONF1_ADDR_PORT);
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if (bootverbose) {
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@ -410,39 +411,37 @@ pcireg_cfgopen(void)
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oldval1);
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}
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if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
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cfgmech = CFGMECH_1;
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devmax = 32;
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cfgmech = CFGMECH_1;
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devmax = 32;
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
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DELAY(1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
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DELAY(1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
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CONF1_ENABLE_CHK);
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if (bootverbose)
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printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK);
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if (mode1res) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK1);
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if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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if (mode1res) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
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CONF1_ENABLE_CHK1);
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if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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/* Type #1 didn't work, so try type #2. */
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oldval2 = inb(CONF2_ENABLE_PORT);
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if (bootverbose) {
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@ -472,6 +471,7 @@ pcireg_cfgopen(void)
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}
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}
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/* Nothing worked, so punt. */
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cfgmech = CFGMECH_NONE;
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devmax = 0;
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return (cfgmech);
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