arm64: allwinner: Add r_intc driver
The r intc interrupt controller seems to do a lot of things : - It can handle the NMI interrupt - It have local interrupts for some device that also can be muxed with GIC - It can serve as an forwarder for the GIC It's mostly used for deepsleep/wakeup if I understood correctly and we do not support this on arm64. For now just forward everything to the GIC so interrupts works again for device which now have this interrupts controller set since dts v5.12 Sponsored by: Diablotin Systems
This commit is contained in:
Emmanuel Vadot
parent
1f7d11e636
commit
993e8236c3
299
sys/arm/allwinner/aw_r_intc.c
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299
sys/arm/allwinner/aw_r_intc.c
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@ -0,0 +1,299 @@
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/*-
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* Copyright (c) 2021 Emmanuel Vadot <manu@freebsd.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/intr.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "pic_if.h"
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struct aw_r_intc_gicp_softc {
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device_t dev;
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device_t parent;
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struct resource *res;
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struct intr_map_data_fdt *parent_map_data;
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};
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static struct ofw_compat_data compat_data[] = {
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{"allwinner,sun6i-a31-r-intc", 1},
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{NULL, 0}
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};
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static int
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aw_r_intc_gicp_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Allwinner R INTC");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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aw_r_intc_gicp_attach(device_t dev)
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{
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struct aw_r_intc_gicp_softc *sc;
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phandle_t node, xref, intr_parent;
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sc = device_get_softc(dev);
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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/* Look for our parent */
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if ((intr_parent = ofw_bus_find_iparent(node)) == 0) {
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device_printf(dev,
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"Cannot find our parent interrupt controller\n");
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return (ENXIO);
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}
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if ((sc->parent = OF_device_from_xref(intr_parent)) == NULL) {
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device_printf(dev,
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"cannot find parent interrupt controller device\n");
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return (ENXIO);
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}
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/* Register ourself as a interrupt controller */
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xref = OF_xref_from_node(node);
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if (intr_pic_register(dev, xref) == NULL) {
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device_printf(dev, "Cannot register GICP\n");
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return (ENXIO);
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}
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/* Allocate GIC compatible mapping */
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sc->parent_map_data = (struct intr_map_data_fdt *)intr_alloc_map_data(
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INTR_MAP_DATA_FDT, sizeof(struct intr_map_data_fdt) +
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+ 3 * sizeof(phandle_t), M_WAITOK | M_ZERO);
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/* Register ourself to device can find us */
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OF_device_register_xref(xref, dev);
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return (0);
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}
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static int
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aw_r_intc_gicp_detach(device_t dev)
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{
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return (EBUSY);
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}
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static struct intr_map_data *
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aw_r_intc_gicp_convert_map_data(struct aw_r_intc_gicp_softc *sc,
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struct intr_map_data *data)
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{
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struct intr_map_data_fdt *daf;
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daf = (struct intr_map_data_fdt *)data;
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/* We only support GIC forward for now */
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if (daf->ncells != 3)
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return (NULL);
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/* Check if this is a GIC_SPI type */
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if (daf->cells[0] != 0)
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return (NULL);
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sc->parent_map_data->ncells = 3;
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sc->parent_map_data->cells[0] = 0;
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sc->parent_map_data->cells[1] = daf->cells[1];
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sc->parent_map_data->cells[2] = daf->cells[2];
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return ((struct intr_map_data *)sc->parent_map_data);
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}
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static int
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aw_r_intc_gicp_activate_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct aw_r_intc_gicp_softc *sc;
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sc = device_get_softc(dev);
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data = aw_r_intc_gicp_convert_map_data(sc, data);
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if (data == NULL)
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return (EINVAL);
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return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data));
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}
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static void
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aw_r_intc_gicp_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct aw_r_intc_gicp_softc *sc;
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sc = device_get_softc(dev);
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PIC_ENABLE_INTR(sc->parent, isrc);
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}
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static void
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aw_r_intc_gicp_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct aw_r_intc_gicp_softc *sc;
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sc = device_get_softc(dev);
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PIC_DISABLE_INTR(sc->parent, isrc);
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}
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static int
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aw_r_intc_gicp_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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struct aw_r_intc_gicp_softc *sc;
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int ret;
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sc = device_get_softc(dev);
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if (data->type != INTR_MAP_DATA_FDT)
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return (ENOTSUP);
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data = aw_r_intc_gicp_convert_map_data(sc, data);
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if (data == NULL)
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return (EINVAL);
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ret = PIC_MAP_INTR(sc->parent, data, isrcp);
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(*isrcp)->isrc_dev = sc->dev;
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return(ret);
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}
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static int
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aw_r_intc_gicp_deactivate_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct aw_r_intc_gicp_softc *sc;
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sc = device_get_softc(dev);
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data = aw_r_intc_gicp_convert_map_data(sc, data);
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if (data == NULL)
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return (EINVAL);
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return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data));
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}
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static int
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aw_r_intc_gicp_setup_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct aw_r_intc_gicp_softc *sc;
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sc = device_get_softc(dev);
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data = aw_r_intc_gicp_convert_map_data(sc, data);
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if (data == NULL)
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return (EINVAL);
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return (PIC_SETUP_INTR(sc->parent, isrc, res, data));
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}
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static int
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aw_r_intc_gicp_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct aw_r_intc_gicp_softc *sc;
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sc = device_get_softc(dev);
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data = aw_r_intc_gicp_convert_map_data(sc, data);
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if (data == NULL)
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return (EINVAL);
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return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data));
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}
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static void
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aw_r_intc_gicp_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct aw_r_intc_gicp_softc *sc;
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sc = device_get_softc(dev);
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PIC_PRE_ITHREAD(sc->parent, isrc);
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}
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static void
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aw_r_intc_gicp_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct aw_r_intc_gicp_softc *sc;
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sc = device_get_softc(dev);
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PIC_POST_ITHREAD(sc->parent, isrc);
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}
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static void
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aw_r_intc_gicp_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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struct aw_r_intc_gicp_softc *sc;
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sc = device_get_softc(dev);
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PIC_POST_FILTER(sc->parent, isrc);
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}
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static device_method_t aw_r_intc_gicp_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, aw_r_intc_gicp_probe),
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DEVMETHOD(device_attach, aw_r_intc_gicp_attach),
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DEVMETHOD(device_detach, aw_r_intc_gicp_detach),
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/* Interrupt controller interface */
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DEVMETHOD(pic_activate_intr, aw_r_intc_gicp_activate_intr),
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DEVMETHOD(pic_disable_intr, aw_r_intc_gicp_disable_intr),
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DEVMETHOD(pic_enable_intr, aw_r_intc_gicp_enable_intr),
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DEVMETHOD(pic_map_intr, aw_r_intc_gicp_map_intr),
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DEVMETHOD(pic_deactivate_intr, aw_r_intc_gicp_deactivate_intr),
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DEVMETHOD(pic_setup_intr, aw_r_intc_gicp_setup_intr),
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DEVMETHOD(pic_teardown_intr, aw_r_intc_gicp_teardown_intr),
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DEVMETHOD(pic_post_filter, aw_r_intc_gicp_post_filter),
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DEVMETHOD(pic_post_ithread, aw_r_intc_gicp_post_ithread),
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DEVMETHOD(pic_pre_ithread, aw_r_intc_gicp_pre_ithread),
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DEVMETHOD_END
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};
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static devclass_t aw_r_intc_gicp_devclass;
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static driver_t aw_r_intc_gicp_driver = {
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"aw_r_intc_gicp",
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aw_r_intc_gicp_methods,
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sizeof(struct aw_r_intc_gicp_softc),
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};
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EARLY_DRIVER_MODULE(aw_r_intc_gicp, simplebus, aw_r_intc_gicp_driver,
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aw_r_intc_gicp_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
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@ -211,6 +211,7 @@ device aw_ccu # Allwinner clock controller
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# Interrupt controllers
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device aw_nmi # Allwinner NMI support
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device aw_r_intc # Allwinner RINTC support
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device mv_cp110_icu # Marvell CP110 ICU
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device mv_ap806_gicp # Marvell AP806 GICP
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device mv_ap806_sei # Marvell AP806 SEI
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@ -323,6 +323,7 @@ arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt
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arm/allwinner/aw_nmi.c optional aw_nmi fdt \
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compile-with "${NORMAL_C} -I$S/contrib/device-tree/include"
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arm/allwinner/aw_pwm.c optional aw_pwm fdt
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arm/allwinner/aw_r_intc.c optional aw_r_intc fdt
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arm/allwinner/aw_rsb.c optional aw_rsb fdt
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arm/allwinner/aw_rtc.c optional aw_rtc fdt
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arm/allwinner/aw_sid.c optional aw_sid nvmem fdt
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