libpmc: remove mips support
Bye bye! Reviewed by: imp, emaste Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D34083
This commit is contained in:
Mitchell Horne
parent
29998bf2ac
commit
99830f702d
@ -52,6 +52,10 @@
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# xargs -n1 | sort | uniq -d;
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# done
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# 20220128: mips pmc events removed
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OLD_FILES+=usr/share/man/man3/pmc.mips24k.3
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OLD_FILES+=usr/share/man/man3/pmc.octeon.3
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# 20220127: terasic_mtl.4 removed
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OLD_FILES+=usr/share/man/man4/terasic_mtl.4.gz
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@ -81,8 +81,6 @@ MAN+= pmc.ivybridge.3
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MAN+= pmc.ivybridgexeon.3
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MAN+= pmc.k7.3
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MAN+= pmc.k8.3
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MAN+= pmc.mips24k.3
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MAN+= pmc.octeon.3
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MAN+= pmc.sandybridge.3
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MAN+= pmc.sandybridgeuc.3
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MAN+= pmc.sandybridgexeon.3
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@ -66,10 +66,6 @@ static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
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static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
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struct pmc_op_pmcallocate *_pmc_config);
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#endif
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#if defined(__mips__)
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static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec,
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struct pmc_op_pmcallocate *_pmc_config);
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#endif /* __mips__ */
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static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
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struct pmc_op_pmcallocate *_pmc_config);
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@ -138,10 +134,6 @@ PMC_CLASSDEP_TABLE(iaf, IAF);
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PMC_CLASSDEP_TABLE(k8, K8);
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PMC_CLASSDEP_TABLE(armv7, ARMV7);
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PMC_CLASSDEP_TABLE(armv8, ARMV8);
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PMC_CLASSDEP_TABLE(beri, BERI);
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PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
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PMC_CLASSDEP_TABLE(mips74k, MIPS74K);
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PMC_CLASSDEP_TABLE(octeon, OCTEON);
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PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
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PMC_CLASSDEP_TABLE(ppc970, PPC970);
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PMC_CLASSDEP_TABLE(e500, E500);
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@ -209,12 +201,6 @@ PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64);
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PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64);
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PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64);
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#endif
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#if defined(__mips__)
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PMC_CLASS_TABLE_DESC(beri, BERI, beri, mips);
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PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips);
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PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips);
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PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips);
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#endif /* __mips__ */
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#if defined(__powerpc__)
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PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc);
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PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc);
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@ -780,64 +766,6 @@ arm64_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
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}
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#endif
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#if defined(__mips__)
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static struct pmc_event_alias beri_aliases[] = {
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EV_ALIAS("instructions", "INST"),
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EV_ALIAS(NULL, NULL)
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};
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static struct pmc_event_alias mips24k_aliases[] = {
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EV_ALIAS("instructions", "INSTR_EXECUTED"),
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EV_ALIAS("branches", "BRANCH_COMPLETED"),
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EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"),
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EV_ALIAS(NULL, NULL)
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};
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static struct pmc_event_alias mips74k_aliases[] = {
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EV_ALIAS("instructions", "INSTR_EXECUTED"),
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EV_ALIAS("branches", "BRANCH_INSNS"),
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EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCH_INSNS"),
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EV_ALIAS(NULL, NULL)
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};
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static struct pmc_event_alias octeon_aliases[] = {
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EV_ALIAS("instructions", "RET"),
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EV_ALIAS("branches", "BR"),
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EV_ALIAS("branch-mispredicts", "BRMIS"),
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EV_ALIAS(NULL, NULL)
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};
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#define MIPS_KW_OS "os"
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#define MIPS_KW_USR "usr"
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#define MIPS_KW_ANYTHREAD "anythread"
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static int
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mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
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struct pmc_op_pmcallocate *pmc_config __unused)
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{
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char *p;
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(void) pe;
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pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
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while ((p = strsep(&ctrspec, ",")) != NULL) {
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if (KWMATCH(p, MIPS_KW_OS))
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pmc_config->pm_caps |= PMC_CAP_SYSTEM;
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else if (KWMATCH(p, MIPS_KW_USR))
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pmc_config->pm_caps |= PMC_CAP_USER;
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else if (KWMATCH(p, MIPS_KW_ANYTHREAD))
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pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
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else
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return (-1);
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}
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return (0);
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}
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#endif /* __mips__ */
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#if defined(__powerpc__)
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static struct pmc_event_alias ppc7450_aliases[] = {
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@ -1211,22 +1139,6 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
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break;
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}
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break;
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case PMC_CLASS_BERI:
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ev = beri_event_table;
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count = PMC_EVENT_TABLE_SIZE(beri);
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break;
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case PMC_CLASS_MIPS24K:
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ev = mips24k_event_table;
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count = PMC_EVENT_TABLE_SIZE(mips24k);
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break;
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case PMC_CLASS_MIPS74K:
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ev = mips74k_event_table;
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count = PMC_EVENT_TABLE_SIZE(mips74k);
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break;
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case PMC_CLASS_OCTEON:
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ev = octeon_event_table;
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count = PMC_EVENT_TABLE_SIZE(octeon);
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break;
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case PMC_CLASS_PPC7450:
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ev = ppc7450_event_table;
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count = PMC_EVENT_TABLE_SIZE(ppc7450);
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@ -1426,24 +1338,6 @@ pmc_init(void)
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pmc_class_table[n] = &cortex_a76_class_table_descr;
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break;
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#endif
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#if defined(__mips__)
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case PMC_CPU_MIPS_BERI:
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PMC_MDEP_INIT(beri);
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pmc_class_table[n] = &beri_class_table_descr;
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break;
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case PMC_CPU_MIPS_24K:
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PMC_MDEP_INIT(mips24k);
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pmc_class_table[n] = &mips24k_class_table_descr;
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break;
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case PMC_CPU_MIPS_74K:
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PMC_MDEP_INIT(mips74k);
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pmc_class_table[n] = &mips74k_class_table_descr;
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break;
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case PMC_CPU_MIPS_OCTEON:
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PMC_MDEP_INIT(octeon);
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pmc_class_table[n] = &octeon_class_table_descr;
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break;
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#endif /* __mips__ */
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#if defined(__powerpc__)
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case PMC_CPU_PPC_7450:
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PMC_MDEP_INIT(ppc7450);
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@ -1570,18 +1464,6 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
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default: /* Unknown CPU type. */
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break;
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}
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} else if (pe >= PMC_EV_BERI_FIRST && pe <= PMC_EV_BERI_LAST) {
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ev = beri_event_table;
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evfence = beri_event_table + PMC_EVENT_TABLE_SIZE(beri);
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} else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) {
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ev = mips24k_event_table;
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evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k);
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} else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) {
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ev = mips74k_event_table;
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evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k);
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} else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) {
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ev = octeon_event_table;
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evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon);
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} else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
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ev = ppc7450_event_table;
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evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
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@ -491,8 +491,6 @@ API is
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.Xr pmc.ivybridgexeon 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.mips24k 3 ,
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.Xr pmc.octeon 3 ,
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.Xr pmc.sandybridge 3 ,
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.Xr pmc.sandybridgeuc 3 ,
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.Xr pmc.sandybridgexeon 3 ,
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@ -1,409 +0,0 @@
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.\" Copyright (c) 2010 George Neville-Neil. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd March 24, 2012
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.Dt PMC.MIPS24K 3
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.Os
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.Sh NAME
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.Nm pmc.mips24k
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.Nd measurement events for
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.Tn MIPS24K
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family CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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MIPS PMCs are present in MIPS
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.Tn "24k"
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and other processors in the MIPS family.
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.Pp
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There are two counters supported by the hardware and each is 32 bits
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wide.
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.Pp
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MIPS PMCs are documented in
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.Rs
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.%B "MIPS32 24K Processor Core Family Software User's Manual"
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.%D December 2008
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.%Q "MIPS Technologies Inc."
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.Re
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.Ss Event Specifiers (Programmable PMCs)
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MIPS programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li CYCLE
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.Pq Event 0, Counter 0/1
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Total number of cycles.
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The performance counters are clocked by the
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top-level gated clock.
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If the core is built with that clock gater
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present, none of the counters will increment while the clock is
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stopped - due to a WAIT instruction.
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.It Li INSTR_EXECUTED
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.Pq Event 1, Counter 0/1
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Total number of instructions completed.
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.It Li BRANCH_COMPLETED
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.Pq Event 2, Counter 0
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Total number of branch instructions completed.
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.It Li BRANCH_MISPRED
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.Pq Event 2, Counter 1
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Counts all branch instructions which completed, but were mispredicted.
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.It Li RETURN
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.Pq Event 3, Counter 0
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Counts all JR R31 instructions completed.
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.It Li RETURN_MISPRED
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.Pq Event 3, Counter 1
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Counts all JR $31 instructions which completed, used the RPS for a prediction, but were mispredicted.
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.It Li RETURN_NOT_31
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.Pq Event 4, Counter 0
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Counts all JR $xx (not $31) and JALR instructions (indirect jumps).
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.It Li RETURN_NOTPRED
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.Pq Event 4, Counter 1
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If RPS use is disabled, JR $31 will not be predicted.
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.It Li ITLB_ACCESS
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.Pq Event 5, Counter 0
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Counts ITLB accesses that are due to fetches showing up in the
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instruction fetch stage of the pipeline and which do not use a fixed
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mapping or are not in unmapped space.
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If an address is fetched twice from the pipe (as in the case of a
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cache miss), that instruction willcount as 2 ITLB accesses.
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Since each fetch gets us 2 instructions,there is one access marked per double
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word.
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.It Li ITLB_MISS
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.Pq Event 5, Counter 1
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Counts all misses in the ITLB except ones that are on the back of another
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miss.
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We cannot process back to back misses and thus those are
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ignored.
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They are also ignored if there is some form of address error.
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.It Li DTLB_ACCESS
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.Pq Event 6, Counter 0
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Counts DTLB access including those in unmapped address spaces.
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.It Li DTLB_MISS
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.Pq Event 6, Counter 1
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Counts DTLB misses.
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Back to back misses that result in only one DTLB
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entry getting refilled are counted as a single miss.
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.It Li JTLB_IACCESS
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.Pq Event 7, Counter 0
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Instruction JTLB accesses are counted exactly the same as ITLB misses.
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.It Li JTLB_IMISS
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.Pq Event 7, Counter 1
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Counts instruction JTLB accesses that result in no match or a match on
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an invalid translation.
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.It Li JTLB_DACCESS
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.Pq Event 8, Counter 0
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Data JTLB accesses.
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.It Li JTLB_DMISS
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.Pq Event 8, Counter 1
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Counts data JTLB accesses that result in no match or a match on an invalid translation.
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.It Li IC_FETCH
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.Pq Event 9, Counter 0
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Counts every time the instruction cache is accessed.
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All replays,
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wasted fetches etc. are counted.
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For example, following a branch, even though the prediction is taken,
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the fall through access is counted.
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.It Li IC_MISS
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.Pq Event 9, Counter 1
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Counts all instruction cache misses that result in a bus request.
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.It Li DC_LOADSTORE
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.Pq Event 10, Counter 0
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Counts cached loads and stores.
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.It Li DC_WRITEBACK
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.Pq Event 10, Counter 1
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Counts cache lines written back to memory due to replacement or cacheops.
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.It Li DC_MISS
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.Pq Event 11, Counter 0/1
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Counts loads and stores that miss in the cache
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.It Li LOAD_MISS
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.Pq Event 13, Counter 0
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Counts number of cacheable loads that miss in the cache.
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.It Li STORE_MISS
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.Pq Event 13, Counter 1
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Counts number of cacheable stores that miss in the cache.
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.It Li INTEGER_COMPLETED
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.Pq Event 14, Counter 0
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Non-floating point, non-Coprocessor 2 instructions.
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.It Li FP_COMPLETED
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.Pq Event 14, Counter 1
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Floating point instructions completed.
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.It Li LOAD_COMPLETED
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.Pq Event 15, Counter 0
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Integer and co-processor loads completed.
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.It Li STORE_COMPLETED
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.Pq Event 15, Counter 1
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Integer and co-processor stores completed.
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.It Li BARRIER_COMPLETED
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.Pq Event 16, Counter 0
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Direct jump (and link) instructions completed.
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.It Li MIPS16_COMPLETED
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.Pq Event 16, Counter 1
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MIPS16c instructions completed.
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.It Li NOP_COMPLETED
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.Pq Event 17, Counter 0
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NOPs completed.
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This includes all instructions that normally write to a general
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purpose register, but where the destination register was set to r0.
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.It Li INTEGER_MULDIV_COMPLETED
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.Pq Event 17, Counter 1
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Integer multiply and divide instructions completed. (MULxx, DIVx, MADDx, MSUBx).
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.It Li RF_STALL
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.Pq Event 18, Counter 0
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Counts the total number of cycles where no instructions are issued
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from the IFU to ALU (the RF stage does not advance) which includes
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both of the previous two events.
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The RT_STALL is different than the sum of them though because cycles
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when both stalls are active will only be counted once.
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.It Li INSTR_REFETCH
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.Pq Event 18, Counter 1
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replay traps (other than uTLB)
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.It Li STORE_COND_COMPLETED
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.Pq Event 19, Counter 0
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Conditional stores completed.
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Counts all events, including failed stores.
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.It Li STORE_COND_FAILED
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.Pq Event 19, Counter 1
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Conditional store instruction that did not update memory.
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Note: While this event and the SC instruction count event can be configured to
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count in specific operating modes, the timing of the events is much
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different and the observed operating mode could change between them,
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causing some inaccuracy in the measured ratio.
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.It Li ICACHE_REQUESTS
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.Pq Event 20, Counter 0
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Note that this only counts PREFs that are actually attempted.
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PREFs to uncached addresses or ones with translation errors are not counted
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.It Li ICACHE_HIT
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.Pq Event 20, Counter 1
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Counts PREF instructions that hit in the cache
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.It Li L2_WRITEBACK
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.Pq Event 21, Counter 0
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Counts cache lines written back to memory due to replacement or cacheops.
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.It Li L2_ACCESS
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.Pq Event 21, Counter 1
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Number of accesses to L2 Cache.
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.It Li L2_MISS
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.Pq Event 22, Counter 0
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Number of accesses that missed in the L2 cache.
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.It Li L2_ERR_CORRECTED
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.Pq Event 22, Counter 1
|
||||
Single bit errors in L2 Cache that were detected and corrected.
|
||||
.It Li EXCEPTIONS
|
||||
.Pq Event 23, Counter 0
|
||||
Any type of exception taken.
|
||||
.It Li RF_CYCLES_STALLED
|
||||
.Pq Event 24, Counter 0
|
||||
Counts cycles where the LSU is in fixup and cannot accept a new
|
||||
instruction from the ALU.
|
||||
Fixups are replays within the LSU that occur when an instruction needs
|
||||
to re-access the cache or the DTLB.
|
||||
.It Li IFU_CYCLES_STALLED
|
||||
.Pq Event 25, Counter 0
|
||||
Counts the number of cycles where the fetch unit is not providing a
|
||||
valid instruction to the ALU.
|
||||
.It Li ALU_CYCLES_STALLED
|
||||
.Pq Event 25, Counter 1
|
||||
Counts the number of cycles where the ALU pipeline cannot advance.
|
||||
.It Li UNCACHED_LOAD
|
||||
.Pq Event 33, Counter 0
|
||||
Counts uncached and uncached accelerated loads.
|
||||
.It Li UNCACHED_STORE
|
||||
.Pq Event 33, Counter 1
|
||||
Counts uncached and uncached accelerated stores.
|
||||
.It Li CP2_REG_TO_REG_COMPLETED
|
||||
.Pq Event 35, Counter 0
|
||||
Co-processor 2 register to register instructions completed.
|
||||
.It Li MFTC_COMPLETED
|
||||
.Pq Event 35, Counter 1
|
||||
Co-processor 2 move to and from instructions as well as loads and stores.
|
||||
.It Li IC_BLOCKED_CYCLES
|
||||
.Pq Event 37, Counter 0
|
||||
Cycles when IFU stalls because an instruction miss caused the IFU not
|
||||
to have any runnable instructions.
|
||||
Ignores the stalls due to ITLB misses as well as the 4 cycles
|
||||
following a redirect.
|
||||
.It Li DC_BLOCKED_CYCLES
|
||||
.Pq Event 37, Counter 1
|
||||
Counts all cycles where integer pipeline waits on Load return data due
|
||||
to a D-cache miss.
|
||||
The LSU can signal a "long stall" on a D-cache misses, in which case
|
||||
the waiting TC might be rescheduled so other TCs can execute
|
||||
instructions till the data returns.
|
||||
.It Li L2_IMISS_STALL_CYCLES
|
||||
.Pq Event 38, Counter 0
|
||||
Cycles where the main pipeline is stalled waiting for a SYNC to complete.
|
||||
.It Li L2_DMISS_STALL_CYCLES
|
||||
.Pq Event 38, Counter 1
|
||||
Cycles where the main pipeline is stalled because of an index conflict
|
||||
in the Fill Store Buffer.
|
||||
.It Li DMISS_CYCLES
|
||||
.Pq Event 39, Counter 0
|
||||
Data miss is outstanding, but not necessarily stalling the pipeline.
|
||||
The difference between this and D$ miss stall cycles can show the gain
|
||||
from non-blocking cache misses.
|
||||
.It Li L2_MISS_CYCLES
|
||||
.Pq Event 39, Counter 1
|
||||
L2 miss is outstanding, but not necessarily stalling the pipeline.
|
||||
.It Li UNCACHED_BLOCK_CYCLES
|
||||
.Pq Event 40, Counter 0
|
||||
Cycles where the processor is stalled on an uncached fetch, load, or store.
|
||||
.It Li MDU_STALL_CYCLES
|
||||
.Pq Event 41, Counter 0
|
||||
Cycles where the processor is stalled on an uncached fetch, load, or store.
|
||||
.It Li FPU_STALL_CYCLES
|
||||
.Pq Event 41, Counter 1
|
||||
Counts all cycles where integer pipeline waits on FPU return data.
|
||||
.It Li CP2_STALL_CYCLES
|
||||
.Pq Event 42, Counter 0
|
||||
Counts all cycles where integer pipeline waits on CP2 return data.
|
||||
.It Li COREXTEND_STALL_CYCLES
|
||||
.Pq Event 42, Counter 1
|
||||
Counts all cycles where integer pipeline waits on CorExtend return data.
|
||||
.It Li ISPRAM_STALL_CYCLES
|
||||
.Pq Event 43, Counter 0
|
||||
Count all pipeline bubbles that are a result of multicycle ISPRAM
|
||||
access.
|
||||
Pipeline bubbles are defined as all cycles that IFU doesn't present an
|
||||
instruction to ALU.
|
||||
The four cycles after a redirect are not counted.
|
||||
.It Li DSPRAM_STALL_CYCLES
|
||||
.Pq Event 43, Counter 1
|
||||
Counts stall cycles created by an instruction waiting for access to DSPRAM.
|
||||
.It Li CACHE_STALL_CYCLES
|
||||
.Pq Event 44, Counter 0
|
||||
Counts all cycles the where pipeline is stalled due to CACHE
|
||||
instructions.
|
||||
Includes cycles where CACHE instructions themselves are
|
||||
stalled in the ALU, and cycles where CACHE instructions cause
|
||||
subsequent instructions to be stalled.
|
||||
.It Li LOAD_TO_USE_STALLS
|
||||
.Pq Event 45, Counter 0
|
||||
Counts all cycles where integer pipeline waits on Load return data.
|
||||
.It Li BASE_MISPRED_STALLS
|
||||
.Pq Event 45, Counter 1
|
||||
Counts stall cycles due to skewed ALU where the bypass to the address
|
||||
generation takes an extra cycle.
|
||||
.It Li CPO_READ_STALLS
|
||||
.Pq Event 46, Counter 0
|
||||
Counts all cycles where integer pipeline waits on return data from
|
||||
MFC0, RDHWR instructions.
|
||||
.It Li BRANCH_MISPRED_CYCLES
|
||||
.Pq Event 46, Counter 1
|
||||
This counts the number of cycles from a mispredicted branch until the
|
||||
next non-delay slot instruction executes.
|
||||
.It Li IFETCH_BUFFER_FULL
|
||||
.Pq Event 48, Counter 0
|
||||
Counts the number of times an instruction cache miss was detected, but
|
||||
both fill buffers were already allocated.
|
||||
.It Li FETCH_BUFFER_ALLOCATED
|
||||
.Pq Event 48, Counter 1
|
||||
Number of cycles where at least one of the IFU fill buffers is
|
||||
allocated (miss pending).
|
||||
.It Li EJTAG_ITRIGGER
|
||||
.Pq Event 49, Counter 0
|
||||
Number of times an EJTAG Instruction Trigger Point condition matched.
|
||||
.It Li EJTAG_DTRIGGER
|
||||
.Pq Event 49, Counter 1
|
||||
Number of times an EJTAG Data Trigger Point condition matched.
|
||||
.It Li FSB_LT_QUARTER
|
||||
.Pq Event 50, Counter 0
|
||||
Fill store buffer less than one quarter full.
|
||||
.It Li FSB_QUARTER_TO_HALF
|
||||
.Pq Event 50, Counter 1
|
||||
Fill store buffer between one quarter and one half full.
|
||||
.It Li FSB_GT_HALF
|
||||
.Pq Event 51, Counter 0
|
||||
Fill store buffer more than half full.
|
||||
.It Li FSB_FULL_PIPELINE_STALLS
|
||||
.Pq Event 51, Counter 1
|
||||
Cycles where the pipeline is stalled because the Fill-Store Buffer in LSU is full.
|
||||
.It Li LDQ_LT_QUARTER
|
||||
.Pq Event 52, Counter 0
|
||||
Load data queue less than one quarter full.
|
||||
.It Li LDQ_QUARTER_TO_HALF
|
||||
.Pq Event 52, Counter 1
|
||||
Load data queue between one quarter and one half full.
|
||||
.It Li LDQ_GT_HALF
|
||||
.Pq Event 53, Counter 0
|
||||
Load data queue more than one half full.
|
||||
.It Li LDQ_FULL_PIPELINE_STALLS
|
||||
.Pq Event 53, Counter 1
|
||||
Cycles where the pipeline is stalled because the Load Data Queue in the LSU is full.
|
||||
.It Li WBB_LT_QUARTER
|
||||
.Pq Event 54, Counter 0
|
||||
Write back buffer less than one quarter full.
|
||||
.It Li WBB_QUARTER_TO_HALF
|
||||
.Pq Event 54, Counter 1
|
||||
Write back buffer between one quarter and one half full.
|
||||
.It Li WBB_GT_HALF
|
||||
.Pq Event 55, Counter 0
|
||||
Write back buffer more than one half full.
|
||||
.It Li WBB_FULL_PIPELINE_STALLS
|
||||
.Pq Event 55 Counter 1
|
||||
Cycles where the pipeline is stalled because the Load Data Queue in the LSU is full.
|
||||
.It Li REQUEST_LATENCY
|
||||
.Pq Event 61, Counter 0
|
||||
Measures latency from miss detection until critical dword of response
|
||||
is returned, Only counts for cacheable reads.
|
||||
.It Li REQUEST_COUNT
|
||||
.Pq Event 61, Counter 1
|
||||
Counts number of cacheable read requests used for previous latency counter.
|
||||
.El
|
||||
.Ss Event Name Aliases
|
||||
The following table shows the mapping between the PMC-independent
|
||||
aliases supported by
|
||||
.Lb libpmc
|
||||
and the underlying hardware events used.
|
||||
.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p"
|
||||
.It Em Alias Ta Em Event
|
||||
.It Li instructions Ta Li INSTR_EXECUTED
|
||||
.It Li branches Ta Li BRANCH_COMPLETED
|
||||
.It Li branch-mispredicts Ta Li BRANCH_MISPRED
|
||||
.El
|
||||
.Sh SEE ALSO
|
||||
.Xr pmc 3 ,
|
||||
.Xr pmc.atom 3 ,
|
||||
.Xr pmc.core 3 ,
|
||||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.octeon 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
.Xr pmc.tsc 3 ,
|
||||
.Xr pmc_cpuinfo 3 ,
|
||||
.Xr pmclog 3 ,
|
||||
.Xr hwpmc 4
|
||||
.Sh HISTORY
|
||||
The
|
||||
.Nm pmc
|
||||
library first appeared in
|
||||
.Fx 6.0 .
|
||||
.Sh AUTHORS
|
||||
.An -nosplit
|
||||
The
|
||||
.Lb libpmc
|
||||
library was written by
|
||||
.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
|
||||
MIPS support was added by
|
||||
.An George Neville-Neil Aq Mt gnn@FreeBSD.org .
|
||||
@ -1,249 +0,0 @@
|
||||
.\" Copyright (c) 2010 George Neville-Neil. All rights reserved.
|
||||
.\"
|
||||
.\" Redistribution and use in source and binary forms, with or without
|
||||
.\" modification, are permitted provided that the following conditions
|
||||
.\" are met:
|
||||
.\" 1. Redistributions of source code must retain the above copyright
|
||||
.\" notice, this list of conditions and the following disclaimer.
|
||||
.\" 2. Redistributions in binary form must reproduce the above copyright
|
||||
.\" notice, this list of conditions and the following disclaimer in the
|
||||
.\" documentation and/or other materials provided with the distribution.
|
||||
.\"
|
||||
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
.\" SUCH DAMAGE.
|
||||
.\"
|
||||
.\" $FreeBSD$
|
||||
.\"
|
||||
.Dd March 24, 2012
|
||||
.Dt PMC.OCTEON 3
|
||||
.Os
|
||||
.Sh NAME
|
||||
.Nm pmc.octeon
|
||||
.Nd measurement events for
|
||||
.Tn Octeon
|
||||
family CPUs
|
||||
.Sh LIBRARY
|
||||
.Lb libpmc
|
||||
.Sh SYNOPSIS
|
||||
.In pmc.h
|
||||
.Sh DESCRIPTION
|
||||
There are two counters per core supported by the hardware and each is 64 bits
|
||||
wide.
|
||||
.Ss Event Specifiers (Programmable PMCs)
|
||||
MIPS programmable PMCs support the following events:
|
||||
.Bl -tag -width indent
|
||||
.It Li CLK
|
||||
.Pq Event 1
|
||||
Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks)
|
||||
.It Li ISSUE
|
||||
.Pq Event 2
|
||||
Instructions issued but not retired
|
||||
.It Li RET
|
||||
.Pq Event 3
|
||||
Instructions retired
|
||||
.It Li NISSUE
|
||||
.Pq Event 4
|
||||
Cycles no issue
|
||||
.It Li SISSUE
|
||||
.Pq Event 5
|
||||
Cycles single issue
|
||||
.It Li DISSUE
|
||||
.Pq Event 6
|
||||
Cycles dual issue
|
||||
.It Li IFI
|
||||
.Pq Event 7
|
||||
Cycle ifetch issued (but not necessarily commit to pp_mem)
|
||||
.It Li BR
|
||||
.Pq Event 8
|
||||
Branches retired
|
||||
.It Li BRMIS
|
||||
.Pq Event 9
|
||||
Branch mispredicts
|
||||
.It Li J
|
||||
.Pq Event 10
|
||||
Jumps retired
|
||||
.It Li JMIS
|
||||
.Pq Event 11
|
||||
Jumps mispredicted
|
||||
.It Li REPLAY
|
||||
.Pq Event 12
|
||||
Mem Replays
|
||||
.It Li IUNA
|
||||
.Pq Event 13
|
||||
Cycles idle due to unaligned_replays
|
||||
.It Li TRAP
|
||||
.Pq Event 14
|
||||
trap_6a signal
|
||||
.It Li UULOAD
|
||||
.Pq Event 16
|
||||
Unexpected unaligned loads (REPUN=1)
|
||||
.It Li UUSTORE
|
||||
.Pq Event 17
|
||||
Unexpected unaligned store (REPUN=1)
|
||||
.It Li ULOAD
|
||||
.Pq Event 18
|
||||
Unaligned loads (REPUN=1 or USEUN=1)
|
||||
.It Li USTORE
|
||||
.Pq Event 19
|
||||
Unaligned store (REPUN=1 or USEUN=1)
|
||||
.It Li EC
|
||||
.Pq Event 20
|
||||
Exec clocks(must set CvmCtl[DISCE] for accurate timing)
|
||||
.It Li MC
|
||||
.Pq Event 21
|
||||
Mul clocks(must set CvmCtl[DISCE] for accurate timing)
|
||||
.It Li CC
|
||||
.Pq Event 22
|
||||
Crypto clocks(must set CvmCtl[DISCE] for accurate timing)
|
||||
.It Li CSRC
|
||||
.Pq Event 23
|
||||
Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing)
|
||||
.It Li CFETCH
|
||||
.Pq Event 24
|
||||
Icache committed fetches (demand+prefetch)
|
||||
.It Li CPREF
|
||||
.Pq Event 25
|
||||
Icache committed prefetches
|
||||
.It Li ICA
|
||||
.Pq Event 26
|
||||
Icache aliases
|
||||
.It Li II
|
||||
.Pq Event 27
|
||||
Icache invalidates
|
||||
.It Li IP
|
||||
.Pq Event 28
|
||||
Icache parity error
|
||||
.It Li CIMISS
|
||||
.Pq Event 29
|
||||
Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing)
|
||||
.It Li WBUF
|
||||
.Pq Event 32
|
||||
Number of write buffer entries created
|
||||
.It Li WDAT
|
||||
.Pq Event 33
|
||||
Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts)
|
||||
.It Li WBUFLD
|
||||
.Pq Event 34
|
||||
Number of write buffer entries forced out by loads
|
||||
.It Li WBUFFL
|
||||
.Pq Event 35
|
||||
Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts)
|
||||
.It Li WBUFTR
|
||||
.Pq Event 36
|
||||
Number of stores that found no available write buffer entries
|
||||
.It Li BADD
|
||||
.Pq Event 37
|
||||
Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts)
|
||||
.It Li BADDL2
|
||||
.Pq Event 38
|
||||
Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts)
|
||||
.It Li BFILL
|
||||
.Pq Event 39
|
||||
Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts)
|
||||
.It Li DDIDS
|
||||
.Pq Event 40
|
||||
Number of Dstream DIDs created
|
||||
.It Li IDIDS
|
||||
.Pq Event 41
|
||||
Number of Istream DIDs created
|
||||
.It Li DIDNA
|
||||
.Pq Event 42
|
||||
Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts)
|
||||
.It Li LDS
|
||||
.Pq Event 43
|
||||
Number of load issues
|
||||
.It Li LMLDS
|
||||
.Pq Event 44
|
||||
Number of local memory load
|
||||
.It Li IOLDS
|
||||
.Pq Event 45
|
||||
Number of I/O load issues
|
||||
.It Li DMLDS
|
||||
.Pq Event 46
|
||||
Number of loads that were not prefetches and missed in the cache
|
||||
.It Li STS
|
||||
.Pq Event 48
|
||||
Number of store issues
|
||||
.It Li LMSTS
|
||||
.Pq Event 49
|
||||
Number of local memory store issues
|
||||
.It Li IOSTS
|
||||
.Pq Event 50
|
||||
Number of I/O store issues
|
||||
.It Li IOBDMA
|
||||
.Pq Event 51
|
||||
Number of IOBDMAs
|
||||
.It Li DTLB
|
||||
.Pq Event 53
|
||||
Number of dstream TLB refill, invalid, or modified exceptions
|
||||
.It Li DTLBAD
|
||||
.Pq Event 54
|
||||
Number of dstream TLB address errors
|
||||
.It Li ITLB
|
||||
.Pq Event 55
|
||||
Number of istream TLB refill, invalid, or address error exceptions
|
||||
.It Li SYNC
|
||||
.Pq Event 56
|
||||
Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts)
|
||||
.It Li SYNCIOB
|
||||
.Pq Event 57
|
||||
Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts)
|
||||
.It Li SYNCW
|
||||
.Pq Event 58
|
||||
Number of SYNCWs
|
||||
.It Li ERETMIS
|
||||
.Pq Event 64
|
||||
D/eret mispredicts (CN63XX specific)
|
||||
.It Li LIKMIS
|
||||
.Pq Event 65
|
||||
Branch likely mispredicts (CN63XX specific)
|
||||
.It Li HAZTR
|
||||
.Pq Event 66
|
||||
Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers (CN63XX specific)
|
||||
.El
|
||||
.Ss Event Name Aliases
|
||||
The following table shows the mapping between the PMC-independent
|
||||
aliases supported by
|
||||
.Lb libpmc
|
||||
and the underlying hardware events used.
|
||||
.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p"
|
||||
.It Em Alias Ta Em Event
|
||||
.It Li instructions Ta Li RET
|
||||
.It Li branches Ta Li BR
|
||||
.It Li branch-mispredicts Ta Li BS
|
||||
.El
|
||||
.Sh SEE ALSO
|
||||
.Xr pmc 3 ,
|
||||
.Xr pmc.atom 3 ,
|
||||
.Xr pmc.core 3 ,
|
||||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.mips24k 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
.Xr pmc.tsc 3 ,
|
||||
.Xr pmc_cpuinfo 3 ,
|
||||
.Xr pmclog 3 ,
|
||||
.Xr hwpmc 4
|
||||
.Sh HISTORY
|
||||
The
|
||||
.Nm pmc
|
||||
library first appeared in
|
||||
.Fx 6.0 .
|
||||
.Sh AUTHORS
|
||||
.An -nosplit
|
||||
The
|
||||
.Lb libpmc
|
||||
library was written by
|
||||
.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
|
||||
MIPS support was added by
|
||||
.An George Neville-Neil Aq Mt gnn@FreeBSD.org .
|
||||
Loading…
Reference in New Issue
Block a user