Move initialization of CESA decoding windows from common section
to driver specific files. - window initialization is done during device attach - CESA TDMA decoding windows values are set based on DTS, not copied from CPU registers - remove unnecessary virtual mapping - update dts file Obtained from: Semihalf
This commit is contained in:
Grzegorz Bernacki
parent
7f3d2746af
commit
99eef68204
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=250291
@ -83,7 +83,7 @@ static int decode_win_usb_valid(void);
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static int decode_win_eth_valid(void);
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static int decode_win_pcie_valid(void);
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static int decode_win_sata_valid(void);
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static int decode_win_cesa_valid(void);
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static int decode_win_idma_valid(void);
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static int decode_win_xor_valid(void);
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@ -93,11 +93,10 @@ static void decode_win_cpu_setup(void);
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static void decode_win_usb_setup(u_long);
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static void decode_win_eth_setup(u_long);
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static void decode_win_sata_setup(u_long);
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static void decode_win_cesa_setup(u_long);
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static void decode_win_idma_setup(u_long);
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static void decode_win_xor_setup(u_long);
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static void decode_win_cesa_dump(u_long);
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static void decode_win_usb_dump(u_long);
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static void decode_win_eth_dump(u_long base);
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static void decode_win_idma_dump(u_long base);
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@ -127,7 +126,6 @@ struct soc_node_spec {
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};
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static struct soc_node_spec soc_nodes[] = {
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{ "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump },
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{ "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump },
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{ "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
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{ "mrvl,sata", &decode_win_sata_setup, NULL },
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@ -143,7 +141,6 @@ struct fdt_pm_mask_entry fdt_pm_mask_table[] = {
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{ "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) },
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{ "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) },
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{ "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) },
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{ "mrvl,cesa", CPU_PM_CTRL_CRYPTO },
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{ "mrvl,xor", CPU_PM_CTRL_XOR },
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{ "mrvl,sata", CPU_PM_CTRL_SATA },
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@ -529,7 +526,7 @@ soc_decode_win(void)
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if (!decode_win_cpu_valid() || !decode_win_usb_valid() ||
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!decode_win_eth_valid() || !decode_win_idma_valid() ||
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!decode_win_pcie_valid() || !decode_win_sata_valid() ||
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!decode_win_cesa_valid() || !decode_win_xor_valid())
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!decode_win_xor_valid())
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return (EINVAL);
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decode_win_cpu_setup();
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@ -537,7 +534,7 @@ soc_decode_win(void)
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if (!decode_win_usb_valid() ||
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!decode_win_eth_valid() || !decode_win_idma_valid() ||
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!decode_win_pcie_valid() || !decode_win_sata_valid() ||
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!decode_win_cesa_valid() || !decode_win_xor_valid())
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!decode_win_xor_valid())
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return (EINVAL);
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#endif
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if (MV_DUMP_WIN)
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@ -570,11 +567,6 @@ WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)
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WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL)
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WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE)
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WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL)
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WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE)
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WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL)
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WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE)
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WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
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WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
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WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
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@ -1790,98 +1782,6 @@ decode_win_xor_dump(u_long base)
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}
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#endif
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/**************************************************************************
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* CESA TDMA windows routines
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**************************************************************************/
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#if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
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/*
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* Dump CESA TDMA decode windows.
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*/
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static void
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decode_win_cesa_dump(u_long base)
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{
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int i;
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if (pm_is_disabled(CPU_PM_CTRL_CRYPTO))
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return;
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for (i = 0; i < MV_WIN_CESA_MAX; i++)
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printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i,
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win_cesa_cr_read(base, i), win_cesa_br_read(base, i));
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}
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/*
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* Set CESA TDMA decode windows.
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*/
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static void
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decode_win_cesa_setup(u_long base)
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{
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uint32_t br, cr;
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int i, j;
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if (pm_is_disabled(CPU_PM_CTRL_CRYPTO))
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return;
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/* Disable and clear all CESA windows */
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for (i = 0; i < MV_WIN_CESA_MAX; i++) {
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win_cesa_cr_write(base, i, 0);
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win_cesa_br_write(base, i, 0);
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}
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/* Only access to active DRAM banks is required. */
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for (i = 0; i < MV_WIN_DDR_MAX; i++)
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if (ddr_is_active(i)) {
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br = ddr_base(i);
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cr = (((ddr_size(i) - 1) & 0xffff0000) |
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(ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1);
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/* Set the first available CESA window */
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for (j = 0; j < MV_WIN_CESA_MAX; j++) {
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if (win_cesa_cr_read(base, j) & 0x1)
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continue;
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win_cesa_br_write(base, j, br);
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win_cesa_cr_write(base, j, cr);
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break;
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}
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}
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}
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/*
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* Check CESA TDMA decode windows.
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*/
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static int
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decode_win_cesa_valid(void)
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{
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return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX));
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}
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#else
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/*
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* Provide dummy functions to satisfy the build for SoCs not equipped with
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* CESA
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*/
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static int
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decode_win_cesa_valid(void)
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{
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return (1);
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}
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static void
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decode_win_cesa_setup(u_long base)
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{
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}
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static void
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decode_win_cesa_dump(u_long base)
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{
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}
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#endif
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/**************************************************************************
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* SATA windows routines
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**************************************************************************/
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@ -1979,33 +1879,34 @@ static int
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win_cpu_from_dt(void)
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{
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pcell_t ranges[48];
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u_long sram_base, sram_size;
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phandle_t node;
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int i, entry_size, err, t, tuple_size, tuples;
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u_long sram_base, sram_size;
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t = 0;
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/* Retrieve 'ranges' property of '/localbus' node. */
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if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges),
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&tuples, &tuple_size)) != 0)
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return (0);
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&tuples, &tuple_size)) == 0) {
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/*
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* Fill CPU decode windows table.
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*/
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bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl));
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/*
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* Fill CPU decode windows table.
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*/
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bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl));
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entry_size = tuple_size / sizeof(pcell_t);
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cpu_wins_no = tuples;
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entry_size = tuple_size / sizeof(pcell_t);
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cpu_wins_no = tuples;
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for (i = 0, t = 0; t < tuples; i += entry_size, t++) {
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cpu_win_tbl[t].target = 1;
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cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]);
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cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]);
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cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]);
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cpu_win_tbl[t].remap = ~0;
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debugf("target = 0x%0x attr = 0x%0x base = 0x%0x "
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"size = 0x%0x remap = 0x%0x\n", cpu_win_tbl[t].target,
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cpu_win_tbl[t].attr, cpu_win_tbl[t].base,
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cpu_win_tbl[t].size, cpu_win_tbl[t].remap);
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for (i = 0, t = 0; t < tuples; i += entry_size, t++) {
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cpu_win_tbl[t].target = 1;
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cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]);
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cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]);
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cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]);
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cpu_win_tbl[t].remap = ~0;
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debugf("target = 0x%0x attr = 0x%0x base = 0x%0x "
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"size = 0x%0x remap = 0x%0x\n",
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cpu_win_tbl[t].target,
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cpu_win_tbl[t].attr, cpu_win_tbl[t].base,
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cpu_win_tbl[t].size, cpu_win_tbl[t].remap);
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}
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}
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/*
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@ -2015,7 +1916,7 @@ win_cpu_from_dt(void)
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if (fdt_is_compatible(node, "mrvl,cesa-sram"))
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goto moveon;
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if ((node = OF_finddevice("/")) == -1)
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if ((node = OF_finddevice("/")) == 0)
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return (ENXIO);
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if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0)
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@ -2026,11 +1927,12 @@ win_cpu_from_dt(void)
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if (fdt_regsize(node, &sram_base, &sram_size) != 0)
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return (EINVAL);
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cpu_win_tbl[++t].target = MV_WIN_CESA_TARGET;
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cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR;
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cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
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cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
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cpu_win_tbl[t].base = sram_base;
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cpu_win_tbl[t].size = sram_size;
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cpu_win_tbl[t].remap = ~0;
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cpu_wins_no++;
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debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
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return (0);
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@ -310,7 +310,6 @@ platform_devmap_init(void)
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{
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phandle_t root, child;
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pcell_t bank_count;
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u_long base, size;
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int i, num_mapped;
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i = 0;
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@ -381,29 +380,6 @@ platform_devmap_init(void)
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}
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}
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/*
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* CESA SRAM range.
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*/
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if ((child = OF_finddevice("sram")) != -1)
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if (fdt_is_compatible(child, "mrvl,cesa-sram"))
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goto moveon;
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if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0)
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/* No CESA SRAM node. */
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return (0);
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moveon:
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if (i >= FDT_DEVMAP_MAX)
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return (ENOMEM);
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if (fdt_regsize(child, &base, &size) != 0)
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return (EINVAL);
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fdt_devmap[i].pd_va = MV_CESA_SRAM_BASE; /* XXX */
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fdt_devmap[i].pd_pa = base;
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fdt_devmap[i].pd_size = size;
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fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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fdt_devmap[i].pd_cache = PTE_NOCACHE;
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return (0);
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}
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@ -208,16 +208,28 @@
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#define MV_WIN_DDR_MAX 4
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#endif /* SOC_MV_DOVE */
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#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04)
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#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00)
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#define MV_WIN_CESA_MAX 4
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/*
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* These values are valid only for peripherals decoding windows
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* Bit in ATTR is zeroed according to CS bank number
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*/
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#define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs)))
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#define MV_WIN_DDR_TARGET 0x0
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#if defined(SOC_MV_DISCOVERY)
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#define MV_WIN_CESA_TARGET 9
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#define MV_WIN_CESA_ATTR 1
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#define MV_WIN_CESA_ATTR(eng_sel) 1
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#elif defined(SOC_MV_ARMADAXP)
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#define MV_WIN_CESA_TARGET 9
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/*
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* Bits [2:3] of cesa attribute select engine:
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* eng_sel:
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* 1: engine1
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* 2: engine0
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*/
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#define MV_WIN_CESA_ATTR(eng_sel) (1 | ((eng_sel) << 2))
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#else
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#define MV_WIN_CESA_TARGET 3
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#define MV_WIN_CESA_ATTR 0
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#define MV_WIN_CESA_ATTR(eng_sel) 0
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#endif
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#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320)
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@ -303,6 +303,11 @@
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>;
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};
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sram@ffff0000 {
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compatible = "mrvl,cesa-sram";
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reg = <0xffff0000 0x00010000>;
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};
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chosen {
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stdin = "serial0";
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stdout = "serial0";
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@ -80,6 +80,7 @@ static void cesa_intr(void *);
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static int cesa_newsession(device_t, u_int32_t *, struct cryptoini *);
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static int cesa_freesession(device_t, u_int64_t);
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static int cesa_process(device_t, struct cryptop *, int);
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static int decode_win_cesa_setup(struct cesa_softc *sc);
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static struct resource_spec cesa_res_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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@ -995,10 +996,10 @@ cesa_attach(device_t dev)
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sc->sc_error = 0;
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sc->sc_dev = dev;
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error = cesa_setup_sram(sc);
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if (error) {
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device_printf(dev, "could not setup SRAM\n");
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return (error);
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/* Check if CESA peripheral device has power turned on */
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if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) != CPU_PM_CTRL_CRYPTO) {
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device_printf(dev, "not powered on\n");
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return (ENXIO);
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}
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soc_id(&d, &r);
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@ -1038,6 +1039,20 @@ cesa_attach(device_t dev)
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sc->sc_bsh = rman_get_bushandle(*(sc->sc_res));
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sc->sc_bst = rman_get_bustag(*(sc->sc_res));
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/* Setup CESA decoding windows */
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error = decode_win_cesa_setup(sc);
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if (error) {
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device_printf(dev, "could not setup decoding windows\n");
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goto err1;
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}
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/* Acquire SRAM base address */
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error = cesa_setup_sram(sc);
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if (error) {
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device_printf(dev, "could not setup SRAM\n");
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goto err1;
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}
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/* Setup interrupt handler */
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error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
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NULL, cesa_intr, sc, &(sc->sc_icookie));
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@ -1609,3 +1624,50 @@ cesa_process(device_t dev, struct cryptop *crp, int hint)
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return (0);
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}
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/*
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* Set CESA TDMA decode windows.
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*/
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static int
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decode_win_cesa_setup(struct cesa_softc *sc)
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{
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struct mem_region availmem_regions[FDT_MEM_REGIONS];
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int availmem_regions_sz;
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uint32_t memsize, br, cr, i;
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/* Grab physical memory regions information from DTS */
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if (fdt_get_mem_regions(availmem_regions, &availmem_regions_sz,
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&memsize) != 0)
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return (ENXIO);
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if (availmem_regions_sz > MV_WIN_CESA_MAX) {
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device_printf(sc->sc_dev, "Too much memory regions, cannot "
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" set CESA windows to cover whole DRAM \n");
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return (ENXIO);
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}
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/* Disable and clear all CESA windows */
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for (i = 0; i < MV_WIN_CESA_MAX; i++) {
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CESA_WRITE(sc, MV_WIN_CESA_BASE(i), 0);
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CESA_WRITE(sc, MV_WIN_CESA_CTRL(i), 0);
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}
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/* Fill CESA TDMA decoding windows with information acquired from DTS */
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for (i = 0; i < availmem_regions_sz; i++) {
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br = availmem_regions[i].mr_start;
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cr = availmem_regions[i].mr_size;
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/* Don't add entries with size lower than 64KB */
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if (cr & 0xffff0000) {
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cr = (((cr - 1) & 0xffff0000) |
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(MV_WIN_DDR_ATTR(i) << MV_WIN_CPU_ATTR_SHIFT) |
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(MV_WIN_DDR_TARGET << MV_WIN_CPU_TARGET_SHIFT) |
|
||||
MV_WIN_CPU_ENABLE_BIT);
|
||||
CESA_WRITE(sc, MV_WIN_CESA_BASE(i), br);
|
||||
CESA_WRITE(sc, MV_WIN_CESA_CTRL(i), cr);
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
@ -333,6 +333,11 @@ struct cesa_chain_info {
|
||||
#define CESA_TDMA_EMR_BOTH_HIT CESA_TDMA_ECR_BOTH_HIT
|
||||
#define CESA_TDMA_EMR_DATA_ERROR CESA_TDMA_ECR_DATA_ERROR
|
||||
|
||||
/* CESA TDMA address decoding registers */
|
||||
#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04)
|
||||
#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00)
|
||||
#define MV_WIN_CESA_MAX 4
|
||||
|
||||
/* CESA SA registers definitions */
|
||||
#define CESA_SA_CMD 0xDE00
|
||||
#define CESA_SA_CMD_ACTVATE (1 << 0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user