Add support for the Marvell 88E6190 11 ports switch.
With more ports, some of the registers are shifted a bit to accommodate. This switch also adds two high speed Serdes/SGMII interfaces (2.5 Gb/s). Sponsored by: Rubicon Communications, LLC (Netgate)
This commit is contained in:
Luiz Otavio O Souza
parent
b46517aa7b
commit
9aba06377d
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=349578
@ -106,6 +106,8 @@ static int e6000sw_parse_fixed_link(e6000sw_softc_t *, phandle_t, uint32_t);
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static int e6000sw_parse_ethernet(e6000sw_softc_t *, phandle_t, uint32_t);
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static int e6000sw_attach(device_t);
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static int e6000sw_detach(device_t);
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static int e6000sw_read_xmdio(device_t, int, int, int);
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static int e6000sw_write_xmdio(device_t, int, int, int, int);
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static int e6000sw_readphy(device_t, int, int);
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static int e6000sw_writephy(device_t, int, int, int);
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static etherswitch_info_t* e6000sw_getinfo(device_t);
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@ -205,16 +207,26 @@ e6000sw_probe(device_t dev)
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const char *description;
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phandle_t switch_node;
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sc = device_get_softc(dev);
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switch_node = ofw_bus_find_compatible(OF_finddevice("/"),
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"marvell,mv88e6085");
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if (switch_node == 0) {
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switch_node = ofw_bus_find_compatible(OF_finddevice("/"),
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"marvell,mv88e6190");
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if (switch_node == 0)
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return (ENXIO);
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if (switch_node == 0)
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return (ENXIO);
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/*
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* Trust DTS and fix the port register offset for the MV88E6190
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* detection bellow.
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*/
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sc->swid = MV88E6190;
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}
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if (bootverbose)
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device_printf(dev, "Found switch_node: 0x%x\n", switch_node);
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->node = switch_node;
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@ -230,7 +242,7 @@ e6000sw_probe(device_t dev)
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*/
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sx_init(&sc->sx, "e6000sw_tmp");
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E6000SW_LOCK(sc);
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sc->swid = e6000sw_readreg(sc, REG_PORT(0), SWITCH_ID) & 0xfff0;
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sc->swid = e6000sw_readreg(sc, REG_PORT(sc, 0), SWITCH_ID) & 0xfff0;
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E6000SW_UNLOCK(sc);
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sx_destroy(&sc->sx);
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@ -257,6 +269,10 @@ e6000sw_probe(device_t dev)
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description = "Marvell 88E6176";
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sc->num_ports = 7;
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break;
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case MV88E6190:
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description = "Marvell 88E6190";
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sc->num_ports = 11;
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break;
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default:
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device_printf(dev, "Unrecognized device, id 0x%x.\n", sc->swid);
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return (ENXIO);
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@ -278,18 +294,16 @@ e6000sw_parse_fixed_link(e6000sw_softc_t *sc, phandle_t node, uint32_t port)
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if (fixed_link != 0) {
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sc->fixed_mask |= (1 << port);
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if (OF_getencprop(fixed_link, "speed", &speed, sizeof(speed))> 0) {
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if (speed == 2500 &&
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(MVSWITCH(sc, MV88E6141) ||
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MVSWITCH(sc, MV88E6341)))
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sc->fixed25_mask |= (1 << port);
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} else {
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device_printf(sc->dev,
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if (OF_getencprop(fixed_link,
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"speed", &speed, sizeof(speed)) < 0) {
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device_printf(sc->dev,
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"Port %d has a fixed-link node without a speed "
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"property\n", port);
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return (ENXIO);
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return (ENXIO);
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}
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if (speed == 2500 && (MVSWITCH(sc, MV88E6141) ||
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MVSWITCH(sc, MV88E6341) || MVSWITCH(sc, MV88E6190)))
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sc->fixed25_mask |= (1 << port);
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}
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return (0);
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@ -383,9 +397,36 @@ e6000sw_attach_miibus(e6000sw_softc_t *sc, int port)
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return (0);
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}
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static void
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e6000sw_serdes_power(device_t dev, int port, bool sgmii)
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{
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uint32_t reg;
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/* SGMII */
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reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV,
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E6000SW_SERDES_SGMII_CTL);
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if (sgmii)
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reg &= ~E6000SW_SERDES_PDOWN;
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else
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reg |= E6000SW_SERDES_PDOWN;
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e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV,
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E6000SW_SERDES_SGMII_CTL, reg);
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/* 10GBASE-R/10GBASE-X4/X2 */
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reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV,
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E6000SW_SERDES_PCS_CTL1);
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if (sgmii)
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reg |= E6000SW_SERDES_PDOWN;
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else
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reg &= ~E6000SW_SERDES_PDOWN;
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e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV,
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E6000SW_SERDES_PCS_CTL1, reg);
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}
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static int
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e6000sw_attach(device_t dev)
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{
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bool sgmii;
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e6000sw_softc_t *sc;
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phandle_t child, ports;
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int err, port;
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@ -436,28 +477,47 @@ e6000sw_attach(device_t dev)
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if (e6000sw_is_fixedport(sc, port)) {
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/* Link must be down to change speed force value. */
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reg = e6000sw_readreg(sc, REG_PORT(port), PSC_CONTROL);
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reg = e6000sw_readreg(sc, REG_PORT(sc, port),
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PSC_CONTROL);
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reg &= ~PSC_CONTROL_LINK_UP;
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reg |= PSC_CONTROL_FORCED_LINK;
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e6000sw_writereg(sc, REG_PORT(port), PSC_CONTROL, reg);
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e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL,
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reg);
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/*
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* Force speed, full-duplex, EEE off and flow-control
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* on.
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*/
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reg &= ~(PSC_CONTROL_SPD2500 | PSC_CONTROL_ALT_SPD |
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PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON |
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PSC_CONTROL_FORCED_EEE);
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if (e6000sw_is_fixed25port(sc, port))
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reg |= PSC_CONTROL_SPD2500;
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else
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reg |= PSC_CONTROL_SPD1000;
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if (MVSWITCH(sc, MV88E6190) &&
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e6000sw_is_fixed25port(sc, port))
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reg |= PSC_CONTROL_ALT_SPD;
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reg |= PSC_CONTROL_FORCED_DPX | PSC_CONTROL_FULLDPX |
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PSC_CONTROL_FORCED_LINK | PSC_CONTROL_LINK_UP |
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PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON |
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PSC_CONTROL_FORCED_SPD;
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if (MVSWITCH(sc, MV88E6141) || MVSWITCH(sc, MV88E6341))
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reg |= PSC_CONTROL_FORCED_EEE;
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e6000sw_writereg(sc, REG_PORT(port), PSC_CONTROL, reg);
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if (!MVSWITCH(sc, MV88E6190))
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reg |= PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON;
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if (MVSWITCH(sc, MV88E6141) ||
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MVSWITCH(sc, MV88E6341) ||
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MVSWITCH(sc, MV88E6190))
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reg |= PSC_CONTROL_FORCED_EEE;
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e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL,
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reg);
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/* Power on the SERDES interfaces. */
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if (MVSWITCH(sc, MV88E6190) &&
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(port == 9 || port == 10)) {
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if (e6000sw_is_fixed25port(sc, port))
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sgmii = false;
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else
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sgmii = true;
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e6000sw_serdes_power(sc->dev, port, sgmii);
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}
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}
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/* Don't attach miibus at CPU/fixed ports */
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@ -510,6 +570,79 @@ e6000sw_waitready(e6000sw_softc_t *sc, uint32_t phy, uint32_t reg,
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return (1);
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}
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/* XMDIO/Clause 45 access. */
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static int
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e6000sw_read_xmdio(device_t dev, int phy, int devaddr, int devreg)
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{
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e6000sw_softc_t *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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E6000SW_LOCK_ASSERT(sc, SA_XLOCKED);
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if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) {
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device_printf(dev, "Timeout while waiting for switch\n");
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return (ETIMEDOUT);
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}
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reg = devaddr & SMI_CMD_REG_ADDR_MASK;
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reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK;
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/* Load C45 register address. */
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg);
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG,
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reg | SMI_CMD_OP_C45_ADDR);
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if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) {
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device_printf(dev, "Timeout while waiting for switch\n");
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return (ETIMEDOUT);
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}
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/* Start C45 read operation. */
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG,
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reg | SMI_CMD_OP_C45_READ);
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if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) {
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device_printf(dev, "Timeout while waiting for switch\n");
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return (ETIMEDOUT);
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}
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/* Read C45 data. */
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reg = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG);
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return (reg & PHY_DATA_MASK);
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}
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static int
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e6000sw_write_xmdio(device_t dev, int phy, int devaddr, int devreg, int val)
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{
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e6000sw_softc_t *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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E6000SW_LOCK_ASSERT(sc, SA_XLOCKED);
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if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) {
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device_printf(dev, "Timeout while waiting for switch\n");
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return (ETIMEDOUT);
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}
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reg = devaddr & SMI_CMD_REG_ADDR_MASK;
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reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK;
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/* Load C45 register address. */
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg);
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG,
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reg | SMI_CMD_OP_C45_ADDR);
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if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) {
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device_printf(dev, "Timeout while waiting for switch\n");
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return (ETIMEDOUT);
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}
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/* Load data and start the C45 write operation. */
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg);
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e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG,
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reg | SMI_CMD_OP_C45_WRITE);
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return (0);
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}
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/*
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* PHY registers are paged. Put page index in reg 22 (accessible from every
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* page), then access specific register.
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@ -670,7 +803,7 @@ e6000sw_getport(device_t dev, etherswitch_port_t *p)
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e6000sw_get_pvid(sc, p->es_port, &p->es_pvid);
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/* Port flags. */
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reg = e6000sw_readreg(sc, REG_PORT(p->es_port), PORT_CONTROL2);
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reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2);
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if (reg & PORT_CONTROL2_DISC_TAGGED)
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p->es_flags |= ETHERSWITCH_PORT_DROPTAGGED;
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if (reg & PORT_CONTROL2_DISC_UNTAGGED)
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@ -717,7 +850,7 @@ e6000sw_setport(device_t dev, etherswitch_port_t *p)
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return (0);
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/* Port flags. */
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reg = e6000sw_readreg(sc, REG_PORT(p->es_port), PORT_CONTROL2);
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reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2);
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if (p->es_flags & ETHERSWITCH_PORT_DROPTAGGED)
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reg |= PORT_CONTROL2_DISC_TAGGED;
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else
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@ -726,7 +859,7 @@ e6000sw_setport(device_t dev, etherswitch_port_t *p)
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reg |= PORT_CONTROL2_DISC_UNTAGGED;
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else
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reg &= ~PORT_CONTROL2_DISC_UNTAGGED;
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e6000sw_writereg(sc, REG_PORT(p->es_port), PORT_CONTROL2, reg);
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e6000sw_writereg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2, reg);
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err = 0;
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E6000SW_LOCK(sc);
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@ -748,15 +881,15 @@ e6000sw_port_vlan_assign(e6000sw_softc_t *sc, int port, uint32_t fid,
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{
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uint32_t reg;
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reg = e6000sw_readreg(sc, REG_PORT(port), PORT_VLAN_MAP);
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reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP);
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reg &= ~(PORT_MASK(sc) | PORT_VLAN_MAP_FID_MASK);
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reg |= members & PORT_MASK(sc) & ~(1 << port);
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reg |= (fid << PORT_VLAN_MAP_FID) & PORT_VLAN_MAP_FID_MASK;
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e6000sw_writereg(sc, REG_PORT(port), PORT_VLAN_MAP, reg);
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reg = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL1);
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e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VLAN_MAP, reg);
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reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1);
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reg &= ~PORT_CONTROL1_FID_MASK;
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reg |= (fid >> 4) & PORT_CONTROL1_FID_MASK;
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e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL1, reg);
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e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL1, reg);
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}
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static int
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@ -767,8 +900,8 @@ e6000sw_init_vlan(struct e6000sw_softc *sc)
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/* Disable all ports */
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for (port = 0; port < sc->num_ports; port++) {
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ret = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL);
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e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL,
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ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL);
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e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL,
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(ret & ~PORT_CONTROL_ENABLE));
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}
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@ -777,23 +910,23 @@ e6000sw_init_vlan(struct e6000sw_softc *sc)
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for (port = 0; port < sc->num_ports; port++) {
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/* Reset the egress and frame mode. */
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ret = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL);
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ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL);
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ret &= ~(PORT_CONTROL_EGRESS | PORT_CONTROL_FRAME);
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e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL, ret);
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e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, ret);
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/* Set the the 802.1q mode. */
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ret = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL2);
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ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL2);
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ret &= ~PORT_CONTROL2_DOT1Q;
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if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q)
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ret |= PORT_CONTROL2_DOT1Q;
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e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL2, ret);
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e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL2, ret);
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}
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for (port = 0; port < sc->num_ports; port++) {
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if (!e6000sw_is_portenabled(sc, port))
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continue;
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ret = e6000sw_readreg(sc, REG_PORT(port), PORT_VID);
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ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID);
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/* Set port priority */
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ret &= ~PORT_VID_PRIORITY_MASK;
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@ -804,7 +937,7 @@ e6000sw_init_vlan(struct e6000sw_softc *sc)
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ret |= 1;
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else
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ret |= (port + 1);
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e6000sw_writereg(sc, REG_PORT(port), PORT_VID, ret);
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e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, ret);
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}
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/* Assign the member ports to each origin port. */
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@ -835,8 +968,8 @@ e6000sw_init_vlan(struct e6000sw_softc *sc)
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for (port = 0; port < sc->num_ports; port++) {
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if (!e6000sw_is_portenabled(sc, port))
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continue;
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ret = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL);
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e6000sw_writereg(sc, REG_PORT(port), PORT_CONTROL,
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ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL);
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e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL,
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(ret | PORT_CONTROL_ENABLE));
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}
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@ -873,9 +1006,11 @@ e6000sw_set_vlan_mode(struct e6000sw_softc *sc, uint32_t mode)
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static int
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e6000sw_readreg_wrapper(device_t dev, int addr_reg)
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{
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e6000sw_softc_t *sc;
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sc = device_get_softc(dev);
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if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) ||
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(addr_reg < (REG_PORT(0) * 32))) {
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(addr_reg < (REG_PORT(sc, 0) * 32))) {
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device_printf(dev, "Wrong register address.\n");
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return (EINVAL);
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}
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@ -887,9 +1022,11 @@ e6000sw_readreg_wrapper(device_t dev, int addr_reg)
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static int
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e6000sw_writereg_wrapper(device_t dev, int addr_reg, int val)
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{
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e6000sw_softc_t *sc;
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sc = device_get_softc(dev);
|
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if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) ||
|
||||
(addr_reg < (REG_PORT(0) * 32))) {
|
||||
(addr_reg < (REG_PORT(sc, 0) * 32))) {
|
||||
device_printf(dev, "Wrong register address.\n");
|
||||
return (EINVAL);
|
||||
}
|
||||
@ -1049,11 +1186,11 @@ e6000sw_get_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg)
|
||||
return (0);
|
||||
}
|
||||
|
||||
reg = e6000sw_readreg(sc, REG_PORT(port), PORT_VLAN_MAP);
|
||||
reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP);
|
||||
vg->es_untagged_ports = vg->es_member_ports = reg & PORT_MASK(sc);
|
||||
vg->es_vid = port | ETHERSWITCH_VID_VALID;
|
||||
vg->es_fid = (reg & PORT_VLAN_MAP_FID_MASK) >> PORT_VLAN_MAP_FID;
|
||||
reg = e6000sw_readreg(sc, REG_PORT(port), PORT_CONTROL1);
|
||||
reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1);
|
||||
vg->es_fid |= (reg & PORT_CONTROL1_FID_MASK) << 4;
|
||||
|
||||
return (0);
|
||||
@ -1268,10 +1405,10 @@ e6000sw_set_pvid(e6000sw_softc_t *sc, int port, int pvid)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = e6000sw_readreg(sc, REG_PORT(port), PORT_VID);
|
||||
reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID);
|
||||
reg &= ~PORT_VID_DEF_VID_MASK;
|
||||
reg |= (pvid & PORT_VID_DEF_VID_MASK);
|
||||
e6000sw_writereg(sc, REG_PORT(port), PORT_VID, reg);
|
||||
e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, reg);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
@ -1281,7 +1418,7 @@ e6000sw_get_pvid(e6000sw_softc_t *sc, int port, int *pvid)
|
||||
if (pvid == NULL)
|
||||
return (ENXIO);
|
||||
|
||||
*pvid = e6000sw_readreg(sc, REG_PORT(port), PORT_VID) &
|
||||
*pvid = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID) &
|
||||
PORT_VID_DEF_VID_MASK;
|
||||
|
||||
return (0);
|
||||
@ -1346,7 +1483,7 @@ e6000sw_tick(void *arg)
|
||||
if (mii == NULL)
|
||||
continue;
|
||||
|
||||
portstatus = e6000sw_readreg(sc, REG_PORT(port),
|
||||
portstatus = e6000sw_readreg(sc, REG_PORT(sc, port),
|
||||
PORT_STATUS);
|
||||
|
||||
e6000sw_update_ifmedia(portstatus,
|
||||
|
||||
@ -48,6 +48,7 @@ struct atu_opt {
|
||||
#define MV88E6352 0x3520
|
||||
#define MV88E6172 0x1720
|
||||
#define MV88E6176 0x1760
|
||||
#define MV88E6190 0x1900
|
||||
|
||||
#define MVSWITCH(_sc, id) ((_sc)->swid == (id))
|
||||
#define MVSWITCH_MULTICHIP(_sc) ((_sc)->sw_addr != 0)
|
||||
@ -57,7 +58,7 @@ struct atu_opt {
|
||||
*/
|
||||
#define REG_GLOBAL 0x1b
|
||||
#define REG_GLOBAL2 0x1c
|
||||
#define REG_PORT(p) (0x10 + (p))
|
||||
#define REG_PORT(_sc, p) ((MVSWITCH((_sc), MV88E6190) ? 0 : 0x10) + (p))
|
||||
|
||||
#define REG_NUM_MAX 31
|
||||
|
||||
@ -139,13 +140,13 @@ struct atu_opt {
|
||||
#define VTU_DATA 7
|
||||
#define VTU_DATA2 8
|
||||
|
||||
#define VTU_FID_MASK(_sc) 0xff
|
||||
#define VTU_FID_MASK(_sc) (MVSWITCH((_sc), MV88E6190) ? 0xfff : 0xff)
|
||||
#define VTU_FID_POLICY (1 << 12)
|
||||
#define VTU_PORT_UNMODIFIED 0
|
||||
#define VTU_PORT_UNTAGGED 1
|
||||
#define VTU_PORT_TAGGED 2
|
||||
#define VTU_PORT_DISCARD 3
|
||||
#define VTU_PPREG(_sc) 4
|
||||
#define VTU_PPREG(_sc) (MVSWITCH((_sc), MV88E6190) ? 8 : 4)
|
||||
#define VTU_PORT(_sc, p) (((p) % VTU_PPREG(_sc)) * (16 / VTU_PPREG(_sc)))
|
||||
#define VTU_PORT_MASK 3
|
||||
#define VTU_BUSY (1 << 15)
|
||||
@ -175,7 +176,7 @@ struct atu_opt {
|
||||
#define ATU_MAC_ADDR45 15
|
||||
|
||||
#define ATU_DATA_LAG (1 << 15)
|
||||
#define ATU_PORT_MASK(_sc) 0xff0
|
||||
#define ATU_PORT_MASK(_sc) (MVSWITCH((_sc), MV88E6190) ? 0xfff0 : 0xff0)
|
||||
#define ATU_PORT_SHIFT 4
|
||||
#define ATU_LAG_MASK 0xf0
|
||||
#define ATU_LAG_SHIFT 4
|
||||
|
||||
Loading…
Reference in New Issue
Block a user