Implement interface to create SR-IOV Virtual Functions
Implement the interace to create SR-IOV Virtual Functions (VFs). When a driver registers that they support SR-IOV by calling pci_setup_iov(), the SR-IOV code creates a new node in /dev/iov for that device. An ioctl can be invoked on that device to create VFs and have the driver initialize them. At this point, allocating memory I/O windows (BARs) is not supported. Differential Revision: https://reviews.freebsd.org/D76 Reviewed by: jhb MFC after: 1 month Sponsored by: Sandvine Inc.
This commit is contained in:
parent
e1de57232c
commit
9bfb1e36d9
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=279447
@ -97,6 +97,7 @@ device cpufreq
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device acpi
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options ACPI_DMAR
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device pci
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options PCI_IOV # PCI SR-IOV support
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# Floppy drives
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device fdc
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@ -2031,6 +2031,7 @@ dev/pci/ignore_pci.c optional pci
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dev/pci/isa_pci.c optional pci isa
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dev/pci/pci.c optional pci
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dev/pci/pci_if.m standard
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dev/pci/pci_iov.c optional pci pci_iov
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dev/pci/pci_pci.c optional pci
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dev/pci/pci_subr.c optional pci
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dev/pci/pci_user.c optional pci
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@ -173,6 +173,7 @@ NO_SYSCTL_DESCR opt_global.h
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NSWBUF_MIN opt_swap.h
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MBUF_PACKET_ZONE_DISABLE opt_global.h
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PANIC_REBOOT_WAIT_TIME opt_panic.h
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PCI_IOV opt_global.h
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PPC_DEBUG opt_ppc.h
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PPC_PROBE_CHIPSET opt_ppc.h
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PPS_SYNC opt_ntp.h
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@ -84,6 +84,11 @@ static int acpi_pci_set_powerstate_method(device_t dev, device_t child,
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static void acpi_pci_update_device(ACPI_HANDLE handle, device_t pci_child);
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static bus_dma_tag_t acpi_pci_get_dma_tag(device_t bus, device_t child);
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#ifdef PCI_IOV
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static device_t acpi_pci_create_iov_child(device_t bus, device_t pf,
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uint16_t rid, uint16_t vid, uint16_t did);
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#endif
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static device_method_t acpi_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, acpi_pci_probe),
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@ -98,6 +103,9 @@ static device_method_t acpi_pci_methods[] = {
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/* PCI interface */
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DEVMETHOD(pci_set_powerstate, acpi_pci_set_powerstate_method),
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#ifdef PCI_IOV
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DEVMETHOD(pci_create_iov_child, acpi_pci_create_iov_child),
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#endif
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DEVMETHOD_END
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};
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@ -345,3 +353,23 @@ acpi_pci_get_dma_tag(device_t bus, device_t child)
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return (pci_get_dma_tag(bus, child));
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}
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#endif
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#ifdef PCI_IOV
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static device_t
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acpi_pci_create_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid,
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uint16_t did)
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{
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struct acpi_pci_devinfo *dinfo;
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device_t vf;
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vf = pci_add_iov_child(bus, pf, sizeof(struct acpi_pci_devinfo), rid,
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vid, did);
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if (vf == NULL)
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return (NULL);
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dinfo = device_get_ivars(vf);
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dinfo->ap_handle = NULL;
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return (vf);
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}
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#endif
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@ -189,6 +189,11 @@ static device_method_t pci_methods[] = {
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DEVMETHOD(pci_msix_count, pci_msix_count_method),
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DEVMETHOD(pci_get_rid, pci_get_rid_method),
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DEVMETHOD(pci_child_added, pci_child_added_method),
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#ifdef PCI_IOV
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DEVMETHOD(pci_iov_attach, pci_iov_attach_method),
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DEVMETHOD(pci_iov_detach, pci_iov_detach_method),
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DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method),
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#endif
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DEVMETHOD_END
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};
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@ -643,6 +648,9 @@ pci_fill_devinfo(device_t pcib, int d, int b, int s, int f, uint16_t vid,
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cfg->hdrtype &= ~PCIM_MFDEV;
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STAILQ_INIT(&cfg->maps);
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cfg->devinfo_size = size;
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cfg->iov = NULL;
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pci_fixancient(cfg);
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pci_hdrtypedata(pcib, b, s, f, cfg);
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@ -3546,6 +3554,51 @@ pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
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#undef REG
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}
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#ifdef PCI_IOV
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device_t
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pci_add_iov_child(device_t bus, device_t pf, size_t size, uint16_t rid,
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uint16_t vid, uint16_t did)
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{
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struct pci_devinfo *pf_dinfo, *vf_dinfo;
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device_t pcib;
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int busno, slot, func;
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pf_dinfo = device_get_ivars(pf);
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/*
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* Do a sanity check that we have been passed the correct size. If this
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* test fails then likely the pci subclass hasn't implemented the
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* pci_create_iov_child method like it's supposed it.
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*/
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if (size != pf_dinfo->cfg.devinfo_size) {
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device_printf(pf,
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"PCI subclass does not properly implement PCI_IOV\n");
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return (NULL);
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}
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pcib = device_get_parent(bus);
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PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func);
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vf_dinfo = pci_fill_devinfo(pcib, pci_get_domain(pcib), busno, slot, func,
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vid, did, size);
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vf_dinfo->cfg.flags |= PCICFG_VF;
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pci_add_child(bus, vf_dinfo);
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return (vf_dinfo->cfg.dev);
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}
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device_t
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pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid,
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uint16_t vid, uint16_t did)
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{
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return (pci_add_iov_child(bus, pf, sizeof(struct pci_devinfo), rid, vid,
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did));
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}
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#endif
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void
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pci_add_child(device_t bus, struct pci_devinfo *dinfo)
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{
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@ -36,6 +36,14 @@ CODE {
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{
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return (0);
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}
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static device_t
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null_create_iov_child(device_t bus, device_t pf, uint16_t rid,
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uint16_t vid, uint16_t did)
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{
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device_printf(bus, "PCI_IOV not implemented on this bus.\n");
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return (NULL);
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}
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};
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@ -189,3 +197,36 @@ METHOD void child_added {
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device_t dev;
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device_t child;
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};
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METHOD int iov_attach {
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device_t dev;
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device_t child;
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};
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METHOD int iov_detach {
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device_t dev;
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device_t child;
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};
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METHOD int init_iov {
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device_t dev;
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uint16_t num_vfs;
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};
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METHOD void uninit_iov {
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device_t dev;
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};
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METHOD int add_vf {
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device_t dev;
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uint16_t vfnum;
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};
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METHOD device_t create_iov_child {
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device_t bus;
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device_t pf;
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uint16_t rid;
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uint16_t vid;
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uint16_t did;
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} DEFAULT null_create_iov_child;
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385
sys/dev/pci/pci_iov.c
Normal file
385
sys/dev/pci/pci_iov.c
Normal file
@ -0,0 +1,385 @@
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/*-
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* Copyright (c) 2013-2015 Sandvine Inc. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_bus.h"
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/fcntl.h>
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#include <sys/ioccom.h>
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#include <sys/iov.h>
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#include <sys/linker.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/pciio.h>
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#include <sys/queue.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pci_private.h>
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#include <dev/pci/pci_iov_private.h>
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#include "pci_if.h"
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#include "pcib_if.h"
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static MALLOC_DEFINE(M_SRIOV, "sr_iov", "PCI SR-IOV allocations");
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static d_ioctl_t pci_iov_ioctl;
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static struct cdevsw iov_cdevsw = {
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.d_version = D_VERSION,
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.d_name = "iov",
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.d_ioctl = pci_iov_ioctl
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};
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#define IOV_READ(d, r, w) \
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pci_read_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, w)
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#define IOV_WRITE(d, r, v, w) \
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pci_write_config((d)->cfg.dev, (d)->cfg.iov->iov_pos + r, v, w)
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int
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pci_iov_attach_method(device_t bus, device_t dev)
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{
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device_t pcib;
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struct pci_devinfo *dinfo;
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struct pcicfg_iov *iov;
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uint32_t version;
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int error;
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int iov_pos;
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dinfo = device_get_ivars(dev);
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pcib = device_get_parent(bus);
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error = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos);
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if (error != 0)
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return (error);
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version = pci_read_config(dev, iov_pos, 4);
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if (PCI_EXTCAP_VER(version) != 1) {
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if (bootverbose)
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device_printf(dev,
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"Unsupported version of SR-IOV (%d) detected\n",
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PCI_EXTCAP_VER(version));
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return (ENXIO);
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}
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iov = malloc(sizeof(*dinfo->cfg.iov), M_SRIOV, M_WAITOK | M_ZERO);
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mtx_lock(&Giant);
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if (dinfo->cfg.iov != NULL) {
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error = EBUSY;
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goto cleanup;
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}
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iov->iov_pos = iov_pos;
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iov->iov_cdev = make_dev(&iov_cdevsw, device_get_unit(dev),
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UID_ROOT, GID_WHEEL, 0600, "iov/%s", device_get_nameunit(dev));
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if (iov->iov_cdev == NULL) {
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error = ENOMEM;
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goto cleanup;
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}
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dinfo->cfg.iov = iov;
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iov->iov_cdev->si_drv1 = dinfo;
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mtx_unlock(&Giant);
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return (0);
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cleanup:
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free(iov, M_SRIOV);
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mtx_unlock(&Giant);
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return (error);
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}
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int
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pci_iov_detach_method(device_t bus, device_t dev)
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{
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struct pci_devinfo *dinfo;
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struct pcicfg_iov *iov;
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mtx_lock(&Giant);
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dinfo = device_get_ivars(dev);
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iov = dinfo->cfg.iov;
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if (iov == NULL) {
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mtx_unlock(&Giant);
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return (0);
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}
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if (iov->iov_num_vfs != 0) {
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mtx_unlock(&Giant);
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return (EBUSY);
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}
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dinfo->cfg.iov = NULL;
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if (iov->iov_cdev) {
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destroy_dev(iov->iov_cdev);
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iov->iov_cdev = NULL;
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}
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free(iov, M_SRIOV);
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mtx_unlock(&Giant);
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return (0);
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}
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/*
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* Set the ARI_EN bit in the lowest-numbered PCI function with the SR-IOV
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* capability. This bit is only writeable on the lowest-numbered PF but
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* affects all PFs on the device.
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*/
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static int
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pci_iov_set_ari(device_t bus)
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{
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device_t lowest;
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device_t *devlist;
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int i, error, devcount, lowest_func, lowest_pos, iov_pos, dev_func;
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uint16_t iov_ctl;
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/* If ARI is disabled on the downstream port there is nothing to do. */
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if (!PCIB_ARI_ENABLED(device_get_parent(bus)))
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return (0);
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error = device_get_children(bus, &devlist, &devcount);
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if (error != 0)
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return (error);
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lowest = NULL;
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for (i = 0; i < devcount; i++) {
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if (pci_find_extcap(devlist[i], PCIZ_SRIOV, &iov_pos) == 0) {
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dev_func = pci_get_function(devlist[i]);
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if (lowest == NULL || dev_func < lowest_func) {
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lowest = devlist[i];
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lowest_func = dev_func;
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lowest_pos = iov_pos;
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}
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}
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}
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/*
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* If we called this function some device must have the SR-IOV
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* capability.
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*/
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KASSERT(lowest != NULL,
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("Could not find child of %s with SR-IOV capability",
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device_get_nameunit(bus)));
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iov_ctl = pci_read_config(lowest, iov_pos + PCIR_SRIOV_CTL, 2);
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iov_ctl |= PCIM_SRIOV_ARI_EN;
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pci_write_config(lowest, iov_pos + PCIR_SRIOV_CTL, iov_ctl, 2);
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free(devlist, M_TEMP);
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return (0);
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}
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static int
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pci_iov_config_page_size(struct pci_devinfo *dinfo)
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{
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uint32_t page_cap, page_size;
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page_cap = IOV_READ(dinfo, PCIR_SRIOV_PAGE_CAP, 4);
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/*
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* If the system page size is less than the smallest SR-IOV page size
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* then round up to the smallest SR-IOV page size.
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*/
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if (PAGE_SHIFT < PCI_SRIOV_BASE_PAGE_SHIFT)
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page_size = (1 << 0);
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else
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page_size = (1 << (PAGE_SHIFT - PCI_SRIOV_BASE_PAGE_SHIFT));
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/* Check that the device supports the system page size. */
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if (!(page_size & page_cap))
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return (ENXIO);
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IOV_WRITE(dinfo, PCIR_SRIOV_PAGE_SIZE, page_size, 4);
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return (0);
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}
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static void
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pci_iov_enumerate_vfs(struct pci_devinfo *dinfo, const char *driver,
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uint16_t first_rid, uint16_t rid_stride)
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{
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device_t bus, dev, vf;
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struct pcicfg_iov *iov;
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struct pci_devinfo *vfinfo;
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size_t size;
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int i, error;
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uint16_t vid, did, next_rid;
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iov = dinfo->cfg.iov;
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dev = dinfo->cfg.dev;
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bus = device_get_parent(dev);
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size = dinfo->cfg.devinfo_size;
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next_rid = first_rid;
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vid = pci_get_vendor(dev);
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did = IOV_READ(dinfo, PCIR_SRIOV_VF_DID, 2);
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for (i = 0; i < iov->iov_num_vfs; i++, next_rid += rid_stride) {
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vf = PCI_CREATE_IOV_CHILD(bus, dev, next_rid, vid, did);
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if (vf == NULL)
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break;
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||||
vfinfo = device_get_ivars(vf);
|
||||
|
||||
vfinfo->cfg.iov = iov;
|
||||
vfinfo->cfg.vf.index = i;
|
||||
|
||||
error = PCI_ADD_VF(dev, i);
|
||||
if (error != 0) {
|
||||
device_printf(dev, "Failed to add VF %d\n", i);
|
||||
pci_delete_child(bus, vf);
|
||||
}
|
||||
}
|
||||
|
||||
bus_generic_attach(bus);
|
||||
}
|
||||
|
||||
static int
|
||||
pci_iov_config(struct cdev *cdev, struct pci_iov_arg *arg)
|
||||
{
|
||||
device_t bus, dev;
|
||||
const char *driver;
|
||||
struct pci_devinfo *dinfo;
|
||||
struct pcicfg_iov *iov;
|
||||
int error;
|
||||
uint16_t rid_off, rid_stride;
|
||||
uint16_t first_rid, last_rid;
|
||||
uint16_t iov_ctl;
|
||||
uint16_t total_vfs;
|
||||
int iov_inited;
|
||||
|
||||
mtx_lock(&Giant);
|
||||
dinfo = cdev->si_drv1;
|
||||
iov = dinfo->cfg.iov;
|
||||
dev = dinfo->cfg.dev;
|
||||
bus = device_get_parent(dev);
|
||||
iov_inited = 0;
|
||||
|
||||
if (iov->iov_num_vfs != 0) {
|
||||
mtx_unlock(&Giant);
|
||||
return (EBUSY);
|
||||
}
|
||||
|
||||
total_vfs = IOV_READ(dinfo, PCIR_SRIOV_TOTAL_VFS, 2);
|
||||
|
||||
if (arg->num_vfs > total_vfs) {
|
||||
error = EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* If we are creating passthrough devices then force the ppt driver to
|
||||
* attach to prevent a VF driver from claming the VFs.
|
||||
*/
|
||||
if (arg->passthrough)
|
||||
driver = "ppt";
|
||||
else
|
||||
driver = NULL;
|
||||
|
||||
error = pci_iov_config_page_size(dinfo);
|
||||
if (error != 0)
|
||||
goto out;
|
||||
|
||||
error = pci_iov_set_ari(bus);
|
||||
if (error != 0)
|
||||
goto out;
|
||||
|
||||
error = PCI_INIT_IOV(dev, arg->num_vfs);
|
||||
|
||||
if (error != 0)
|
||||
goto out;
|
||||
|
||||
iov_inited = 1;
|
||||
IOV_WRITE(dinfo, PCIR_SRIOV_NUM_VFS, arg->num_vfs, 2);
|
||||
|
||||
rid_off = IOV_READ(dinfo, PCIR_SRIOV_VF_OFF, 2);
|
||||
rid_stride = IOV_READ(dinfo, PCIR_SRIOV_VF_STRIDE, 2);
|
||||
|
||||
first_rid = pci_get_rid(dev) + rid_off;
|
||||
last_rid = first_rid + (arg->num_vfs - 1) * rid_stride;
|
||||
|
||||
/* We don't yet support allocating extra bus numbers for VFs. */
|
||||
if (pci_get_bus(dev) != PCI_RID2BUS(last_rid)) {
|
||||
error = ENOSPC;
|
||||
goto out;
|
||||
}
|
||||
|
||||
iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
|
||||
iov_ctl &= ~(PCIM_SRIOV_VF_EN | PCIM_SRIOV_VF_MSE);
|
||||
IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
|
||||
|
||||
iov->iov_num_vfs = arg->num_vfs;
|
||||
|
||||
iov_ctl = IOV_READ(dinfo, PCIR_SRIOV_CTL, 2);
|
||||
iov_ctl |= PCIM_SRIOV_VF_EN;
|
||||
IOV_WRITE(dinfo, PCIR_SRIOV_CTL, iov_ctl, 2);
|
||||
|
||||
/* Per specification, we must wait 100ms before accessing VFs. */
|
||||
pause("iov", roundup(hz, 10));
|
||||
pci_iov_enumerate_vfs(dinfo, driver, first_rid, rid_stride);
|
||||
mtx_unlock(&Giant);
|
||||
|
||||
return (0);
|
||||
out:
|
||||
if (iov_inited)
|
||||
PCI_UNINIT_IOV(dev);
|
||||
iov->iov_num_vfs = 0;
|
||||
mtx_unlock(&Giant);
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
|
||||
struct thread *td)
|
||||
{
|
||||
|
||||
switch (cmd) {
|
||||
case IOV_CONFIG:
|
||||
return (pci_iov_config(dev, (struct pci_iov_arg *)data));
|
||||
default:
|
||||
return (EINVAL);
|
||||
}
|
||||
}
|
||||
|
40
sys/dev/pci/pci_iov_private.h
Normal file
40
sys/dev/pci/pci_iov_private.h
Normal file
@ -0,0 +1,40 @@
|
||||
/*-
|
||||
* Copyright (c) 2013-2015 Sandvine Inc. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _PCI_IOV_PRIVATE_H_
|
||||
#define _PCI_IOV_PRIVATE_H_
|
||||
|
||||
struct pcicfg_iov {
|
||||
struct cdev *iov_cdev;
|
||||
|
||||
int iov_pos;
|
||||
int iov_num_vfs;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
@ -51,6 +51,8 @@ extern int pci_do_power_suspend;
|
||||
void pci_add_children(device_t dev, int domain, int busno,
|
||||
size_t dinfo_size);
|
||||
void pci_add_child(device_t bus, struct pci_devinfo *dinfo);
|
||||
device_t pci_add_iov_child(device_t bus, device_t pf, size_t dinfo_size,
|
||||
uint16_t rid, uint16_t vid, uint16_t did);
|
||||
void pci_add_resources(device_t bus, device_t dev, int force,
|
||||
uint32_t prefetchmask);
|
||||
int pci_attach_common(device_t dev);
|
||||
@ -150,4 +152,10 @@ struct resource *pci_alloc_multi_resource(device_t dev, device_t child,
|
||||
int type, int *rid, u_long start, u_long end, u_long count,
|
||||
u_long num, u_int flags);
|
||||
|
||||
int pci_iov_attach_method(device_t bus, device_t dev);
|
||||
int pci_iov_detach_method(device_t bus, device_t dev);
|
||||
|
||||
device_t pci_create_iov_child_method(device_t bus, device_t pf,
|
||||
uint16_t rid, uint16_t vid, uint16_t did);
|
||||
|
||||
#endif /* _PCI_PRIVATE_H_ */
|
||||
|
@ -924,3 +924,21 @@
|
||||
#define PCIR_SERIAL_LOW 0x04
|
||||
#define PCIR_SERIAL_HIGH 0x08
|
||||
|
||||
/* SR-IOV definitions */
|
||||
#define PCIR_SRIOV_CTL 0x08
|
||||
#define PCIM_SRIOV_VF_EN 0x01
|
||||
#define PCIM_SRIOV_VF_MSE 0x08 /* Memory space enable. */
|
||||
#define PCIM_SRIOV_ARI_EN 0x10
|
||||
#define PCIR_SRIOV_TOTAL_VFS 0x0E
|
||||
#define PCIR_SRIOV_NUM_VFS 0x10
|
||||
#define PCIR_SRIOV_VF_OFF 0x14
|
||||
#define PCIR_SRIOV_VF_STRIDE 0x16
|
||||
#define PCIR_SRIOV_VF_DID 0x1A
|
||||
#define PCIR_SRIOV_PAGE_CAP 0x1C
|
||||
#define PCIR_SRIOV_PAGE_SIZE 0x20
|
||||
|
||||
#define PCI_SRIOV_BASE_PAGE_SHIFT 12
|
||||
|
||||
#define PCIR_SRIOV_BARS 0x24
|
||||
#define PCIR_SRIOV_BAR(x) (PCIR_SRIOV_BARS + (x) * 4)
|
||||
|
||||
|
@ -143,6 +143,12 @@ struct pcicfg_pcix {
|
||||
uint8_t pcix_location; /* Offset of PCI-X capability registers. */
|
||||
};
|
||||
|
||||
struct pcicfg_vf {
|
||||
int index;
|
||||
};
|
||||
|
||||
#define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */
|
||||
|
||||
/* config header information common to all header types */
|
||||
typedef struct pcicfg {
|
||||
struct device *dev; /* device which owns this */
|
||||
@ -179,6 +185,9 @@ typedef struct pcicfg {
|
||||
uint8_t slot; /* config space slot address */
|
||||
uint8_t func; /* config space function number */
|
||||
|
||||
uint32_t flags; /* flags defined above */
|
||||
size_t devinfo_size; /* Size of devinfo for this bus type. */
|
||||
|
||||
struct pcicfg_pp pp; /* Power management */
|
||||
struct pcicfg_vpd vpd; /* Vital product data */
|
||||
struct pcicfg_msi msi; /* PCI MSI */
|
||||
@ -186,6 +195,8 @@ typedef struct pcicfg {
|
||||
struct pcicfg_ht ht; /* HyperTransport */
|
||||
struct pcicfg_pcie pcie; /* PCI Express */
|
||||
struct pcicfg_pcix pcix; /* PCI-X */
|
||||
struct pcicfg_iov *iov; /* SR-IOV */
|
||||
struct pcicfg_vf vf; /* SR-IOV Virtual Function */
|
||||
} pcicfgregs;
|
||||
|
||||
/* additional type 1 device config header information (PCI to PCI bridge) */
|
||||
@ -513,6 +524,18 @@ pci_child_added(device_t dev)
|
||||
return (PCI_CHILD_ADDED(device_get_parent(dev), dev));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_iov_attach(device_t dev)
|
||||
{
|
||||
return (PCI_IOV_ATTACH(device_get_parent(dev), dev));
|
||||
}
|
||||
|
||||
static __inline int
|
||||
pci_iov_detach(device_t dev)
|
||||
{
|
||||
return (PCI_IOV_DETACH(device_get_parent(dev), dev));
|
||||
}
|
||||
|
||||
device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
|
||||
device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
|
||||
device_t pci_find_device(uint16_t, uint16_t);
|
||||
|
@ -97,6 +97,7 @@ device cpufreq
|
||||
# Bus support.
|
||||
device acpi
|
||||
device pci
|
||||
options PCI_IOV # PCI SR-IOV support
|
||||
|
||||
# Floppy drives
|
||||
device fdc
|
||||
|
43
sys/sys/iov.h
Normal file
43
sys/sys/iov.h
Normal file
@ -0,0 +1,43 @@
|
||||
/*-
|
||||
* Copyright (c) 2013-2015 Sandvine Inc. All rights reserved.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _SYS_IOV_H_
|
||||
#define _SYS_IOV_H_
|
||||
|
||||
#include <sys/ioccom.h>
|
||||
|
||||
struct pci_iov_arg
|
||||
{
|
||||
int num_vfs;
|
||||
int passthrough;
|
||||
};
|
||||
|
||||
#define IOV_CONFIG _IOWR('p', 10, struct pci_iov_arg)
|
||||
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue
Block a user