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Load the transmit dma buffer at attach time as well. We don't need to

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load and unload it all the time since the buffer never changes. In
addition, we were loading it with a hardware spin lock held, which
makes the sleepable lock in busdma (for the bounce pages) trigger a
witness warning, as well as ipend being called with it held by uart,
which made it impossible to unload.

These differences don't matter with the v4 busdma implementation, but
they do with the v6 implementation since the latter likes to bounce
transactions more, and will always do so for Atmel's driver.

It's more efficient as well as being more correct.
This commit is contained in:
Warner Losh 2017-06-18 21:03:35 +00:00
parent 5342d6e0d2
commit 9cbc5bd323
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=320080
1 changed files with 5 additions and 9 deletions
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14
sys/arm/at91/uart_dev_at91usart.c
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@ -72,6 +72,7 @@ struct at91_usart_softc {
struct uart_softc base;
bus_dma_tag_t tx_tag;
bus_dmamap_t tx_map;
bus_addr_t tx_paddr;
uint32_t flags;
#define HAS_TIMEOUT 0x1
#define USE_RTS0_WORKAROUND 0x2
@ -472,6 +473,9 @@ at91_usart_bus_attach(struct uart_softc *sc)
err = bus_dmamap_create(atsc->tx_tag, 0, &atsc->tx_map);
if (err != 0)
goto errout;
if (bus_dmamap_load(atsc->tx_tag, atsc->tx_map, sc->sc_txbuf,
sc->sc_txfifosz, at91_getaddr, &atsc->tx_paddr, 0) != 0)
goto errout;
if (atsc->flags & HAS_TIMEOUT) {
/*
@ -547,29 +551,22 @@ at91_usart_bus_attach(struct uart_softc *sc)
static int
at91_usart_bus_transmit(struct uart_softc *sc)
{
bus_addr_t addr;
struct at91_usart_softc *atsc;
int err;
err = 0;
atsc = (struct at91_usart_softc *)sc;
uart_lock(sc->sc_hwmtx);
if (bus_dmamap_load(atsc->tx_tag, atsc->tx_map, sc->sc_txbuf,
sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0) {
err = EAGAIN;
goto errout;
}
bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
sc->sc_txbusy = 1;
/*
* Setup the PDC to transfer the data and interrupt us when it
* is done. We've already requested the interrupt.
*/
WR4(&sc->sc_bas, PDC_TPR, addr);
WR4(&sc->sc_bas, PDC_TPR, atsc->tx_paddr);
WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
errout:
uart_unlock(sc->sc_hwmtx);
return (err);
}
@ -666,7 +663,6 @@ at91_usart_bus_ipend(struct uart_softc *sc)
if (csr & USART_CSR_ENDTX) {
bus_dmamap_sync(atsc->tx_tag, atsc->tx_map,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(atsc->tx_tag, atsc->tx_map);
}
if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) {
if (sc->sc_txbusy)