style(9): single tab after #define.

This commit is contained in:
mdodd 2004-01-13 11:28:21 +00:00
parent 3d88fef4f3
commit a056cd2fc5
4 changed files with 66 additions and 66 deletions

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@ -48,15 +48,15 @@ __FBSDID("$FreeBSD$");
#include <dev/eisa/eisaconf.h>
#define IDA_EISA_IOPORT_START 0x0c88
#define IDA_EISA_IOPORT_LEN 0x0017
#define IDA_EISA_IOPORT_START 0x0c88
#define IDA_EISA_IOPORT_LEN 0x0017
#define IDA_EISA_IRQ_REG 0x0cc0
#define IDA_EISA_IRQ_MASK 0xf0
#define IDA_EISA_IRQ_15 0x80
#define IDA_EISA_IRQ_14 0x40
#define IDA_EISA_IRQ_11 0x10
#define IDA_EISA_IRQ_10 0x20
#define IDA_EISA_IRQ_REG 0x0cc0
#define IDA_EISA_IRQ_MASK 0xf0
#define IDA_EISA_IRQ_15 0x80
#define IDA_EISA_IRQ_14 0x40
#define IDA_EISA_IRQ_11 0x10
#define IDA_EISA_IRQ_10 0x20
static int
ida_v1_fifo_full(struct ida_softc *ida)

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@ -49,14 +49,14 @@ __FBSDID("$FreeBSD$");
#include <dev/ida/idavar.h>
#include <dev/ida/idareg.h>
#define IDA_PCI_MAX_DMA_ADDR 0xFFFFFFFF
#define IDA_PCI_MAX_DMA_COUNT 0xFFFFFFFF
#define IDA_PCI_MAX_DMA_ADDR 0xFFFFFFFF
#define IDA_PCI_MAX_DMA_COUNT 0xFFFFFFFF
#define IDA_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */
#define IDA_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */
#define IDA_DEVICEID_SMART 0xAE100E11
#define IDA_DEVICEID_DEC_SMART 0x00461011
#define IDA_DEVICEID_NCR_53C1510 0x00101000
#define IDA_DEVICEID_SMART 0xAE100E11
#define IDA_DEVICEID_DEC_SMART 0x00461011
#define IDA_DEVICEID_NCR_53C1510 0x00101000
static int
ida_v3_fifo_full(struct ida_softc *ida)

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@ -33,56 +33,56 @@
/*
* defines for older EISA controllers (IDA, IDA-2, IAES, SMART)
*/
#define R_EISA_INT_MASK 0x01
#define R_EISA_LOCAL_MASK 0x04
#define R_EISA_LOCAL_DOORBELL 0x05
#define R_EISA_SYSTEM_MASK 0x06
#define R_EISA_SYSTEM_DOORBELL 0x07
#define R_EISA_LIST_ADDR 0x08
#define R_EISA_LIST_LEN 0x0c
#define R_EISA_TAG 0x0f
#define R_EISA_COMPLETE_ADDR 0x10
#define R_EISA_LIST_STATUS 0x16
#define R_EISA_INT_MASK 0x01
#define R_EISA_LOCAL_MASK 0x04
#define R_EISA_LOCAL_DOORBELL 0x05
#define R_EISA_SYSTEM_MASK 0x06
#define R_EISA_SYSTEM_DOORBELL 0x07
#define R_EISA_LIST_ADDR 0x08
#define R_EISA_LIST_LEN 0x0c
#define R_EISA_TAG 0x0f
#define R_EISA_COMPLETE_ADDR 0x10
#define R_EISA_LIST_STATUS 0x16
#define EISA_CHANNEL_BUSY 0x01
#define EISA_CHANNEL_CLEAR 0x02
#define EISA_CHANNEL_BUSY 0x01
#define EISA_CHANNEL_CLEAR 0x02
/*
* board register offsets for SMART-2 controllers
*/
#define R_CMD_FIFO 0x04
#define R_DONE_FIFO 0x08
#define R_INT_MASK 0x0C
#define R_STATUS 0x10
#define R_INT_PENDING 0x14
#define R_CMD_FIFO 0x04
#define R_DONE_FIFO 0x08
#define R_INT_MASK 0x0C
#define R_STATUS 0x10
#define R_INT_PENDING 0x14
/*
* interrupt mask values for SMART series
*/
#define INT_DISABLE 0x00
#define INT_ENABLE 0x01
#define INT_DISABLE 0x00
#define INT_ENABLE 0x01
/*
* board offsets for the 42xx series
*/
#define R_42XX_STATUS 0x30
#define R_42XX_INT_MASK 0x34
#define R_42XX_REQUEST 0x40
#define R_42XX_REPLY 0x44
#define R_42XX_STATUS 0x30
#define R_42XX_INT_MASK 0x34
#define R_42XX_REQUEST 0x40
#define R_42XX_REPLY 0x44
/*
* interrupt values for 42xx series
*/
#define INT_ENABLE_42XX 0x00
#define INT_DISABLE_42XX 0x08
#define STATUS_42XX_INT_PENDING 0x08
#define INT_ENABLE_42XX 0x00
#define INT_DISABLE_42XX 0x08
#define STATUS_42XX_INT_PENDING 0x08
/*
* return status codes
*/
#define SOFT_ERROR 0x02
#define HARD_ERROR 0x04
#define CMD_REJECTED 0x14
#define SOFT_ERROR 0x02
#define HARD_ERROR 0x04
#define CMD_REJECTED 0x14
/*
* command types
@ -96,13 +96,13 @@
#define CMD_SENSE_DRV_LEDS 0x17
#define CMD_GET_LOG_DRV_EXT 0x18
#define CMD_GET_CTRL_INFO 0x11
#define CMD_READ 0x20
#define CMD_WRITE 0x30
#define CMD_WRITE_MEDIA 0x31
#define CMD_GET_CONFIG 0x50
#define CMD_SET_CONFIG 0x51
#define CMD_START_FIRMWARE 0x99 /* for integrated RAID */
#define CMD_FLUSH_CACHE 0xc2
#define CMD_READ 0x20
#define CMD_WRITE 0x30
#define CMD_WRITE_MEDIA 0x31
#define CMD_GET_CONFIG 0x50
#define CMD_SET_CONFIG 0x51
#define CMD_START_FIRMWARE 0x99 /* for integrated RAID */
#define CMD_FLUSH_CACHE 0xc2
/*
* command structures

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@ -31,20 +31,20 @@
*/
#ifndef _IDAVAR_H
#define _IDAVAR_H
#define _IDAVAR_H
#define ida_inb(ida, port) \
#define ida_inb(ida, port) \
bus_space_read_1((ida)->tag, (ida)->bsh, port)
#define ida_inw(ida, port) \
#define ida_inw(ida, port) \
bus_space_read_2((ida)->tag, (ida)->bsh, port)
#define ida_inl(ida, port) \
#define ida_inl(ida, port) \
bus_space_read_4((ida)->tag, (ida)->bsh, port)
#define ida_outb(ida, port, val) \
#define ida_outb(ida, port, val) \
bus_space_write_1((ida)->tag, (ida)->bsh, port, val)
#define ida_outw(ida, port, val) \
#define ida_outw(ida, port, val) \
bus_space_write_2((ida)->tag, (ida)->bsh, port, val)
#define ida_outl(ida, port, val) \
#define ida_outl(ida, port, val) \
bus_space_write_4((ida)->tag, (ida)->bsh, port, val)
struct ida_hdr {
@ -68,7 +68,7 @@ struct ida_sgb {
u_int32_t addr; /* physical address of block */
};
#define IDA_NSEG 32 /* maximum number of segments */
#define IDA_NSEG 32 /* maximum number of segments */
/*
* right now, this structure totals 276 bytes.
@ -87,11 +87,11 @@ typedef enum {
#define DMA_DATA_IN 0x0001
#define DMA_DATA_OUT 0x0002
#define IDA_COMMAND 0x0004
#define DMA_DATA_TRANSFER (DMA_DATA_IN | DMA_DATA_OUT)
#define IDA_COMMAND 0x0004
#define DMA_DATA_TRANSFER (DMA_DATA_IN | DMA_DATA_OUT)
#define IDA_QCB_MAX 256
#define IDA_CONTROLLER 0 /* drive "number" for controller */
#define IDA_QCB_MAX 256
#define IDA_CONTROLLER 0 /* drive "number" for controller */
struct ida_qcb {
struct ida_hardware_qcb *hwqcb;
@ -119,9 +119,9 @@ struct ida_access {
/*
* flags for the controller
*/
#define IDA_ATTACHED 0x01 /* attached */
#define IDA_FIRMWARE 0x02 /* firmware must be started */
#define IDA_INTERRUPTS 0x04 /* interrupts enabled */
#define IDA_ATTACHED 0x01 /* attached */
#define IDA_FIRMWARE 0x02 /* firmware must be started */
#define IDA_INTERRUPTS 0x04 /* interrupts enabled */
struct ida_softc {
device_t dev;
@ -164,7 +164,7 @@ struct ida_softc {
/*
* drive flags
*/
#define DRV_WRITEPROT 0x0001
#define DRV_WRITEPROT 0x0001
struct idad_softc {
device_t dev;