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Add tunable for XHCI port routing.

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MFC after:	1 week
This commit is contained in:
Hans Petter Selasky 2012-08-23 17:40:20 +00:00
parent 5ea2b3b5db
commit a0942dd7b2
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=239617
3 changed files with 19 additions and 5 deletions
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17
sys/dev/usb/controller/xhci.c
View File

@ -84,14 +84,17 @@ __FBSDID("$FreeBSD$");
((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
#ifdef USB_DEBUG
static int xhcidebug = 0;
static int xhcidebug;
static int xhciroute;
static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW,
&xhcidebug, 0, "Debug level");
SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW,
&xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
#endif
#define XHCI_INTR_ENDPT 1
@ -177,6 +180,16 @@ xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
}
#endif
uint32_t
xhci_get_port_route(void)
{
#ifdef USB_DEBUG
return (0xFFFFFFFFU ^ ((uint32_t)xhciroute));
#else
return (0xFFFFFFFFU);
#endif
}
static void
xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
{

1
sys/dev/usb/controller/xhci.h
View File

@ -499,6 +499,7 @@ struct xhci_softc {
/* prototypes */
uint32_t xhci_get_port_route(void);
usb_error_t xhci_halt_controller(struct xhci_softc *);
usb_error_t xhci_init(struct xhci_softc *, device_t);
usb_error_t xhci_start_controller(struct xhci_softc *);

6
sys/dev/usb/controller/xhci_pci.c
View File

@ -292,9 +292,9 @@ xhci_pci_take_controller(device_t self)
/* On Intel chipsets reroute ports from EHCI to XHCI controller. */
if (device_id == 0x1e318086 /* Panther Point */ ||
device_id == 0x8c318086 /* Lynx Point */) {
pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 0xffffffff, 4);
pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, 0xffffffff, 4);
uint32_t temp = xhci_get_port_route();
pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp, 4);
pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp, 4);
}
return (0);
}