[ar531x] [if_are] Fix if_are behaviour under high load traffic
* use ifqmaxlen * handle (inefficiently for now) meeting padding and alignment requirements for transmit mbufs. * change how TX ring handling is done Submitted by: Hiroki Mori <yamori813@yahoo.co.jp> Differential Revision: https://reviews.freebsd.org/D10557
This commit is contained in:
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52d3eee999
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a10430e0a3
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=317868
@ -302,9 +302,9 @@ are_attach(device_t dev)
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ifp->if_init = are_init;
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sc->are_if_flags = ifp->if_flags;
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/* XXX: add real size */
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IFQ_SET_MAXLEN(&ifp->if_snd, 9);
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ifp->if_snd.ifq_maxlen = 9;
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/* ifqmaxlen is sysctl value in net/if.c */
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IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
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ifp->if_snd.ifq_maxlen = ifqmaxlen;
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IFQ_SET_READY(&ifp->if_snd);
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/* Tell the upper layer(s) we support long frames. */
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@ -686,19 +686,92 @@ are_encap(struct are_softc *sc, struct mbuf **m_head)
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{
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struct are_txdesc *txd;
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struct are_desc *desc, *prev_desc;
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struct mbuf *m;
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bus_dma_segment_t txsegs[ARE_MAXFRAGS];
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uint32_t link_addr;
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int error, i, nsegs, prod, si, prev_prod;
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int txstat;
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int startcount;
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int padlen;
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startcount = sc->are_cdata.are_tx_cnt;
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ARE_LOCK_ASSERT(sc);
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/*
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* Some VIA Rhine wants packet buffers to be longword
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* aligned, but very often our mbufs aren't. Rather than
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* waste time trying to decide when to copy and when not
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* to copy, just do it all the time.
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*/
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m = m_defrag(*m_head, M_NOWAIT);
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if (m == NULL) {
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device_printf(sc->are_dev, "are_encap m_defrag error\n");
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m_freem(*m_head);
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*m_head = NULL;
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return (ENOBUFS);
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}
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*m_head = m;
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/*
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* The Rhine chip doesn't auto-pad, so we have to make
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* sure to pad short frames out to the minimum frame length
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* ourselves.
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*/
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if ((*m_head)->m_pkthdr.len < ARE_MIN_FRAMELEN) {
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m = *m_head;
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padlen = ARE_MIN_FRAMELEN - m->m_pkthdr.len;
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if (M_WRITABLE(m) == 0) {
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/* Get a writable copy. */
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m = m_dup(*m_head, M_NOWAIT);
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m_freem(*m_head);
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if (m == NULL) {
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device_printf(sc->are_dev, "are_encap m_dup error\n");
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*m_head = NULL;
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return (ENOBUFS);
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}
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*m_head = m;
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}
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if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
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m = m_defrag(m, M_NOWAIT);
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if (m == NULL) {
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device_printf(sc->are_dev, "are_encap m_defrag error\n");
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m_freem(*m_head);
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*m_head = NULL;
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return (ENOBUFS);
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}
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}
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/*
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* Manually pad short frames, and zero the pad space
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* to avoid leaking data.
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*/
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bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
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m->m_pkthdr.len += padlen;
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m->m_len = m->m_pkthdr.len;
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*m_head = m;
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}
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prod = sc->are_cdata.are_tx_prod;
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txd = &sc->are_cdata.are_txdesc[prod];
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error = bus_dmamap_load_mbuf_sg(sc->are_cdata.are_tx_tag, txd->tx_dmamap,
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*m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
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error = bus_dmamap_load_mbuf_sg(sc->are_cdata.are_tx_tag,
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txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
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if (error == EFBIG) {
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panic("EFBIG");
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device_printf(sc->are_dev, "are_encap EFBIG error\n");
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m = m_defrag(*m_head, M_NOWAIT);
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if (m == NULL) {
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m_freem(*m_head);
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*m_head = NULL;
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return (ENOBUFS);
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}
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*m_head = m;
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error = bus_dmamap_load_mbuf_sg(sc->are_cdata.are_tx_tag,
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txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
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if (error != 0) {
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m_freem(*m_head);
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*m_head = NULL;
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return (error);
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}
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} else if (error != 0)
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return (error);
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if (nsegs == 0) {
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@ -729,13 +802,12 @@ are_encap(struct are_softc *sc, struct mbuf **m_head)
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for (i = 0; i < nsegs; i++) {
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desc = &sc->are_rdata.are_tx_ring[prod];
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desc->are_stat = ADSTAT_OWN;
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desc->are_devcs = ARE_DMASIZE(txsegs[i].ds_len) | ADCTL_CH;
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if (i == 0)
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desc->are_devcs |= ADCTL_Tx_FS;
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desc->are_devcs = ARE_DMASIZE(txsegs[i].ds_len);
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desc->are_addr = txsegs[i].ds_addr;
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/* link with previous descriptor */
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if (prev_desc)
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prev_desc->are_link = ARE_TX_RING_ADDR(sc, prod);
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/* end of descriptor */
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if (prod == ARE_TX_RING_CNT - 1)
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desc->are_devcs |= ADCTL_ER;
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sc->are_cdata.are_tx_cnt++;
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prev_desc = desc;
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@ -761,16 +833,16 @@ are_encap(struct are_softc *sc, struct mbuf **m_head)
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/* Start transmitting */
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/* Check if new list is queued in NDPTR */
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txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7;
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if (txstat == 0 || txstat == 6) {
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/* Transmit Process Stat is stop or suspended */
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CSR_WRITE_4(sc, CSR_TXPOLL, TXPOLL_TPD);
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if (startcount == 0 && (txstat == 0 || txstat == 6)) {
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desc = &sc->are_rdata.are_tx_ring[si];
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desc->are_devcs |= ADCTL_Tx_FS;
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}
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else {
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link_addr = ARE_TX_RING_ADDR(sc, si);
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/* Get previous descriptor */
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si = (si + ARE_TX_RING_CNT - 1) % ARE_TX_RING_CNT;
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desc = &sc->are_rdata.are_tx_ring[si];
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desc->are_link = link_addr;
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desc->are_devcs &= ~(ADCTL_Tx_IC | ADCTL_Tx_LS);
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}
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return (0);
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@ -782,6 +854,7 @@ are_start_locked(struct ifnet *ifp)
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struct are_softc *sc;
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struct mbuf *m_head;
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int enq;
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int txstat;
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sc = ifp->if_softc;
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@ -816,6 +889,14 @@ are_start_locked(struct ifnet *ifp)
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*/
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ETHER_BPF_MTAP(ifp, m_head);
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}
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if (enq > 0) {
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txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7;
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if (txstat == 0 || txstat == 6) {
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/* Transmit Process Stat is stop or suspended */
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CSR_WRITE_4(sc, CSR_TXPOLL, TXPOLL_TPD);
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}
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}
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}
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static void
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@ -44,6 +44,8 @@ struct are_desc {
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#define ARE_TX_RING_CNT 128
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#define ARE_TX_RING_SIZE sizeof(struct are_desc) * ARE_TX_RING_CNT
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#define ARE_RX_RING_SIZE sizeof(struct are_desc) * ARE_RX_RING_CNT
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#define ARE_MIN_FRAMELEN 60
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#define ARE_RING_ALIGN sizeof(struct are_desc)
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#define ARE_RX_ALIGN sizeof(uint32_t)
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#define ARE_MAXFRAGS 8
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