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- Add a few more register defintions for the PCI express capability

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registers.
- Cleanup PCI-X capability printf to not leave a dangling "supports" for
  some PCI-X bridges.
- Display additional PCI express details including the negotiated and max
  link width and the actual and maximum supported max payload.

MFC after:	1 month
This commit is contained in:
John Baldwin 2009-04-17 19:07:44 +00:00
parent e94ba2ce53
commit a28b3fc741
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=191222
2 changed files with 54 additions and 3 deletions
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28
sys/dev/pci/pcireg.h
View File

@ -596,8 +596,36 @@
#define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050
#define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060
#define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070
#define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080
#define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090
#define PCIM_EXP_TYPE_ROOT_EC 0x00a0
#define PCIM_EXP_FLAGS_SLOT 0x0100
#define PCIM_EXP_FLAGS_IRQ 0x3e00
#define PCIR_EXPRESS_DEVICE_CAP 0x4
#define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007
#define PCIR_EXPRESS_DEVICE_CTL 0x8
#define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0
#define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000
#define PCIR_EXPRESS_DEVICE_STA 0xa
#define PCIR_EXPRESS_LINK_CAP 0xc
#define PCIM_LINK_CAP_MAX_SPEED 0x0000000f
#define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0
#define PCIM_LINK_CAP_ASPM 0x00000c00
#define PCIM_LINK_CAP_L0S_EXIT 0x00007000
#define PCIM_LINK_CAP_L1_EXIT 0x00038000
#define PCIM_LINK_CAP_PORT 0xff000000
#define PCIR_EXPRESS_LINK_CTL 0x10
#define PCIR_EXPRESS_LINK_STA 0x12
#define PCIM_LINK_STA_SPEED 0x000f
#define PCIM_LINK_STA_WIDTH 0x03f0
#define PCIM_LINK_STA_TRAINING_ERROR 0x0400
#define PCIM_LINK_STA_TRAINING 0x0800
#define PCIM_LINK_STA_SLOT_CLOCK 0x1000
#define PCIR_EXPRESS_SLOT_CAP 0x14
#define PCIR_EXPRESS_SLOT_CTL 0x18
#define PCIR_EXPRESS_SLOT_STA 0x1a
#define PCIR_EXPRESS_ROOT_CTL 0x1c
#define PCIR_EXPRESS_ROOT_STA 0x20
/* MSI-X definitions */
#define PCIR_MSIX_CTRL 0x2

29
usr.sbin/pciconf/cap.c
View File

@ -151,7 +151,9 @@ cap_pcix(int fd, struct pci_conf *p, uint8_t ptr)
printf("64-bit ");
if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
printf("bridge ");
printf("supports");
if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP |
PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0)
printf("supports");
comma = 0;
if (status & PCIXM_STATUS_133CAP) {
printf("%s 133MHz", comma ? "," : "");
@ -357,9 +359,12 @@ cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr)
printf("PCI Bridge card=0x%08x", id);
}
#define MAX_PAYLOAD(field) (128 << (field))
static void
cap_express(int fd, struct pci_conf *p, uint8_t ptr)
{
uint32_t val;
uint16_t flags;
flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_FLAGS, 2);
@ -383,12 +388,30 @@ cap_express(int fd, struct pci_conf *p, uint8_t ptr)
case PCIM_EXP_TYPE_PCI_BRIDGE:
printf("PCI bridge");
break;
case PCIM_EXP_TYPE_PCIE_BRIDGE:
printf("PCI to PCIe bridge");
break;
case PCIM_EXP_TYPE_ROOT_INT_EP:
printf("root endpoint");
break;
case PCIM_EXP_TYPE_ROOT_EC:
printf("event collector");
break;
default:
printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 8);
printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 4);
break;
}
if (flags & PCIM_EXP_FLAGS_IRQ)
printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 17);
printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 8);
val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CAP, 4);
flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CTL, 2);
printf(" max data %d(%d)",
MAX_PAYLOAD((flags & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5),
MAX_PAYLOAD(val & PCIM_EXP_CAP_MAX_PAYLOAD));
val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_LINK_CAP, 4);
flags = read_config(fd, &p->pc_sel, ptr+ PCIR_EXPRESS_LINK_STA, 2);
printf(" link x%d(x%d)", (flags & PCIM_LINK_STA_WIDTH) >> 4,
(val & PCIM_LINK_CAP_MAX_WIDTH) >> 4);
}
static void