- Add a few more register defintions for the PCI express capability
registers. - Cleanup PCI-X capability printf to not leave a dangling "supports" for some PCI-X bridges. - Display additional PCI express details including the negotiated and max link width and the actual and maximum supported max payload. MFC after: 1 month
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=191222
@ -596,8 +596,36 @@
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#define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050
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#define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060
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#define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070
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#define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080
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#define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090
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#define PCIM_EXP_TYPE_ROOT_EC 0x00a0
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#define PCIM_EXP_FLAGS_SLOT 0x0100
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#define PCIM_EXP_FLAGS_IRQ 0x3e00
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#define PCIR_EXPRESS_DEVICE_CAP 0x4
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#define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007
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#define PCIR_EXPRESS_DEVICE_CTL 0x8
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#define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0
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#define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000
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#define PCIR_EXPRESS_DEVICE_STA 0xa
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#define PCIR_EXPRESS_LINK_CAP 0xc
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#define PCIM_LINK_CAP_MAX_SPEED 0x0000000f
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#define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0
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#define PCIM_LINK_CAP_ASPM 0x00000c00
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#define PCIM_LINK_CAP_L0S_EXIT 0x00007000
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#define PCIM_LINK_CAP_L1_EXIT 0x00038000
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#define PCIM_LINK_CAP_PORT 0xff000000
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#define PCIR_EXPRESS_LINK_CTL 0x10
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#define PCIR_EXPRESS_LINK_STA 0x12
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#define PCIM_LINK_STA_SPEED 0x000f
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#define PCIM_LINK_STA_WIDTH 0x03f0
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#define PCIM_LINK_STA_TRAINING_ERROR 0x0400
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#define PCIM_LINK_STA_TRAINING 0x0800
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#define PCIM_LINK_STA_SLOT_CLOCK 0x1000
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#define PCIR_EXPRESS_SLOT_CAP 0x14
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#define PCIR_EXPRESS_SLOT_CTL 0x18
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#define PCIR_EXPRESS_SLOT_STA 0x1a
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#define PCIR_EXPRESS_ROOT_CTL 0x1c
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#define PCIR_EXPRESS_ROOT_STA 0x20
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/* MSI-X definitions */
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#define PCIR_MSIX_CTRL 0x2
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@ -151,7 +151,9 @@ cap_pcix(int fd, struct pci_conf *p, uint8_t ptr)
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printf("64-bit ");
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if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
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printf("bridge ");
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printf("supports");
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if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP |
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PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0)
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printf("supports");
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comma = 0;
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if (status & PCIXM_STATUS_133CAP) {
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printf("%s 133MHz", comma ? "," : "");
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@ -357,9 +359,12 @@ cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr)
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printf("PCI Bridge card=0x%08x", id);
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}
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#define MAX_PAYLOAD(field) (128 << (field))
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static void
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cap_express(int fd, struct pci_conf *p, uint8_t ptr)
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{
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uint32_t val;
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uint16_t flags;
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flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_FLAGS, 2);
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@ -383,12 +388,30 @@ cap_express(int fd, struct pci_conf *p, uint8_t ptr)
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case PCIM_EXP_TYPE_PCI_BRIDGE:
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printf("PCI bridge");
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break;
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case PCIM_EXP_TYPE_PCIE_BRIDGE:
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printf("PCI to PCIe bridge");
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break;
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case PCIM_EXP_TYPE_ROOT_INT_EP:
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printf("root endpoint");
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break;
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case PCIM_EXP_TYPE_ROOT_EC:
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printf("event collector");
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break;
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default:
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printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 8);
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printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 4);
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break;
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}
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if (flags & PCIM_EXP_FLAGS_IRQ)
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printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 17);
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printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 8);
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val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CAP, 4);
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flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CTL, 2);
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printf(" max data %d(%d)",
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MAX_PAYLOAD((flags & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5),
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MAX_PAYLOAD(val & PCIM_EXP_CAP_MAX_PAYLOAD));
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val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_LINK_CAP, 4);
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flags = read_config(fd, &p->pc_sel, ptr+ PCIR_EXPRESS_LINK_STA, 2);
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printf(" link x%d(x%d)", (flags & PCIM_LINK_STA_WIDTH) >> 4,
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(val & PCIM_LINK_CAP_MAX_WIDTH) >> 4);
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}
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static void
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