Unbreak G3 support. G3 processors don't have an L3 cache, so we shouldn't try to program it.
Approved by: marcel (mentor)
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=183262
@ -251,8 +251,6 @@ cpu_setup(u_int cpuid)
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}
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switch (vers) {
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case MPC750:
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case IBM750FX:
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case MPC7400:
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case MPC7410:
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case MPC7447A:
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@ -260,11 +258,18 @@ cpu_setup(u_int cpuid)
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case MPC7450:
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case MPC7455:
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case MPC7457:
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/* G3 systems don't have an L3 cache, so only check
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* for G4 and above */
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l3cr_config = mfspr(SPR_L3CR);
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/* Fallthrough */
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case MPC750:
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case IBM750FX:
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cpu_print_speed();
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printf("\n");
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l2cr_config = mfspr(SPR_L2CR);
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l3cr_config = mfspr(SPR_L3CR);
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if (bootverbose)
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cpu_print_cacheinfo(cpuid, vers);
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