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Unbreak G3 support. G3 processors don't have an L3 cache, so we shouldn't try to program it.

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Approved by:	marcel (mentor)
This commit is contained in:
Nathan Whitehorn 2008-09-22 03:21:02 +00:00
parent 51947cb625
commit a2fff700c9
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=183262
1 changed files with 8 additions and 3 deletions
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11
sys/powerpc/powerpc/cpu.c
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@ -251,8 +251,6 @@ cpu_setup(u_int cpuid)
}
switch (vers) {
case MPC750:
case IBM750FX:
case MPC7400:
case MPC7410:
case MPC7447A:
@ -260,11 +258,18 @@ cpu_setup(u_int cpuid)
case MPC7450:
case MPC7455:
case MPC7457:
/* G3 systems don't have an L3 cache, so only check
* for G4 and above */
l3cr_config = mfspr(SPR_L3CR);
/* Fallthrough */
case MPC750:
case IBM750FX:
cpu_print_speed();
printf("\n");
l2cr_config = mfspr(SPR_L2CR);
l3cr_config = mfspr(SPR_L3CR);
if (bootverbose)
cpu_print_cacheinfo(cpuid, vers);