d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Revert r343095

Browse Source 
This was intended to fix the soft reset timeout on boot for OrangePi One/R1
with internal PHY, but seems to cause other problems later on due to soft
resetting around some state changes that may or may not make the NIC
non-functional.

Reverting this for now while a better solution is sought out.
This commit is contained in:
Kyle Evans 2019-01-17 18:51:56 +00:00
parent 2b5691ee44
commit a3a7d2a4e5
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=343119
1 changed files with 41 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

77
sys/arm/allwinner/if_awg.c
View File

@ -750,31 +750,6 @@ awg_disable_intr(struct awg_softc *sc)
WR4(sc, EMAC_INT_EN, 0);
}
static int
awg_reset(struct awg_softc *sc)
{
int retry;
/* Soft reset all registers and logic */
WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
/* Wait for soft reset bit to self-clear */
for (retry = SOFT_RST_RETRY; retry > 0; retry--) {
if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0)
break;
DELAY(10);
}
if (retry == 0) {
device_printf(sc->dev, "soft reset timed out\n");
#ifdef AWG_DEBUG
awg_dump_regs(sc->dev);
#endif
return (ETIMEDOUT);
}
return (0);
}
static void
awg_init_locked(struct awg_softc *sc)
{
@ -790,12 +765,6 @@ awg_init_locked(struct awg_softc *sc)
if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
return;
awg_reset(sc);
/* Write transmit and receive descriptor base address registers */
WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
awg_setup_rxfilter(sc);
/* Configure DMA burst length and priorities */
@ -1684,6 +1653,40 @@ awg_phy_reset(device_t dev)
return (0);
}
static int
awg_reset(device_t dev)
{
struct awg_softc *sc;
int retry;
sc = device_get_softc(dev);
/* Reset PHY if necessary */
if (awg_phy_reset(dev) != 0) {
device_printf(dev, "failed to reset PHY\n");
return (ENXIO);
}
/* Soft reset all registers and logic */
WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
/* Wait for soft reset bit to self-clear */
for (retry = SOFT_RST_RETRY; retry > 0; retry--) {
if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0)
break;
DELAY(10);
}
if (retry == 0) {
device_printf(dev, "soft reset timed out\n");
#ifdef AWG_DEBUG
awg_dump_regs(dev);
#endif
return (ETIMEDOUT);
}
return (0);
}
static void
awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
{
@ -1837,6 +1840,10 @@ awg_setup_dma(device_t dev)
bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
BUS_DMASYNC_PREWRITE);
/* Write transmit and receive descriptor base address registers */
WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
return (0);
}
@ -1881,12 +1888,10 @@ awg_attach(device_t dev)
/* Read MAC address before resetting the chip */
awg_get_eaddr(dev, eaddr);
/* Reset PHY if necessary */
error = awg_phy_reset(dev);
if (error != 0) {
device_printf(dev, "failed to reset PHY\n");
/* Soft reset EMAC core */
error = awg_reset(dev);
if (error != 0)
return (error);
}
/* Setup DMA descriptors */
error = awg_setup_dma(dev);