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Disable branch-target instruction cache on MPC7457 as outlined

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in Motorola processor errata.

Submitted by:  Suleiman Souhlal <refugee@segfaulted.com>
This commit is contained in:
Peter Grehan 2004-02-09 07:04:01 +00:00
parent f893fdd54e
commit a4d2c25de5
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=125617
1 changed files with 3 additions and 2 deletions
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5
sys/powerpc/powerpc/cpu.c
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@ -177,8 +177,9 @@ cpu_setup(u_int cpuid)
case MPC7457:
case MPC7455:
case MPC7450:
/* Disable BTIC on 7450 Rev 2.0 or earlier */
if ((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
/* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
|| (pvr >> 16) == MPC7457)
hid0 &= ~HID0_BTIC;
/* Select NAP mode. */
hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);