arm64: rockchip: rk3399_pll: Fix the recalc function
The plls frequency are now correctly calculated in fractional mode and integer mode. While here add some debug printfs (disabled by default) Tested with powerd on the little cluster on a RockPro64. MFC after: 1 week
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=344699
@ -359,43 +359,56 @@ static int
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rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *freq)
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{
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struct rk_clk_pll_sc *sc;
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uint64_t rate;
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uint32_t dsmpd, refdiv, fbdiv;
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uint32_t postdiv1, postdiv2, frac;
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uint32_t raw1, raw2, raw3, raw4;
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uint32_t postdiv1, postdiv2, fracdiv;
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uint32_t con1, con2, con3, con4;
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uint64_t foutvco;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(clk);
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READ4(clk, sc->base_offset, &raw1);
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READ4(clk, sc->base_offset + 4, &raw2);
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READ4(clk, sc->base_offset + 8, &raw3);
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READ4(clk, sc->base_offset + 0xC, &raw4);
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READ4(clk, sc->base_offset, &con1);
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READ4(clk, sc->base_offset + 4, &con2);
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READ4(clk, sc->base_offset + 8, &con3);
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READ4(clk, sc->base_offset + 0xC, &con4);
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DEVICE_UNLOCK(clk);
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fbdiv = (raw1 & RK3399_CLK_PLL_FBDIV_MASK) >> RK3399_CLK_PLL_FBDIV_SHIFT;
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dprintf("con0: %x\n", con1);
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dprintf("con1: %x\n", con2);
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dprintf("con2: %x\n", con3);
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dprintf("con3: %x\n", con4);
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postdiv1 = (raw2 & RK3399_CLK_PLL_POSTDIV1_MASK) >> RK3399_CLK_PLL_POSTDIV1_SHIFT;
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postdiv2 = (raw2 & RK3399_CLK_PLL_POSTDIV2_MASK) >> RK3399_CLK_PLL_POSTDIV2_SHIFT;
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refdiv = (raw2 & RK3399_CLK_PLL_REFDIV_MASK) >> RK3399_CLK_PLL_REFDIV_SHIFT;
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fbdiv = (con1 & RK3399_CLK_PLL_FBDIV_MASK) >> RK3399_CLK_PLL_FBDIV_SHIFT;
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frac = (raw3 & RK3399_CLK_PLL_FRAC_MASK) >> RK3399_CLK_PLL_FRAC_SHIFT;
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postdiv1 = (con2 & RK3399_CLK_PLL_POSTDIV1_MASK) >> RK3399_CLK_PLL_POSTDIV1_SHIFT;
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postdiv2 = (con2 & RK3399_CLK_PLL_POSTDIV2_MASK) >> RK3399_CLK_PLL_POSTDIV2_SHIFT;
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refdiv = (con2 & RK3399_CLK_PLL_REFDIV_MASK) >> RK3399_CLK_PLL_REFDIV_SHIFT;
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dsmpd = (raw4 & RK3399_CLK_PLL_DSMPD_MASK) >> RK3399_CLK_PLL_DSMPD_SHIFT;
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fracdiv = (con3 & RK3399_CLK_PLL_FRAC_MASK) >> RK3399_CLK_PLL_FRAC_SHIFT;
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fracdiv >>= 24;
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dsmpd = (con4 & RK3399_CLK_PLL_DSMPD_MASK) >> RK3399_CLK_PLL_DSMPD_SHIFT;
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dprintf("fbdiv: %d\n", fbdiv);
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dprintf("postdiv1: %d\n", postdiv1);
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dprintf("postdiv2: %d\n", postdiv2);
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dprintf("refdiv: %d\n", refdiv);
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dprintf("fracdiv: %d\n", fracdiv);
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dprintf("dsmpd: %d\n", dsmpd);
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dprintf("parent freq=%lu\n", *freq);
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rate = *freq * fbdiv / refdiv;
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if (dsmpd == 0) {
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/* Fractional mode */
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uint64_t frac_rate;
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frac_rate = *freq * frac / refdiv;
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rate += frac_rate >> 24;
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foutvco = *freq / refdiv * (fbdiv + fracdiv);
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} else {
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/* Integer mode */
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foutvco = *freq / refdiv * fbdiv;
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}
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dprintf("foutvco: %lu\n", foutvco);
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*freq = rate / postdiv1 / postdiv2;
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if (*freq % 2)
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*freq = *freq + 1;
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*freq = foutvco / postdiv1 / postdiv2;
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dprintf("freq: %lu\n", *freq);
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return (0);
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}
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