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- Move to array based indexing for TX/RX descriptor/buffer management

Browse Source 
- Added support for ITR (interrupt throttle register). This feature is available on
adapters based on 82545 and above
- Fixed problem with vlan support when traffic has priority bits set. (kern/45907)

PR:			kern/45907
MFC after:		1 week
This commit is contained in:
Prafulla Deuskar 2002-12-23 19:11:23 +00:00
parent c2095e2b12
commit a58e485d36
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=108229
3 changed files with 514 additions and 533 deletions
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6
sys/dev/em/README
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@ -2,7 +2,7 @@ $FreeBSD$
FreeBSD* Driver for the Intel(R) PRO/1000 Family of Adapters
============================================================
September 11, 2002
November 12, 2002
Contents
@ -23,8 +23,8 @@ In This Release
This file describes the FreeBSD* driver, version 1.4.x, for the Intel(R)
PRO/1000 Family of Adapters. This driver has been developed for use with
FreeBSD, version 4.6. As a new feature for this release, the driver is now
compiled by default into the FreeBSD 4.6 kernel.
FreeBSD, version 4.7. As a new feature for this release, the driver is now
compiled by default into the FreeBSD 4.7 kernel.
The driver supports Transmit/Receive Checksum Offload and Jumbo Frames on
all but the 82542-based adapters. For specific adapters, refer to the

919
sys/dev/em/if_em.c
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122
sys/dev/em/if_em.h
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@ -75,38 +75,38 @@ POSSIBILITY OF SUCH DAMAGE.
#include <dev/em/if_em_hw.h>
/* Tunables -- Begin */
/*
/* Tunables */
/*
* FlowControl
* Valid Range: 0-3 (0=none, 1=Rx only, 2=Tx only, 3=Rx&Tx)
* Default: Read flow control settings from the EEPROM
* This parameter controls the automatic generation(Tx) and response(Rx) to
* Ethernet PAUSE frames.
*/
/*
/*
* TxDescriptors
* Valid Range: 80-256 for 82542 and 82543-based adapters
* 80-4096 for 82540, 82544, 82545, and 82546-based adapters
* Default Value: 256
* This value is the number of transmit descriptors allocated by the driver.
* Increasing this value allows the driver to queue more transmits. Each
* descriptor is 16 bytes.
*/
* descriptor is 16 bytes.
*/
#define EM_MAX_TXD 256
/*
* RxDescriptors
* Valid Range: 80-256 for 82542 and 82543-based adapters
* 80-4096 for 82540, 82544, 82545, and 82546-based adapters
* Default Value: 256
* Default Value: 256
* This value is the number of receive descriptors allocated by the driver.
* Increasing this value allows the driver to buffer more incoming packets.
* Each descriptor is 16 bytes. A receive buffer is also allocated for each
* descriptor. The maximum MTU size is 16110.
*
*
*/
#define EM_MAX_RXD 256
@ -120,7 +120,20 @@ POSSIBILITY OF SUCH DAMAGE.
* system is reporting dropped transmits, this value may be set too high
* causing the driver to run out of available transmit descriptors.
*/
#define EM_TIDV 128
#define EM_TIDV 64
/*
* TxAbsIntDelay (82540, 82545, and 82546-based adapters only)
* Valid Range: 0-65535 (0=off)
* Default Value: 64
* This value, in units of 1.024 microseconds, limits the delay in which a
* transmit interrupt is generated. Useful only if TxIntDelay is non-zero,
* this value ensures that an interrupt is generated after the initial
* packet is sent on the wire within the set amount of time. Proper tuning,
* along with TxIntDelay, may improve traffic throughput in specific
* network conditions.
*/
#define EM_TADV 64
/*
* RxIntDelay
@ -135,13 +148,26 @@ POSSIBILITY OF SUCH DAMAGE.
* descriptors.
*
* CAUTION: When setting RxIntDelay to a value other than 0, adapters
* may hang (stop transmitting) under certain network conditions.
* may hang (stop transmitting) under certain network conditions.
* If this occurs a WATCHDOG message is logged in the system event log.
* In addition, the controller is automatically reset, restoring the
* network connection. To eliminate the potential for the hang
* ensure that RxIntDelay is set to 0.
*/
#define EM_RDTR 0
#define EM_RDTR 0
/*
* RxAbsIntDelay (82540, 82545, and 82546-based adapters only)
* Valid Range: 0-65535 (0=off)
* Default Value: 64
* This value, in units of 1.024 microseconds, limits the delay in which a
* receive interrupt is generated. Useful only if RxIntDelay is non-zero,
* this value ensures that an interrupt is generated after the initial
* packet is received within the set amount of time. Proper tuning,
* along with RxIntDelay, may improve traffic throughput in specific network
* conditions.
*/
#define EM_RADV 64
/*
@ -198,6 +224,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
ADVERTISE_1000_FULL)
#define EM_VENDOR_ID 0x8086
#define EM_MMBA 0x0010 /* Mem base address */
#define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
@ -207,9 +234,11 @@ POSSIBILITY OF SUCH DAMAGE.
#define IOCTL_CMD_TYPE u_long
#define MAX_NUM_MULTICAST_ADDRESSES 128
#define PCI_ANY_ID (~0U)
#ifndef ETHER_ALIGN
#define ETHER_ALIGN 2
#endif
#define QTAG_TYPE 0x8100
/* Defines for printing debug information */
@ -255,21 +284,10 @@ typedef struct _em_vendor_info_t {
} em_vendor_info_t;
struct em_tx_buffer {
STAILQ_ENTRY(em_tx_buffer) em_tx_entry;
struct em_buffer {
struct mbuf *m_head;
struct em_tx_desc *used_tx_desc;
};
/* ******************************************************************************
* This structure stores information about the 2k aligned receive buffer
* into which the E1000 DMA's frames.
* ******************************************************************************/
struct em_rx_buffer {
STAILQ_ENTRY(em_rx_buffer) em_rx_entry;
struct mbuf *m_head;
u_int64_t buffer_addr;
};
typedef enum _XSUM_CONTEXT_T {
OFFLOAD_NONE,
@ -302,31 +320,43 @@ struct adapter {
u_int16_t link_speed;
u_int16_t link_duplex;
u_int32_t tx_int_delay;
u_int32_t tx_abs_int_delay;
u_int32_t rx_int_delay;
u_int32_t rx_abs_int_delay;
XSUM_CONTEXT_T active_checksum_context;
/* Transmit definitions */
struct em_tx_desc *first_tx_desc;
struct em_tx_desc *last_tx_desc;
struct em_tx_desc *next_avail_tx_desc;
struct em_tx_desc *tx_desc_base;
volatile u_int16_t num_tx_desc_avail;
u_int16_t num_tx_desc;
u_int32_t txd_cmd;
struct em_tx_buffer *tx_buffer_area;
STAILQ_HEAD(__em_tx_buffer_free, em_tx_buffer) free_tx_buffer_list;
STAILQ_HEAD(__em_tx_buffer_used, em_tx_buffer) used_tx_buffer_list;
/*
* Transmit definitions
*
* We have an array of num_tx_desc descriptors (handled
* by the controller) paired with an array of tx_buffers
* (at tx_buffer_area).
* The index of the next available descriptor is next_avail_tx_desc.
* The number of remaining tx_desc is num_tx_desc_avail.
*/
struct em_tx_desc *tx_desc_base;
u_int32_t next_avail_tx_desc;
u_int32_t oldest_used_tx_desc;
volatile u_int16_t num_tx_desc_avail;
u_int16_t num_tx_desc;
u_int32_t txd_cmd;
struct em_buffer *tx_buffer_area;
/*
* Receive definitions
*
* we have an array of num_rx_desc rx_desc (handled by the
* controller), and paired with an array of rx_buffers
* (at rx_buffer_area).
* The next pair to check on receive is at offset next_rx_desc_to_check
*/
struct em_rx_desc *rx_desc_base;
u_int32_t next_rx_desc_to_check;
u_int16_t num_rx_desc;
u_int32_t rx_buffer_len;
struct em_buffer *rx_buffer_area;
/* Receive definitions */
struct em_rx_desc *first_rx_desc;
struct em_rx_desc *last_rx_desc;
struct em_rx_desc *next_rx_desc_to_check;
struct em_rx_desc *rx_desc_base;
u_int16_t num_rx_desc;
u_int32_t rx_buffer_len;
struct em_rx_buffer *rx_buffer_area;
STAILQ_HEAD(__em_rx_buffer, em_rx_buffer) rx_buffer_list;
/* Jumbo frame */
struct mbuf *fmp;
@ -339,8 +369,6 @@ struct adapter {
unsigned long mbuf_cluster_failed;
unsigned long no_tx_desc_avail1;
unsigned long no_tx_desc_avail2;
unsigned long no_tx_buffer_avail1;
unsigned long no_tx_buffer_avail2;
#ifdef DBG_STATS
unsigned long no_pkts_avail;
unsigned long clean_tx_interrupts;