arge: do an explicit flush between updating the TX ring and starting transmit.

The MIPS busdma sync operations currently are a big no-op on coherent memory.
This isn't strictly correct behaviour as we need a SYNC in here to ensure that
the writes have finished and are visible in main memory before the MMIO accesses
occur.  This will have to be addressed in a later commit.

But, before that happens, let's at least do a flush here to make things
more "correct".

This is required for even remotely sensible behaviour on mips74k with
write-through memory enabled.

sys/mips/atheros/if_arge.c

@@ -1550,6 +1550,9 @@ arge_encap(struct arge_softc *sc, struct mbuf **m_head)
 	    sc->arge_cdata.arge_tx_ring_map,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 
+	/* Flush writes */
+	ARGE_BARRIER_WRITE(sc);
+
 	/* Start transmitting */
 	ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n",
 	    __func__);