amd-vi: set iommu msi configuration using pci_enable_msi method
This is better than directly changing PCI configuration space of the device because it makes the PCI bus aware of the configuration. Also, the change allows to drop a bunch of code that duplicated pci_enable_msi() functionality. I wonder if it's possible to further simplify the code by using pci_alloc_msi().
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=326539
@ -119,15 +119,6 @@ CTASSERT(sizeof(amdvi_dte) == 0x200000);
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static SLIST_HEAD (, amdvi_domain) dom_head;
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static inline void
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amdvi_pci_write(struct amdvi_softc *softc, int off, uint32_t data)
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{
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pci_cfgregwrite(PCI_RID2BUS(softc->pci_rid),
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PCI_RID2SLOT(softc->pci_rid), PCI_RID2FUNC(softc->pci_rid),
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off, data, 4);
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}
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static inline uint32_t
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amdvi_pci_read(struct amdvi_softc *softc, int off)
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{
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@ -137,32 +128,6 @@ amdvi_pci_read(struct amdvi_softc *softc, int off)
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off, 4));
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}
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static int
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amdvi_find_pci_cap(struct amdvi_softc *softc, uint8_t capability, int *off)
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{
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uint32_t read;
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uint8_t ptr;
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read = amdvi_pci_read(softc, PCIR_COMMAND);
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if (((read >> 16) & PCIM_STATUS_CAPPRESENT) == 0)
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return (ENXIO);
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/* Read the starting of capability pointer. */
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read = amdvi_pci_read(softc, PCIR_CAP_PTR);
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ptr = read & 0xFF;
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while (ptr != 0) {
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read = amdvi_pci_read(softc, ptr);
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if ((read & 0xFF) == capability) {
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*off = ptr;
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return (0);
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}
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ptr = (read >> 8) & 0xFF;
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}
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return (ENOENT);
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}
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#ifdef AMDVI_ATS_ENABLE
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/* XXX: Should be in pci.c */
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/*
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@ -837,36 +802,47 @@ amdvi_free_evt_intr_res(device_t dev)
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dev, 1, &softc->event_irq);
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}
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static bool
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static bool
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amdvi_alloc_intr_resources(struct amdvi_softc *softc)
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{
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struct amdvi_ctrl *ctrl;
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device_t dev, pcib;
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device_t mmio_dev;
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uint64_t msi_addr;
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uint32_t msi_data, temp;
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int err, msi_off;
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uint32_t msi_data;
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int err;
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dev = softc->dev;
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pcib = device_get_parent(device_get_parent(dev));
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mmio_dev = pci_find_bsf(PCI_RID2BUS(softc->pci_rid),
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PCI_RID2SLOT(softc->pci_rid), PCI_RID2FUNC(softc->pci_rid));
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if (device_is_attached(mmio_dev)) {
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device_printf(dev,
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"warning: IOMMU device is claimed by another driver %s\n",
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device_get_driver(mmio_dev)->name);
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}
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softc->event_irq = -1;
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softc->event_rid = 0;
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/*
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* Section 3.7.1 of IOMMU rev 2.0. With MSI, there is only one
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* interrupt. XXX: Enable MSI/X support.
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*/
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err = PCIB_ALLOC_MSI(pcib, dev, 1, 1, &softc->event_irq);
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if (err) {
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device_printf(dev,
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"Couldn't find event MSI IRQ resource.\n");
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return (ENOENT);
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}
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err = bus_set_resource(dev, SYS_RES_IRQ, softc->event_rid,
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softc->event_irq, 1);
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if (err) {
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device_printf(dev, "Couldn't set event MSI resource.\n");
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return (ENXIO);
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}
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softc->event_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&softc->event_rid, RF_ACTIVE);
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if (!softc->event_res) {
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@ -888,13 +864,6 @@ amdvi_alloc_intr_resources(struct amdvi_softc *softc)
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bus_describe_intr(dev, softc->event_res, softc->event_tag,
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"fault");
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err = amdvi_find_pci_cap(softc, PCIY_MSI, &msi_off);
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if (err) {
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device_printf(dev, "Couldn't find MSI capability, err = %d.\n",
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err);
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return (err);
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}
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err = PCIB_MAP_MSI(pcib, dev, softc->event_irq, &msi_addr,
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&msi_data);
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if (err) {
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@ -909,17 +878,8 @@ amdvi_alloc_intr_resources(struct amdvi_softc *softc)
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ctrl = softc->ctrl;
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ctrl->status &= AMDVI_STATUS_EV_OF | AMDVI_STATUS_EV_INTR;
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/* Configure MSI */
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amdvi_pci_write(softc, msi_off + PCIR_MSI_ADDR, msi_addr);
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amdvi_pci_write(softc, msi_off + PCIR_MSI_ADDR_HIGH,
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msi_addr >> 32);
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amdvi_pci_write(softc, msi_off + PCIR_MSI_DATA_64BIT, msi_data);
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/* Now enable MSI interrupt. */
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temp = amdvi_pci_read(softc, msi_off);
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temp |= (PCIM_MSICTRL_MSI_ENABLE << 16); /* MSI enable. */
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amdvi_pci_write(softc, msi_off, temp);
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pci_enable_msi(mmio_dev, msi_addr, msi_data);
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return (0);
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}
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