Add support for Ingenic JZ4780 SMBus controller.
Reviewed by: kan Relnotes: yes Differential Revision: https://reviews.freebsd.org/D8793
This commit is contained in:
parent
2cae16075b
commit
a7514a4925
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=310172
@ -75,6 +75,9 @@ device ext_resources
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device gpio
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device iicbus
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device iic
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device scbus
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device da
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@ -4,6 +4,7 @@ mips/ingenic/jz4780_dwc_fdt.c optional dwcotg
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mips/ingenic/jz4780_ehci.c optional ehci
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mips/ingenic/jz4780_mmc.c optional mmc
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mips/ingenic/jz4780_ohci.c optional ohci
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mips/ingenic/jz4780_smb.c optional iicbus
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mips/ingenic/jz4780_uart.c optional uart
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mips/ingenic/jz4780_clock.c standard
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480
sys/mips/ingenic/jz4780_smb.c
Normal file
480
sys/mips/ingenic/jz4780_smb.c
Normal file
@ -0,0 +1,480 @@
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/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Ingenic JZ4780 SMB Controller
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/time.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/extres/clk/clk.h>
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#include <mips/ingenic/jz4780_smb.h>
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#include "iicbus_if.h"
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#define JZSMB_TIMEOUT ((300UL * hz) / 1000)
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#define JZSMB_SPEED_STANDARD 100000
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#define JZSMB_SETUP_TIME_STANDARD 300
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#define JZSMB_HOLD_TIME_STANDARD 400
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#define JZSMB_PERIOD_MIN_STANDARD 4000
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#define JZSMB_PERIOD_MAX_STANDARD 4700
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#define JZSMB_SPEED_FAST 400000
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#define JZSMB_SETUP_TIME_FAST 450
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#define JZSMB_HOLD_TIME_FAST 450
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#define JZSMB_PERIOD_MIN_FAST 600
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#define JZSMB_PERIOD_MAX_FAST 1300
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#define JZSMB_HCNT_BASE 8
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#define JZSMB_HCNT_MIN 6
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#define JZSMB_LCNT_BASE 1
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#define JZSMB_LCNT_MIN 8
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static inline int
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tstohz(const struct timespec *tsp)
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{
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struct timeval tv;
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TIMESPEC_TO_TIMEVAL(&tv, tsp);
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return (tvtohz(&tv));
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}
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static struct ofw_compat_data compat_data[] = {
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{ "ingenic,jz4780-i2c", 1 },
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{ NULL, 0 }
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};
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static struct resource_spec jzsmb_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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struct jzsmb_softc {
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struct resource *res;
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struct mtx mtx;
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clk_t clk;
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device_t iicbus;
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int busy;
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uint32_t i2c_freq;
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uint64_t bus_freq;
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uint32_t status;
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struct iic_msg *msg;
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};
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#define SMB_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define SMB_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define SMB_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
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#define SMB_READ(sc, reg) bus_read_2((sc)->res, (reg))
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#define SMB_WRITE(sc, reg, val) bus_write_2((sc)->res, (reg), (val))
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static phandle_t
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jzsmb_get_node(device_t bus, device_t dev)
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{
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return (ofw_bus_get_node(bus));
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}
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static int
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jzsmb_enable(struct jzsmb_softc *sc, int enable)
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{
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SMB_ASSERT_LOCKED(sc);
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if (enable) {
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SMB_WRITE(sc, SMBENB, SMBENB_SMBENB);
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while ((SMB_READ(sc, SMBENBST) & SMBENBST_SMBEN) == 0)
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;
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} else {
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SMB_WRITE(sc, SMBENB, 0);
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while ((SMB_READ(sc, SMBENBST) & SMBENBST_SMBEN) != 0)
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;
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}
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return (0);
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}
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static int
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jzsmb_reset_locked(device_t dev, u_char addr)
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{
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struct jzsmb_softc *sc;
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uint16_t con;
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uint32_t period;
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int hcnt, lcnt, setup_time, hold_time;
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sc = device_get_softc(dev);
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SMB_ASSERT_LOCKED(sc);
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/* Setup master mode operation */
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/* Disable SMB */
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jzsmb_enable(sc, 0);
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/* Disable interrupts */
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SMB_WRITE(sc, SMBINTM, 0);
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/* Set supported speed mode and expected SCL frequency */
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period = sc->bus_freq / sc->i2c_freq;
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con = SMBCON_REST | SMBCON_SLVDIS | SMBCON_MD;
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switch (sc->i2c_freq) {
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case JZSMB_SPEED_STANDARD:
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con |= SMBCON_SPD_STANDARD;
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setup_time = JZSMB_SETUP_TIME_STANDARD;
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hold_time = JZSMB_HOLD_TIME_STANDARD;
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hcnt = (period * JZSMB_PERIOD_MIN_STANDARD) /
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(JZSMB_PERIOD_MAX_STANDARD + JZSMB_PERIOD_MIN_STANDARD);
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lcnt = period - hcnt;
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hcnt = MAX(hcnt - JZSMB_HCNT_BASE, JZSMB_HCNT_MIN);
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lcnt = MAX(lcnt - JZSMB_LCNT_BASE, JZSMB_LCNT_MIN);
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SMB_WRITE(sc, SMBCON, con);
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SMB_WRITE(sc, SMBSHCNT, hcnt);
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SMB_WRITE(sc, SMBSLCNT, lcnt);
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break;
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case JZSMB_SPEED_FAST:
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con |= SMBCON_SPD_FAST;
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setup_time = JZSMB_SETUP_TIME_FAST;
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hold_time = JZSMB_HOLD_TIME_FAST;
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hcnt = (period * JZSMB_PERIOD_MIN_FAST) /
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(JZSMB_PERIOD_MAX_FAST + JZSMB_PERIOD_MIN_FAST);
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lcnt = period - hcnt;
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hcnt = MAX(hcnt - JZSMB_HCNT_BASE, JZSMB_HCNT_MIN);
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lcnt = MAX(lcnt - JZSMB_LCNT_BASE, JZSMB_LCNT_MIN);
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SMB_WRITE(sc, SMBCON, con);
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SMB_WRITE(sc, SMBFHCNT, hcnt);
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SMB_WRITE(sc, SMBFLCNT, lcnt);
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break;
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default:
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return (EINVAL);
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}
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setup_time = ((setup_time * sc->bus_freq / 1000) / 1000000) + 1;
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setup_time = MIN(1, MAX(255, setup_time));
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SMB_WRITE(sc, SMBSDASU, setup_time);
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hold_time = ((hold_time * sc->bus_freq / 1000) / 1000000) - 1;
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hold_time = MAX(255, hold_time);
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if (hold_time >= 0)
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SMB_WRITE(sc, SMBSDAHD, hold_time | SMBSDAHD_HDENB);
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else
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SMB_WRITE(sc, SMBSDAHD, 0);
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SMB_WRITE(sc, SMBTAR, addr >> 1);
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if (addr != 0) {
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/* Enable SMB */
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jzsmb_enable(sc, 1);
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}
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return (0);
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}
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static int
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jzsmb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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{
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struct jzsmb_softc *sc;
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int error;
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sc = device_get_softc(dev);
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SMB_LOCK(sc);
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error = jzsmb_reset_locked(dev, addr);
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SMB_UNLOCK(sc);
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return (error);
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}
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static int
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jzsmb_transfer_read(device_t dev, struct iic_msg *msg)
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{
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struct jzsmb_softc *sc;
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struct timespec start, diff;
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uint16_t con, resid;
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int timeo;
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sc = device_get_softc(dev);
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timeo = JZSMB_TIMEOUT * msg->len;
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SMB_ASSERT_LOCKED(sc);
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con = SMB_READ(sc, SMBCON);
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con |= SMBCON_STPHLD;
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SMB_WRITE(sc, SMBCON, con);
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getnanouptime(&start);
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for (resid = msg->len; resid > 0; resid--) {
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for (int i = 0; i < min(resid, 8); i++)
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SMB_WRITE(sc, SMBDC, SMBDC_CMD);
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for (;;) {
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getnanouptime(&diff);
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timespecsub(&diff, &start);
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if ((SMB_READ(sc, SMBST) & SMBST_RFNE) != 0) {
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msg->buf[msg->len - resid] =
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SMB_READ(sc, SMBDC) & SMBDC_DAT;
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break;
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} else
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DELAY(1000);
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if (tstohz(&diff) >= timeo) {
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device_printf(dev,
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"read timeout (status=0x%02x)\n",
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SMB_READ(sc, SMBST));
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return (EIO);
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}
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}
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}
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con = SMB_READ(sc, SMBCON);
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con &= ~SMBCON_STPHLD;
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SMB_WRITE(sc, SMBCON, con);
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return (0);
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}
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static int
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jzsmb_transfer_write(device_t dev, struct iic_msg *msg, int stop_hold)
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{
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struct jzsmb_softc *sc;
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struct timespec start, diff;
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uint16_t con, resid;
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int timeo;
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sc = device_get_softc(dev);
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timeo = JZSMB_TIMEOUT * msg->len;
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SMB_ASSERT_LOCKED(sc);
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con = SMB_READ(sc, SMBCON);
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con |= SMBCON_STPHLD;
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SMB_WRITE(sc, SMBCON, con);
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getnanouptime(&start);
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for (resid = msg->len; resid > 0; resid--) {
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for (;;) {
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getnanouptime(&diff);
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timespecsub(&diff, &start);
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if ((SMB_READ(sc, SMBST) & SMBST_TFNF) != 0) {
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SMB_WRITE(sc, SMBDC,
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msg->buf[msg->len - resid]);
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break;
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} else
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DELAY((1000 * hz) / JZSMB_TIMEOUT);
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if (tstohz(&diff) >= timeo) {
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device_printf(dev,
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"write timeout (status=0x%02x)\n",
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SMB_READ(sc, SMBST));
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return (EIO);
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}
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}
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}
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if (!stop_hold) {
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con = SMB_READ(sc, SMBCON);
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con &= ~SMBCON_STPHLD;
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SMB_WRITE(sc, SMBCON, con);
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}
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return (0);
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}
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static int
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jzsmb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
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{
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struct jzsmb_softc *sc;
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uint32_t n;
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uint16_t con;
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int error;
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sc = device_get_softc(dev);
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SMB_LOCK(sc);
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while (sc->busy)
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mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
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sc->busy = 1;
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sc->status = 0;
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for (n = 0; n < nmsgs; n++) {
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/* Set target address */
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if (n == 0 || msgs[n].slave != msgs[n - 1].slave)
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jzsmb_reset_locked(dev, msgs[n].slave);
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/* Set read or write */
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if ((msgs[n].flags & IIC_M_RD) != 0)
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error = jzsmb_transfer_read(dev, &msgs[n]);
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else
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error = jzsmb_transfer_write(dev, &msgs[n],
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n < nmsgs - 1);
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if (error != 0)
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goto done;
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}
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done:
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/* Send stop if necessary */
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con = SMB_READ(sc, SMBCON);
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con &= ~SMBCON_STPHLD;
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SMB_WRITE(sc, SMBCON, con);
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/* Disable SMB */
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jzsmb_enable(sc, 0);
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sc->msg = NULL;
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sc->busy = 0;
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wakeup(sc);
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SMB_UNLOCK(sc);
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return (error);
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}
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static int
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jzsmb_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Ingenic JZ4780 SMB Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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jzsmb_attach(device_t dev)
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{
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struct jzsmb_softc *sc;
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phandle_t node;
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int error;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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mtx_init(&sc->mtx, device_get_nameunit(dev), "jzsmb", MTX_DEF);
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error = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
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if (error != 0) {
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device_printf(dev, "cannot get clock\n");
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goto fail;
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}
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error = clk_enable(sc->clk);
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if (error != 0) {
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device_printf(dev, "cannot enable clock\n");
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goto fail;
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}
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error = clk_get_freq(sc->clk, &sc->bus_freq);
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if (error != 0 || sc->bus_freq == 0) {
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device_printf(dev, "cannot get bus frequency\n");
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return (error);
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}
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if (bus_alloc_resources(dev, jzsmb_spec, &sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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error = ENXIO;
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goto fail;
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}
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if (OF_getencprop(node, "clock-frequency", &sc->i2c_freq,
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sizeof(sc->i2c_freq)) != 0 || sc->i2c_freq == 0)
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sc->i2c_freq = 100000; /* Default to standard mode */
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sc->iicbus = device_add_child(dev, "iicbus", -1);
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if (sc->iicbus == NULL) {
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device_printf(dev, "cannot add iicbus child device\n");
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error = ENXIO;
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goto fail;
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}
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bus_generic_attach(dev);
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return (0);
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fail:
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bus_release_resources(dev, jzsmb_spec, &sc->res);
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if (sc->clk != NULL)
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clk_release(sc->clk);
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mtx_destroy(&sc->mtx);
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return (error);
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}
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static device_method_t jzsmb_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, jzsmb_probe),
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DEVMETHOD(device_attach, jzsmb_attach),
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/* Bus interface */
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
||||
DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
|
||||
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
||||
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
||||
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
||||
DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
|
||||
DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
|
||||
DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
|
||||
|
||||
/* OFW methods */
|
||||
DEVMETHOD(ofw_bus_get_node, jzsmb_get_node),
|
||||
|
||||
/* iicbus interface */
|
||||
DEVMETHOD(iicbus_callback, iicbus_null_callback),
|
||||
DEVMETHOD(iicbus_reset, jzsmb_reset),
|
||||
DEVMETHOD(iicbus_transfer, jzsmb_transfer),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t jzsmb_driver = {
|
||||
"iichb",
|
||||
jzsmb_methods,
|
||||
sizeof(struct jzsmb_softc),
|
||||
};
|
||||
|
||||
static devclass_t jzsmb_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(iicbus, jzsmb, iicbus_driver, iicbus_devclass, 0, 0,
|
||||
BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
|
||||
EARLY_DRIVER_MODULE(jzsmb, simplebus, jzsmb_driver, jzsmb_devclass, 0, 0,
|
||||
BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
|
||||
MODULE_VERSION(jzsmb, 1);
|
98
sys/mips/ingenic/jz4780_smb.h
Normal file
98
sys/mips/ingenic/jz4780_smb.h
Normal file
@ -0,0 +1,98 @@
|
||||
/*-
|
||||
* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Ingenic JZ4780 SMB Controller
|
||||
*/
|
||||
|
||||
#ifndef __JZ4780_SMB_H__
|
||||
#define __JZ4780_SMB_H__
|
||||
|
||||
#define SMBCON 0x00
|
||||
#define SMBCON_STPHLD (1 << 7)
|
||||
#define SMBCON_SLVDIS (1 << 6)
|
||||
#define SMBCON_REST (1 << 5)
|
||||
#define SMBCON_MATP (1 << 4)
|
||||
#define SMBCON_SATP (1 << 3)
|
||||
#define SMBCON_SPD (3 << 1)
|
||||
#define SMBCON_SPD_STANDARD (1 << 1)
|
||||
#define SMBCON_SPD_FAST (2 << 1)
|
||||
#define SMBCON_MD (1 << 0)
|
||||
#define SMBTAR 0x04
|
||||
#define SMBTAR_MATP (1 << 12)
|
||||
#define SMBTAR_SPECIAL (1 << 11)
|
||||
#define SMBTAR_GC_OR_START (1 << 10)
|
||||
#define SMBTAR_SMBTAR (0x3ff << 0)
|
||||
#define SMBSAR 0x08
|
||||
#define SMBDC 0x10
|
||||
#define SMBDC_CMD (1 << 8)
|
||||
#define SMBDC_DAT (0xff << 0)
|
||||
#define SMBSHCNT 0x14
|
||||
#define SMBSLCNT 0x18
|
||||
#define SMBFHCNT 0x1c
|
||||
#define SMBFLCNT 0x20
|
||||
#define SMBINTST 0x2c
|
||||
#define SMBINTM 0x30
|
||||
#define SMBRXTL 0x38
|
||||
#define SMBTXTL 0x3c
|
||||
#define SMBCINT 0x40
|
||||
#define SMBCRXUF 0x44
|
||||
#define SMBCRXOF 0x48
|
||||
#define SMBCTXOF 0x4c
|
||||
#define SMBCRXREQ 0x50
|
||||
#define SMBCTXABT 0x54
|
||||
#define SMBCRXDN 0x58
|
||||
#define SMBCACT 0x5c
|
||||
#define SMBCSTP 0x60
|
||||
#define SMBCSTT 0x64
|
||||
#define SMBCGC 0x68
|
||||
#define SMBENB 0x6c
|
||||
#define SMBENB_SMBENB (1 << 0)
|
||||
#define SMBST 0x70
|
||||
#define SMBST_SLVACT (1 << 6)
|
||||
#define SMBST_MSTACT (1 << 5)
|
||||
#define SMBST_RFF (1 << 4)
|
||||
#define SMBST_RFNE (1 << 3)
|
||||
#define SMBST_TFE (1 << 2)
|
||||
#define SMBST_TFNF (1 << 1)
|
||||
#define SMBST_ACT (1 << 0)
|
||||
#define SMBABTSRC 0x80
|
||||
#define SMBDMACR 0x88
|
||||
#define SMBDMATDLR 0x8c
|
||||
#define SMBDMARDLR 0x90
|
||||
#define SMBSDASU 0x94
|
||||
#define SMBACKGC 0x98
|
||||
#define SMBENBST 0x9c
|
||||
#define SMBENBST_SLVRDLST (1 << 2)
|
||||
#define SMBENBST_SLVDISB (1 << 1)
|
||||
#define SMBENBST_SMBEN (1 << 0)
|
||||
#define SMBSDAHD 0xd0
|
||||
#define SMBSDAHD_HDENB (1 << 8)
|
||||
#define SMBSDAHD_SDAHD (0xff << 0)
|
||||
|
||||
#endif /* !__JZ4780_SMB_H__ */
|
Loading…
Reference in New Issue
Block a user