Merge amd64 and i386 <machine/intr_machdep.h> headers.
Reviewed by: kib MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16803
This commit is contained in:
John Baldwin
parent
ce9d7aee49
commit
a800b45c18
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=338101
@ -31,112 +31,7 @@
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#ifndef __MACHINE_INTR_MACHDEP_H__
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#define __MACHINE_INTR_MACHDEP_H__
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#ifdef _KERNEL
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/*
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* The maximum number of I/O interrupts we allow. This number is rather
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* arbitrary as it is just the maximum IRQ resource value. The interrupt
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* source for a given IRQ maps that I/O interrupt to device interrupt
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* source whether it be a pin on an interrupt controller or an MSI interrupt.
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* The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
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* interrupts allocate IDT vectors on demand. Currently we have 191 IDT
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* vectors available for device interrupts. On many systems with I/O APICs,
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* a lot of the IRQs are not used, so this number can be much larger than
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* 191 and still be safe since only interrupt sources in actual use will
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* allocate IDT vectors.
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*
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* The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs.
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* IRQ values from 256 to 767 are used by MSI. When running under the Xen
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* Hypervisor, IRQ values from 768 to 4863 are available for binding to
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* event channel events. We leave 255 unused to avoid confusion since 255 is
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* used in PCI to indicate an invalid IRQ.
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*/
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#define NUM_MSI_INTS 512
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#define FIRST_MSI_INT 256
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#ifdef XENHVM
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#include <xen/xen-os.h>
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#include <xen/interface/event_channel.h>
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#define NUM_EVTCHN_INTS NR_EVENT_CHANNELS
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#define FIRST_EVTCHN_INT \
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(FIRST_MSI_INT + NUM_MSI_INTS)
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#define LAST_EVTCHN_INT \
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(FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1)
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#else
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#define NUM_EVTCHN_INTS 0
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#endif
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#define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS + NUM_EVTCHN_INTS)
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/*
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* Default base address for MSI messages on x86 platforms.
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*/
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#define MSI_INTEL_ADDR_BASE 0xfee00000
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/*
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* - 1 ??? dummy counter.
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* - 2 counters for each I/O interrupt.
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* - 1 counter for each CPU for lapic timer.
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* - 8 counters for each CPU for IPI counters for SMP.
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*/
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#ifdef SMP
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#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 8) * MAXCPU)
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#else
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#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1)
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#endif
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#ifndef LOCORE
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typedef void inthand_t(void);
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#define IDTVEC(name) __CONCAT(X,name)
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struct intsrc;
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/*
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* Methods that a PIC provides to mask/unmask a given interrupt source,
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* "turn on" the interrupt on the CPU side by setting up an IDT entry, and
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* return the vector associated with this source.
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*/
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struct pic {
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void (*pic_enable_source)(struct intsrc *);
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void (*pic_disable_source)(struct intsrc *, int);
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void (*pic_eoi_source)(struct intsrc *);
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void (*pic_enable_intr)(struct intsrc *);
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void (*pic_disable_intr)(struct intsrc *);
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int (*pic_vector)(struct intsrc *);
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int (*pic_source_pending)(struct intsrc *);
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void (*pic_suspend)(struct pic *);
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void (*pic_resume)(struct pic *, bool suspend_cancelled);
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int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
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enum intr_polarity);
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int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
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void (*pic_reprogram_pin)(struct intsrc *);
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TAILQ_ENTRY(pic) pics;
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};
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/* Flags for pic_disable_source() */
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enum {
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PIC_EOI,
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PIC_NO_EOI,
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};
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/*
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* An interrupt source. The upper-layer code uses the PIC methods to
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* control a given source. The lower-layer PIC drivers can store additional
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* private data in a given interrupt source such as an interrupt pin number
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* or an I/O APIC pointer.
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*/
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struct intsrc {
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struct pic *is_pic;
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struct intr_event *is_event;
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u_long *is_count;
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u_long *is_straycount;
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u_int is_index;
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u_int is_handlers;
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u_int is_domain;
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u_int is_cpu;
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};
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struct trapframe;
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#include <x86/intr_machdep.h>
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/*
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* The following data structure holds per-cpu data, and is placed just
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@ -147,53 +42,4 @@ struct nmi_pcpu {
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register_t __padding; /* pad to 16 bytes */
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};
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#ifdef SMP
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extern cpuset_t intr_cpus;
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#endif
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extern struct mtx icu_lock;
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extern int elcr_found;
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#ifdef SMP
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extern int msix_disable_migration;
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#endif
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#ifndef DEV_ATPIC
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void atpic_reset(void);
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#endif
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/* XXX: The elcr_* prototypes probably belong somewhere else. */
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int elcr_probe(void);
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enum intr_trigger elcr_read_trigger(u_int irq);
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void elcr_resume(void);
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void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
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#ifdef SMP
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void intr_add_cpu(u_int cpu);
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#endif
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int intr_add_handler(const char *name, int vector, driver_filter_t filter,
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driver_intr_t handler, void *arg, enum intr_type flags,
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void **cookiep, int domain);
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#ifdef SMP
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int intr_bind(u_int vector, u_char cpu);
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#endif
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int intr_config_intr(int vector, enum intr_trigger trig,
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enum intr_polarity pol);
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int intr_describe(u_int vector, void *ih, const char *descr);
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void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
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u_int intr_next_cpu(int domain);
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struct intsrc *intr_lookup_source(int vector);
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int intr_register_pic(struct pic *pic);
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int intr_register_source(struct intsrc *isrc);
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int intr_remove_handler(void *cookie);
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void intr_resume(bool suspend_cancelled);
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void intr_suspend(void);
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void intr_reprogram(void);
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void intrcnt_add(const char *name, u_long **countp);
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void nexus_add_irq(u_long irq);
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int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
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void msi_init(void);
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int msi_map(int irq, uint64_t *addr, uint32_t *data);
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int msi_release(int *irqs, int count);
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int msix_alloc(device_t dev, int *irq);
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int msix_release(int irq);
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#endif /* !LOCORE */
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#endif /* _KERNEL */
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#endif /* !__MACHINE_INTR_MACHDEP_H__ */
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@ -1,190 +1,6 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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* This file is in the public domain.
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*/
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/* $FreeBSD$ */
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#ifndef __MACHINE_INTR_MACHDEP_H__
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#define __MACHINE_INTR_MACHDEP_H__
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#ifdef _KERNEL
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/*
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* The maximum number of I/O interrupts we allow. This number is rather
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* arbitrary as it is just the maximum IRQ resource value. The interrupt
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* source for a given IRQ maps that I/O interrupt to device interrupt
|
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* source whether it be a pin on an interrupt controller or an MSI interrupt.
|
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* The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
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* interrupts allocate IDT vectors on demand. Currently we have 191 IDT
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* vectors available for device interrupts. On many systems with I/O APICs,
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* a lot of the IRQs are not used, so this number can be much larger than
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* 191 and still be safe since only interrupt sources in actual use will
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* allocate IDT vectors.
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*
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* The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs.
|
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* IRQ values from 256 to 767 are used by MSI. When running under the Xen
|
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* Hypervisor, IRQ values from 768 to 4863 are available for binding to
|
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* event channel events. We leave 255 unused to avoid confusion since 255 is
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* used in PCI to indicate an invalid IRQ.
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*/
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#define NUM_MSI_INTS 512
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#define FIRST_MSI_INT 256
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#ifdef XENHVM
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#include <xen/xen-os.h>
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#include <xen/interface/event_channel.h>
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#define NUM_EVTCHN_INTS NR_EVENT_CHANNELS
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#define FIRST_EVTCHN_INT \
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(FIRST_MSI_INT + NUM_MSI_INTS)
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#define LAST_EVTCHN_INT \
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(FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1)
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#else /* !XENHVM */
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#define NUM_EVTCHN_INTS 0
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#endif
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#define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS + NUM_EVTCHN_INTS)
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/*
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* Default base address for MSI messages on x86 platforms.
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*/
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#define MSI_INTEL_ADDR_BASE 0xfee00000
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/*
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* - 1 ??? dummy counter.
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* - 2 counters for each I/O interrupt.
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* - 1 counter for each CPU for lapic timer.
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* - 8 counters for each CPU for IPI counters for SMP.
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*/
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#ifdef SMP
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#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 8) * MAXCPU)
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#else
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#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1)
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#endif
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#ifndef LOCORE
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typedef void inthand_t(void);
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#define IDTVEC(name) __CONCAT(X,name)
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struct intsrc;
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/*
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* Methods that a PIC provides to mask/unmask a given interrupt source,
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* "turn on" the interrupt on the CPU side by setting up an IDT entry, and
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* return the vector associated with this source.
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*/
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struct pic {
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void (*pic_enable_source)(struct intsrc *);
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void (*pic_disable_source)(struct intsrc *, int);
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void (*pic_eoi_source)(struct intsrc *);
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void (*pic_enable_intr)(struct intsrc *);
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void (*pic_disable_intr)(struct intsrc *);
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int (*pic_vector)(struct intsrc *);
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int (*pic_source_pending)(struct intsrc *);
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void (*pic_suspend)(struct pic *);
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void (*pic_resume)(struct pic *, bool suspend_cancelled);
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int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
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enum intr_polarity);
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int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
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void (*pic_reprogram_pin)(struct intsrc *);
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TAILQ_ENTRY(pic) pics;
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};
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/* Flags for pic_disable_source() */
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enum {
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PIC_EOI,
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PIC_NO_EOI,
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};
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/*
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* An interrupt source. The upper-layer code uses the PIC methods to
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* control a given source. The lower-layer PIC drivers can store additional
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* private data in a given interrupt source such as an interrupt pin number
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* or an I/O APIC pointer.
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*/
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struct intsrc {
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struct pic *is_pic;
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struct intr_event *is_event;
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u_long *is_count;
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u_long *is_straycount;
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u_int is_index;
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u_int is_handlers;
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u_int is_domain;
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u_int is_cpu;
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};
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struct trapframe;
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#ifdef SMP
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extern cpuset_t intr_cpus;
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#endif
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extern struct mtx icu_lock;
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extern int elcr_found;
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#ifdef SMP
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extern int msix_disable_migration;
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#endif
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#ifndef DEV_ATPIC
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void atpic_reset(void);
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#endif
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/* XXX: The elcr_* prototypes probably belong somewhere else. */
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int elcr_probe(void);
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enum intr_trigger elcr_read_trigger(u_int irq);
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void elcr_resume(void);
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void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
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#ifdef SMP
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void intr_add_cpu(u_int cpu);
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#endif
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int intr_add_handler(const char *name, int vector, driver_filter_t filter,
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driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep,
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int domain);
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#ifdef SMP
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int intr_bind(u_int vector, u_char cpu);
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#endif
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int intr_config_intr(int vector, enum intr_trigger trig,
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enum intr_polarity pol);
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int intr_describe(u_int vector, void *ih, const char *descr);
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void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
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u_int intr_next_cpu(int domain);
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struct intsrc *intr_lookup_source(int vector);
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int intr_register_pic(struct pic *pic);
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int intr_register_source(struct intsrc *isrc);
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int intr_remove_handler(void *cookie);
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void intr_resume(bool suspend_cancelled);
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void intr_suspend(void);
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void intr_reprogram(void);
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void intrcnt_add(const char *name, u_long **countp);
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void nexus_add_irq(u_long irq);
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int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
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void msi_init(void);
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int msi_map(int irq, uint64_t *addr, uint32_t *data);
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int msi_release(int* irqs, int count);
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int msix_alloc(device_t dev, int *irq);
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int msix_release(int irq);
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#endif /* !LOCORE */
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#endif /* _KERNEL */
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#endif /* !__MACHINE_INTR_MACHDEP_H__ */
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#include <x86/intr_machdep.h>
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190
sys/x86/include/intr_machdep.h
Normal file
190
sys/x86/include/intr_machdep.h
Normal file
@ -0,0 +1,190 @@
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/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
||||
*
|
||||
* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef __X86_INTR_MACHDEP_H__
|
||||
#define __X86_INTR_MACHDEP_H__
|
||||
|
||||
#ifdef _KERNEL
|
||||
|
||||
/*
|
||||
* The maximum number of I/O interrupts we allow. This number is rather
|
||||
* arbitrary as it is just the maximum IRQ resource value. The interrupt
|
||||
* source for a given IRQ maps that I/O interrupt to device interrupt
|
||||
* source whether it be a pin on an interrupt controller or an MSI interrupt.
|
||||
* The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
|
||||
* interrupts allocate IDT vectors on demand. Currently we have 191 IDT
|
||||
* vectors available for device interrupts. On many systems with I/O APICs,
|
||||
* a lot of the IRQs are not used, so this number can be much larger than
|
||||
* 191 and still be safe since only interrupt sources in actual use will
|
||||
* allocate IDT vectors.
|
||||
*
|
||||
* The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs.
|
||||
* IRQ values from 256 to 767 are used by MSI. When running under the Xen
|
||||
* Hypervisor, IRQ values from 768 to 4863 are available for binding to
|
||||
* event channel events. We leave 255 unused to avoid confusion since 255 is
|
||||
* used in PCI to indicate an invalid IRQ.
|
||||
*/
|
||||
#define NUM_MSI_INTS 512
|
||||
#define FIRST_MSI_INT 256
|
||||
#ifdef XENHVM
|
||||
#include <xen/xen-os.h>
|
||||
#include <xen/interface/event_channel.h>
|
||||
#define NUM_EVTCHN_INTS NR_EVENT_CHANNELS
|
||||
#define FIRST_EVTCHN_INT \
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(FIRST_MSI_INT + NUM_MSI_INTS)
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||||
#define LAST_EVTCHN_INT \
|
||||
(FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1)
|
||||
#else
|
||||
#define NUM_EVTCHN_INTS 0
|
||||
#endif
|
||||
#define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS + NUM_EVTCHN_INTS)
|
||||
|
||||
/*
|
||||
* Default base address for MSI messages on x86 platforms.
|
||||
*/
|
||||
#define MSI_INTEL_ADDR_BASE 0xfee00000
|
||||
|
||||
/*
|
||||
* - 1 ??? dummy counter.
|
||||
* - 2 counters for each I/O interrupt.
|
||||
* - 1 counter for each CPU for lapic timer.
|
||||
* - 8 counters for each CPU for IPI counters for SMP.
|
||||
*/
|
||||
#ifdef SMP
|
||||
#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 8) * MAXCPU)
|
||||
#else
|
||||
#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1)
|
||||
#endif
|
||||
|
||||
#ifndef LOCORE
|
||||
|
||||
typedef void inthand_t(void);
|
||||
|
||||
#define IDTVEC(name) __CONCAT(X,name)
|
||||
|
||||
struct intsrc;
|
||||
|
||||
/*
|
||||
* Methods that a PIC provides to mask/unmask a given interrupt source,
|
||||
* "turn on" the interrupt on the CPU side by setting up an IDT entry, and
|
||||
* return the vector associated with this source.
|
||||
*/
|
||||
struct pic {
|
||||
void (*pic_enable_source)(struct intsrc *);
|
||||
void (*pic_disable_source)(struct intsrc *, int);
|
||||
void (*pic_eoi_source)(struct intsrc *);
|
||||
void (*pic_enable_intr)(struct intsrc *);
|
||||
void (*pic_disable_intr)(struct intsrc *);
|
||||
int (*pic_vector)(struct intsrc *);
|
||||
int (*pic_source_pending)(struct intsrc *);
|
||||
void (*pic_suspend)(struct pic *);
|
||||
void (*pic_resume)(struct pic *, bool suspend_cancelled);
|
||||
int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
|
||||
enum intr_polarity);
|
||||
int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
|
||||
void (*pic_reprogram_pin)(struct intsrc *);
|
||||
TAILQ_ENTRY(pic) pics;
|
||||
};
|
||||
|
||||
/* Flags for pic_disable_source() */
|
||||
enum {
|
||||
PIC_EOI,
|
||||
PIC_NO_EOI,
|
||||
};
|
||||
|
||||
/*
|
||||
* An interrupt source. The upper-layer code uses the PIC methods to
|
||||
* control a given source. The lower-layer PIC drivers can store additional
|
||||
* private data in a given interrupt source such as an interrupt pin number
|
||||
* or an I/O APIC pointer.
|
||||
*/
|
||||
struct intsrc {
|
||||
struct pic *is_pic;
|
||||
struct intr_event *is_event;
|
||||
u_long *is_count;
|
||||
u_long *is_straycount;
|
||||
u_int is_index;
|
||||
u_int is_handlers;
|
||||
u_int is_domain;
|
||||
u_int is_cpu;
|
||||
};
|
||||
|
||||
struct trapframe;
|
||||
|
||||
#ifdef SMP
|
||||
extern cpuset_t intr_cpus;
|
||||
#endif
|
||||
extern struct mtx icu_lock;
|
||||
extern int elcr_found;
|
||||
#ifdef SMP
|
||||
extern int msix_disable_migration;
|
||||
#endif
|
||||
|
||||
#ifndef DEV_ATPIC
|
||||
void atpic_reset(void);
|
||||
#endif
|
||||
/* XXX: The elcr_* prototypes probably belong somewhere else. */
|
||||
int elcr_probe(void);
|
||||
enum intr_trigger elcr_read_trigger(u_int irq);
|
||||
void elcr_resume(void);
|
||||
void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
|
||||
#ifdef SMP
|
||||
void intr_add_cpu(u_int cpu);
|
||||
#endif
|
||||
int intr_add_handler(const char *name, int vector, driver_filter_t filter,
|
||||
driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep,
|
||||
int domain);
|
||||
#ifdef SMP
|
||||
int intr_bind(u_int vector, u_char cpu);
|
||||
#endif
|
||||
int intr_config_intr(int vector, enum intr_trigger trig,
|
||||
enum intr_polarity pol);
|
||||
int intr_describe(u_int vector, void *ih, const char *descr);
|
||||
void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
|
||||
u_int intr_next_cpu(int domain);
|
||||
struct intsrc *intr_lookup_source(int vector);
|
||||
int intr_register_pic(struct pic *pic);
|
||||
int intr_register_source(struct intsrc *isrc);
|
||||
int intr_remove_handler(void *cookie);
|
||||
void intr_resume(bool suspend_cancelled);
|
||||
void intr_suspend(void);
|
||||
void intr_reprogram(void);
|
||||
void intrcnt_add(const char *name, u_long **countp);
|
||||
void nexus_add_irq(u_long irq);
|
||||
int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
|
||||
void msi_init(void);
|
||||
int msi_map(int irq, uint64_t *addr, uint32_t *data);
|
||||
int msi_release(int *irqs, int count);
|
||||
int msix_alloc(device_t dev, int *irq);
|
||||
int msix_release(int irq);
|
||||
|
||||
#endif /* !LOCORE */
|
||||
#endif /* _KERNEL */
|
||||
#endif /* !__X86_INTR_MACHDEP_H__ */
|
||||
Loading…
Reference in New Issue
Block a user