ARM: Use new ARMv6 naming conventions for cache and TLB functions
in all but ARMv4 specific files. Expand ARMv6 compatibility stubs in cpu-v4.h. Use physical address in L2 cache functions if ARM_L2_PIPT is defined.
This commit is contained in:
parent
3af1c2aae2
commit
a89156f53f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=295319
@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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@ -101,8 +102,7 @@ platform_mp_start_ap(void)
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&cpucfg) != 0)
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panic("Couldn't map the CPUCFG\n");
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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dcache_wbinv_poc_all();
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_P_REG0,
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pmap_kextract((vm_offset_t)mpentry));
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@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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@ -162,8 +163,7 @@ platform_mp_start_ap(void)
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bus_space_write_region_4(fdtbus_bs_tag, ram, 0,
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(uint32_t *)&socfpga_trampoline, 8);
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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dcache_wbinv_poc_all();
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/* Put CPU1 out from reset */
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bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0);
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@ -53,6 +53,7 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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@ -485,7 +486,7 @@ platform_mp_start_ap(void)
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value |= AML_SCU_CONTROL_ENABLE;
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SCU_WRITE_4(AML_SCU_CONTROL_REG, value);
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SCU_BARRIER(AML_SCU_CONTROL_REG);
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cpu_idcache_wbinv_all();
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dcache_wbinv_poc_all();
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/* Set the boot address and power on each AP. */
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paddr = pmap_kextract((vm_offset_t)mpentry);
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@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/cons.h>
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#include <sys/proc.h>
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#include <sys/reboot.h>
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#include <sys/systm.h> /* just for boothowto */
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@ -53,9 +54,9 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm_extern.h>
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#include <machine/db_machdep.h>
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#include <machine/cpu.h>
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#include <machine/machdep.h>
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#include <machine/vmparam.h>
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#include <machine/cpu.h>
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#include <ddb/ddb.h>
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#include <ddb/db_access.h>
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@ -63,7 +64,7 @@ __FBSDID("$FreeBSD$");
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#include <ddb/db_output.h>
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#include <ddb/db_variables.h>
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#include <ddb/db_sym.h>
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#include <sys/cons.h>
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static int nil = 0;
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@ -245,11 +246,10 @@ db_write_bytes(vm_offset_t addr, size_t size, char *data)
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}
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/* make sure the caches and memory are in sync */
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cpu_icache_sync_range(addr, size);
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icache_sync(addr, size);
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/* In case the current page tables have been modified ... */
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cpu_tlb_flushID();
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cpu_cpwait();
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tlb_flush_all();
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return (0);
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}
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@ -59,8 +59,7 @@ dumpsys_wbinv_all(void)
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* have already been stopped, and their flush/invalidate was done as
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* part of stopping.
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*/
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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dcache_wbinv_poc_all();
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#ifdef __XSCALE__
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xscale_cache_clean_minidata();
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#endif
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@ -81,8 +81,8 @@ fiq_installhandler(void *func, size_t size)
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#if !defined(__ARM_FIQ_INDIRECT)
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vector_page_setprot(VM_PROT_READ);
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cpu_icache_sync_range((vm_offset_t) fiqvector, size);
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#endif
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icache_sync((vm_offset_t) fiqvector, size);
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}
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/*
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@ -396,7 +396,7 @@ arm_vector_init(vm_offset_t va, int which)
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}
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/* Now sync the vectors. */
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cpu_icache_sync_range(va, (ARM_NVEC * 2) * sizeof(u_int));
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icache_sync(va, (ARM_NVEC * 2) * sizeof(u_int));
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vector_page = va;
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@ -478,12 +478,7 @@ void
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cpu_flush_dcache(void *ptr, size_t len)
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{
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cpu_dcache_wb_range((uintptr_t)ptr, len);
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#ifdef ARM_L2_PIPT
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cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len);
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#else
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cpu_l2cache_wb_range((uintptr_t)ptr, len);
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#endif
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dcache_wb_poc((vm_offset_t)ptr, (vm_paddr_t)vtophys(ptr), len);
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}
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/* Get current clock frequency for the given cpu id. */
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@ -45,11 +45,11 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/atomic.h>
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#include <machine/cpu.h>
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#include <machine/elf.h>
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#include <machine/md_var.h>
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#include <machine/vmparam.h>
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#include <machine/minidump.h>
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#include <machine/cpufunc.h>
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#include <machine/vmparam.h>
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CTASSERT(sizeof(struct kerneldumpheader) == 512);
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@ -203,8 +203,7 @@ minidumpsys(struct dumperinfo *di)
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* by time we get to here, all that remains is to flush the L1 for the
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* current CPU, then the L2.
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*/
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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dcache_wbinv_poc_all();
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counter = 0;
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/* Walk page table pages, set bits in vm_page_dump */
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@ -123,9 +123,7 @@ cpu_mp_start(void)
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dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
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M_WAITOK | M_ZERO);
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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cpu_idcache_wbinv_all();
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dcache_wbinv_poc_all();
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/* Initialize boot code and start up processors */
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platform_mp_start_ap();
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@ -283,7 +281,7 @@ ipi_stop(void *dummy __unused)
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* stop will do the l2 cache flush after all other cores
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* have done their l1 flushes and stopped.
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*/
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cpu_idcache_wbinv_all();
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dcache_wbinv_poc_all();
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/* Indicate we are stopped */
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CPU_SET_ATOMIC(cpu, &stopped_cpus);
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@ -381,7 +379,7 @@ ipi_handler(void *arg)
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* stop will do the l2 cache flush after all other cores
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* have done their l1 flushes and stopped.
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*/
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cpu_idcache_wbinv_all();
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dcache_wbinv_poc_all();
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/* Indicate we are stopped */
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CPU_SET_ATOMIC(cpu, &stopped_cpus);
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@ -153,8 +153,13 @@ arm32_drain_writebuf(struct thread *td, void *args)
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{
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/* No args. */
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td->td_retval[0] = 0;
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#if __ARM_ARCH < 6
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cpu_drain_writebuf();
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#else
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dsb();
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cpu_l2cache_drain_writebuf();
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#endif
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td->td_retval[0] = 0;
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return (0);
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}
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@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/smp.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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@ -123,8 +124,7 @@ platform_mp_start_ap(void)
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BSWR4(MBOX3CLR_CORE(i), 0xffffffff);
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}
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wmb();
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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dcache_wbinv_poc_all();
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/* boot secondary CPUs */
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for (i = 1; i < mp_ncpus; i++) {
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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@ -149,7 +150,7 @@ platform_mp_start_ap(void)
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val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
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bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
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val | SCU_CONTROL_ENABLE);
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cpu_idcache_wbinv_all();
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dcache_wbinv_poc_all();
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/*
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* For each AP core, set the entry point address and argument registers,
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@ -41,7 +41,7 @@
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#include <machine/sysreg.h>
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#if __ARM_ARCH >= 6
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#error Newer include this file for ARMv6
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#error Never include this file for ARMv6
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#else
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#define CPU_ASID_KERNEL 0
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@ -124,12 +124,29 @@ _RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
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* armv5 asm code handles that.
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*/
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static __inline void
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tlb_flush_all(void)
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{
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cpu_tlb_flushID();
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cpu_cpwait();
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}
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static __inline void
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icache_sync(vm_offset_t va, vm_size_t size)
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{
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cpu_icache_sync_range(va, size);
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}
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static __inline void
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dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
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{
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cpu_dcache_inv_range(va, size);
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#ifdef ARM_L2_PIPT
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cpu_l2cache_inv_range(pa, size);
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#else
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cpu_l2cache_inv_range(va, size);
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#endif
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}
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static __inline void
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@ -137,7 +154,11 @@ dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
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{
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/* See armv6 code, above, for why we do L2 before L1 in this case. */
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#ifdef ARM_L2_PIPT
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cpu_l2cache_inv_range(pa, size);
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#else
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cpu_l2cache_inv_range(va, size);
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#endif
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cpu_dcache_inv_range(va, size);
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}
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@ -146,7 +167,18 @@ dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
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{
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cpu_dcache_wb_range(va, size);
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#ifdef ARM_L2_PIPT
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cpu_l2cache_wb_range(pa, size);
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#else
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cpu_l2cache_wb_range(va, size);
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#endif
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}
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static __inline void
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dcache_wbinv_poc_all(void)
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{
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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}
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#endif /* _KERNEL */
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#error Only include this file for ARMv6
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#else
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#define CPU_ASID_KERNEL 0
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void dcache_wbinv_poc_all(void); /* !!! NOT SMP coherent function !!! */
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vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
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vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
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@ -161,9 +161,12 @@ struct cpu_functions {
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extern struct cpu_functions cpufuncs;
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extern u_int cputype;
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#if __ARM_ARCH < 6
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#define cpu_cpwait() cpufuncs.cf_cpwait()
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#endif
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#define cpu_control(c, e) cpufuncs.cf_control(c, e)
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#if __ARM_ARCH < 6
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#define cpu_setttb(t) cpufuncs.cf_setttb(t)
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#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
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@ -181,13 +184,16 @@ extern u_int cputype;
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#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all()
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#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
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#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
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#endif
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#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
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#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
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#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
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#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
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#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
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#if __ARM_ARCH < 6
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#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
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#endif
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#define cpu_sleep(m) cpufuncs.cf_sleep(m)
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#define cpu_setup() cpufuncs.cf_setup()
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@ -29,10 +29,10 @@
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#ifndef _MACHINE_KDB_H_
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#define _MACHINE_KDB_H_
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#include <machine/cpu.h>
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#include <machine/db_machdep.h>
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#include <machine/frame.h>
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#include <machine/psl.h>
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#include <machine/cpufunc.h>
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#include <machine/db_machdep.h>
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#define KDB_STOPPEDPCB(pc) &stoppcbs[pc->pc_cpuid]
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@ -56,7 +56,7 @@ static __inline void
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kdb_cpu_sync_icache(unsigned char *addr, size_t size)
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{
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cpu_icache_sync_range((vm_offset_t)addr, size);
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icache_sync((vm_offset_t)addr, size);
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}
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static __inline void
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@ -36,10 +36,12 @@ __FBSDID("$FreeBSD$");
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/resource.h>
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#include <sys/systm.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/fdt.h>
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#include <machine/smp.h>
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@ -143,8 +145,7 @@ pmsu_boot_secondary_cpu(void)
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bus_space_write_4(fdtbus_bs_tag, vaddr, PMSU_BOOT_ADDR_REDIRECT_OFFSET(1),
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pmap_kextract((vm_offset_t)mpentry));
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cpu_idcache_wbinv_all();
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cpu_l2cache_wbinv_all();
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dcache_wbinv_poc_all();
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armv7_sev();
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bus_space_unmap(fdtbus_bs_tag, vaddr, MV_PMSU_REGS_LEN);
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@ -40,6 +40,7 @@
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#include <dev/fdt/fdt_common.h>
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#include <machine/cpu.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/armreg.h>
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@ -174,7 +175,7 @@ platform_mp_start_ap(void)
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bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT,
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pmap_kextract((vm_offset_t)mpentry));
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cpu_idcache_wbinv_all();
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dcache_wbinv_poc_all();
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for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
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bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0);
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@ -36,6 +36,7 @@ __FBSDID("$FreeBSD$");
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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@ -171,8 +172,7 @@ platform_mp_start_ap(void)
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bus_space_write_region_4(fdtbus_bs_tag, imem, 0,
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(uint32_t *)&rk30xx_boot2, 8);
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cpu_idcache_wbinv_all();
|
||||
cpu_l2cache_wbinv_all();
|
||||
dcache_wbinv_poc_all();
|
||||
|
||||
/* Start all cores */
|
||||
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
|
||||
|
@ -36,6 +36,7 @@ __FBSDID("$FreeBSD$");
|
||||
#include <vm/vm.h>
|
||||
#include <vm/pmap.h>
|
||||
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/smp.h>
|
||||
#include <machine/fdt.h>
|
||||
#include <machine/intr.h>
|
||||
@ -135,8 +136,7 @@ platform_mp_start_ap(void)
|
||||
bus_space_write_4(fdtbus_bs_tag, sysram, 0x0,
|
||||
pmap_kextract((vm_offset_t)mpentry));
|
||||
|
||||
cpu_idcache_wbinv_all();
|
||||
cpu_l2cache_wbinv_all();
|
||||
dcache_wbinv_poc_all();
|
||||
|
||||
armv7_sev();
|
||||
bus_space_unmap(fdtbus_bs_tag, sysram, 0x100);
|
||||
|
@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
|
||||
#include <vm/vm.h>
|
||||
#include <vm/pmap.h>
|
||||
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/smp.h>
|
||||
#include <machine/fdt.h>
|
||||
#include <machine/intr.h>
|
||||
@ -72,8 +73,8 @@ platform_mp_start_ap(void)
|
||||
/* Enable the SCU */
|
||||
*(volatile unsigned int *)scu_addr |= 1;
|
||||
//*(volatile unsigned int *)(scu_addr + 0x30) |= 1;
|
||||
cpu_idcache_wbinv_all();
|
||||
cpu_l2cache_wbinv_all();
|
||||
dcache_wbinv_poc_all();
|
||||
|
||||
ti_smc0(0x200, 0xfffffdff, MODIFY_AUX_CORE_0);
|
||||
ti_smc0(pmap_kextract((vm_offset_t)mpentry), 0, WRITE_AUX_CORE_1);
|
||||
armv7_sev();
|
||||
|
@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
|
||||
#include <vm/vm.h>
|
||||
#include <vm/pmap.h>
|
||||
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/smp.h>
|
||||
#include <machine/fdt.h>
|
||||
#include <machine/intr.h>
|
||||
@ -104,8 +105,7 @@ platform_mp_start_ap(void)
|
||||
* magic location, 0xfffffff0, isn't in the SCU's filtering range so it
|
||||
* needs a write-back too.
|
||||
*/
|
||||
cpu_idcache_wbinv_all();
|
||||
cpu_l2cache_wbinv_all();
|
||||
dcache_wbinv_poc_all();
|
||||
|
||||
/* Wake up CPU1. */
|
||||
armv7_sev();
|
||||
|
@ -48,6 +48,7 @@
|
||||
#include <vm/vm_phys.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/cpu.h>
|
||||
#include <arm/broadcom/bcm2835/bcm2835_mbox.h>
|
||||
#include <arm/broadcom/bcm2835/bcm2835_vcbus.h>
|
||||
|
||||
@ -411,6 +412,7 @@ create_pagelist(char __user *buf, size_t count, unsigned short type,
|
||||
int run, addridx, actual_pages;
|
||||
int err;
|
||||
vm_paddr_t pagelist_phys;
|
||||
vm_paddr_t pa;
|
||||
|
||||
offset = (vm_offset_t)buf & (PAGE_SIZE - 1);
|
||||
num_pages = (count + offset + PAGE_SIZE - 1) / PAGE_SIZE;
|
||||
@ -533,7 +535,8 @@ create_pagelist(char __user *buf, size_t count, unsigned short type,
|
||||
(fragments - g_fragments_base)/g_fragment_size;
|
||||
}
|
||||
|
||||
cpu_dcache_wbinv_range((vm_offset_t)buf, count);
|
||||
pa = pmap_extract(PCPU_GET(curpmap), (vm_offset_t)buf);
|
||||
dcache_wbinv_poc((vm_offset_t)buf, pa, count);
|
||||
|
||||
bus_dmamap_sync(bi->pagelist_dma_tag, bi->pagelist_dma_map, BUS_DMASYNC_PREWRITE);
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user