Decode the arm64 ID_AA64ISAR1_EL1 register
Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D35627
This commit is contained in:
Andrew Turner
parent
69ce6ae21a
commit
a8fac0ce78
@ -127,6 +127,7 @@ struct cpu_desc {
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uint64_t id_aa64dfr1;
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uint64_t id_aa64isar0;
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uint64_t id_aa64isar1;
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uint64_t id_aa64isar2;
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uint64_t id_aa64mmfr0;
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uint64_t id_aa64mmfr1;
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uint64_t id_aa64mmfr2;
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@ -154,6 +155,7 @@ static u_int cpu_print_regs;
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#define PRINT_ID_AA64_DFR1 0x00000020
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#define PRINT_ID_AA64_ISAR0 0x00000100
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#define PRINT_ID_AA64_ISAR1 0x00000200
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#define PRINT_ID_AA64_ISAR2 0x00000400
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#define PRINT_ID_AA64_MMFR0 0x00001000
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#define PRINT_ID_AA64_MMFR1 0x00002000
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#define PRINT_ID_AA64_MMFR2 0x00004000
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@ -743,10 +745,10 @@ static struct mrs_field_value id_aa64isar1_apa[] = {
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MRS_FIELD_VALUE(ID_AA64ISAR1_APA_NONE, ""),
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MRS_FIELD_VALUE(ID_AA64ISAR1_APA_PAC, "APA PAC"),
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MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC, "APA EPAC"),
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MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC2, "PAuth+EPAC2"),
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MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC, "PAuth+FPAC"),
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MRS_FIELD_VALUE(ID_AA64ISAR1_APA_EPAC2, "APA EPAC2"),
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MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC, "APA FPAC"),
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MRS_FIELD_VALUE(ID_AA64ISAR1_APA_FPAC_COMBINED,
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"PAuth+FPAC+Combined"),
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"APA FPAC+Combined"),
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MRS_FIELD_VALUE_END,
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};
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@ -801,6 +803,73 @@ static struct mrs_field id_aa64isar1_fields[] = {
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};
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/* ID_AA64ISAR2_EL1 */
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static struct mrs_field_value id_aa64isar2_pac_frac[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, PAC_frac, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64isar2_bc[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, BC, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64isar2_mops[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, MOPS, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64isar2_apa3[] = {
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MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_NONE, ""),
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MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_PAC, "APA3 PAC"),
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MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC, "APA3 EPAC"),
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MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_EPAC2, "APA3 EPAC2"),
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MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC, "APA3 FPAC"),
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MRS_FIELD_VALUE(ID_AA64ISAR2_APA3_FPAC_COMBINED,
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"APA3 FPAC+Combined"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_hwcap id_aa64isar2_apa3_caps[] = {
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MRS_HWCAP(&elf_hwcap, HWCAP_PACA, ID_AA64ISAR2_APA3_PAC),
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MRS_HWCAP_END
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};
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static struct mrs_field_value id_aa64isar2_gpa3[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, GPA3, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_hwcap id_aa64isar2_gpa3_caps[] = {
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MRS_HWCAP(&elf_hwcap, HWCAP_PACG, ID_AA64ISAR2_GPA3_IMPL),
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MRS_HWCAP_END
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};
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static struct mrs_field_value id_aa64isar2_rpres[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, RPRES, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_aa64isar2_wfxt[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, WFxT, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field id_aa64isar2_fields[] = {
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MRS_FIELD(ID_AA64ISAR2, PAC_frac, false, MRS_EXACT,
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id_aa64isar2_pac_frac),
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MRS_FIELD(ID_AA64ISAR2, BC, false, MRS_EXACT, id_aa64isar2_bc),
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MRS_FIELD(ID_AA64ISAR2, MOPS, false, MRS_EXACT, id_aa64isar2_mops),
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MRS_FIELD_HWCAP(ID_AA64ISAR2, APA3, false, MRS_EXACT,
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id_aa64isar2_apa3, id_aa64isar2_apa3_caps),
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MRS_FIELD_HWCAP(ID_AA64ISAR2, GPA3, false, MRS_EXACT,
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id_aa64isar2_gpa3, id_aa64isar2_gpa3_caps),
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MRS_FIELD(ID_AA64ISAR2, RPRES, false, MRS_EXACT, id_aa64isar2_rpres),
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MRS_FIELD(ID_AA64ISAR2, WFxT, false, MRS_EXACT, id_aa64isar2_wfxt),
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MRS_FIELD_END,
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};
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/* ID_AA64MMFR0_EL1 */
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static struct mrs_field_value id_aa64mmfr0_exs[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR0, ExS, ALL, IMPL),
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@ -2179,6 +2248,11 @@ print_cpu_features(u_int cpu)
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print_id_register(sb, "Instruction Set Attributes 1",
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cpu_desc[cpu].id_aa64isar1, id_aa64isar1_fields);
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/* AArch64 Instruction Set Attribute Register 2 */
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if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR2) != 0)
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print_id_register(sb, "Instruction Set Attributes 2",
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cpu_desc[cpu].id_aa64isar2, id_aa64isar2_fields);
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/* AArch64 Processor Feature Register 0 */
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if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR0) != 0)
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print_id_register(sb, "Processor Features 0",
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@ -2308,6 +2382,7 @@ identify_cpu(u_int cpu)
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cpu_desc[cpu].id_aa64dfr1 = READ_SPECIALREG(id_aa64dfr1_el1);
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cpu_desc[cpu].id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
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cpu_desc[cpu].id_aa64isar1 = READ_SPECIALREG(id_aa64isar1_el1);
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cpu_desc[cpu].id_aa64isar2 = READ_SPECIALREG(id_aa64isar2_el1);
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cpu_desc[cpu].id_aa64mmfr0 = READ_SPECIALREG(id_aa64mmfr0_el1);
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cpu_desc[cpu].id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
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cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1);
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@ -2394,6 +2469,8 @@ check_cpu_regs(u_int cpu)
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cpu_print_regs |= PRINT_ID_AA64_ISAR0;
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if (cpu_desc[cpu].id_aa64isar1 != cpu_desc[0].id_aa64isar1)
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cpu_print_regs |= PRINT_ID_AA64_ISAR1;
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if (cpu_desc[cpu].id_aa64isar2 != cpu_desc[0].id_aa64isar2)
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cpu_print_regs |= PRINT_ID_AA64_ISAR2;
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if (cpu_desc[cpu].id_aa64mmfr0 != cpu_desc[0].id_aa64mmfr0)
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cpu_print_regs |= PRINT_ID_AA64_MMFR0;
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@ -673,6 +673,53 @@
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#define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT)
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#define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT)
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/* ID_AA64ISAR2_EL1 */
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#define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1)
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#define ID_AA64ISAR2_EL1_op0 3
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#define ID_AA64ISAR2_EL1_op1 0
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#define ID_AA64ISAR2_EL1_CRn 0
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#define ID_AA64ISAR2_EL1_CRm 6
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#define ID_AA64ISAR2_EL1_op2 2
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#define ID_AA64ISAR2_WFxT_SHIFT 0
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#define ID_AA64ISAR2_WFxT_MASK (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT)
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#define ID_AA64ISAR2_WFxT_VAL(x) ((x) & ID_AA64ISAR2_WFxT_MASK)
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#define ID_AA64ISAR2_WFxT_NONE (UL(0x0) << ID_AA64ISAR2_WFxT_SHIFT)
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#define ID_AA64ISAR2_WFxT_IMPL (UL(0x1) << ID_AA64ISAR2_WFxT_SHIFT)
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#define ID_AA64ISAR2_RPRES_SHIFT 4
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#define ID_AA64ISAR2_RPRES_MASK (UL(0xf) << ID_AA64ISAR2_RPRES_SHIFT)
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#define ID_AA64ISAR2_RPRES_VAL(x) ((x) & ID_AA64ISAR2_RPRES_MASK)
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#define ID_AA64ISAR2_RPRES_NONE (UL(0x0) << ID_AA64ISAR2_RPRES_SHIFT)
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#define ID_AA64ISAR2_RPRES_IMPL (UL(0x1) << ID_AA64ISAR2_RPRES_SHIFT)
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#define ID_AA64ISAR2_GPA3_SHIFT 8
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#define ID_AA64ISAR2_GPA3_MASK (UL(0xf) << ID_AA64ISAR2_GPA3_SHIFT)
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#define ID_AA64ISAR2_GPA3_VAL(x) ((x) & ID_AA64ISAR2_GPA3_MASK)
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#define ID_AA64ISAR2_GPA3_NONE (UL(0x0) << ID_AA64ISAR2_GPA3_SHIFT)
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#define ID_AA64ISAR2_GPA3_IMPL (UL(0x1) << ID_AA64ISAR2_GPA3_SHIFT)
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#define ID_AA64ISAR2_APA3_SHIFT 12
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#define ID_AA64ISAR2_APA3_MASK (UL(0xf) << ID_AA64ISAR2_APA3_SHIFT)
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#define ID_AA64ISAR2_APA3_VAL(x) ((x) & ID_AA64ISAR2_APA3_MASK)
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#define ID_AA64ISAR2_APA3_NONE (UL(0x0) << ID_AA64ISAR2_APA3_SHIFT)
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#define ID_AA64ISAR2_APA3_PAC (UL(0x1) << ID_AA64ISAR2_APA3_SHIFT)
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#define ID_AA64ISAR2_APA3_EPAC (UL(0x2) << ID_AA64ISAR2_APA3_SHIFT)
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#define ID_AA64ISAR2_APA3_EPAC2 (UL(0x3) << ID_AA64ISAR2_APA3_SHIFT)
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#define ID_AA64ISAR2_APA3_FPAC (UL(0x4) << ID_AA64ISAR2_APA3_SHIFT)
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#define ID_AA64ISAR2_APA3_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR2_APA3_SHIFT)
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#define ID_AA64ISAR2_MOPS_SHIFT 16
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#define ID_AA64ISAR2_MOPS_MASK (UL(0xf) << ID_AA64ISAR2_MOPS_SHIFT)
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#define ID_AA64ISAR2_MOPS_VAL(x) ((x) & ID_AA64ISAR2_MOPS_MASK)
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#define ID_AA64ISAR2_MOPS_NONE (UL(0x0) << ID_AA64ISAR2_MOPS_SHIFT)
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#define ID_AA64ISAR2_MOPS_IMPL (UL(0x1) << ID_AA64ISAR2_MOPS_SHIFT)
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#define ID_AA64ISAR2_BC_SHIFT 20
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#define ID_AA64ISAR2_BC_MASK (UL(0xf) << ID_AA64ISAR2_BC_SHIFT)
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#define ID_AA64ISAR2_BC_VAL(x) ((x) & ID_AA64ISAR2_BC_MASK)
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#define ID_AA64ISAR2_BC_NONE (UL(0x0) << ID_AA64ISAR2_BC_SHIFT)
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#define ID_AA64ISAR2_BC_IMPL (UL(0x1) << ID_AA64ISAR2_BC_SHIFT)
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#define ID_AA64ISAR2_PAC_frac_SHIFT 28
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#define ID_AA64ISAR2_PAC_frac_MASK (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT)
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#define ID_AA64ISAR2_PAC_frac_VAL(x) ((x) & ID_AA64ISAR2_PAC_frac_MASK)
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#define ID_AA64ISAR2_PAC_frac_NONE (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT)
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#define ID_AA64ISAR2_PAC_frac_IMPL (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT)
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/* ID_AA64MMFR0_EL1 */
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#define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1)
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#define ID_AA64MMFR0_EL1_op0 0x3
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