Cleanup the clock code. This includes:
o Remove alpha specific timer code (mc146818A) and compiled-out calibration of said timer. o Remove i386 inherited timer code (i8253) and related acquire and release functions. o Move sysbeep() from clock.c to machdep.c and have it return ENODEV. Console beeps should be implemented using ACPI or if no such device is described, using the sound driver. o Move the sysctls related to adjkerntz, disable_rtc_set and wall_cmos_clock from machdep.c to clock.c, where the variables are. o Don't hardcode a hz value of 1024 in cpu_initclocks() and don't bother faking a stathz that's 1/8 of that. Keep it simple: hz defaults to HZ and stathz equals hz. This is also how it's done for sparc64. o Keep a per-CPU ITC counter (pc_clock) and adjustment (pc_clockadj) to calculate ITC skew and corrections. On average, we adjust the ITC match register once every ~1500 interrupts for a duration of 2 consequtive interruprs. This is to correct the non-deterministic behaviour of the ITC interrupt (there's a delay between the match and the raising of the interrupt). o Add 4 debugging sysctls to monitor clock behaviour. Those are debug.clock_adjust_edges, debug.clock_adjust_excess, debug.clock_adjust_lost and debug.clock_adjust_ticks. The first counts the individual adjustment cycles (when the skew first crosses the threshold), the second counts the number of times the adjustment was excessive (any non-zero value is to be considered a bug), the third counts lost clock interrupts and the last counts the number of interrupts for which we applied an adjustment (debug.clock_adjust_ticks / debug.clock_adjust_edges gives the avarage duration of an individual adjustment -- should be ~2). While here, remove some nearby (trivial) left-overs from alpha and other cleanups.
This commit is contained in:
marcel
parent
0c6d0d5962
commit
a9b84efaa9
@ -1,6 +1,3 @@
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/* $FreeBSD$ */
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/* $NetBSD: clock.c,v 1.20 1998/01/31 10:32:47 ross Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1992, 1993
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@ -42,8 +39,10 @@
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*
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* @(#)clock.c 8.1 (Berkeley) 6/10/93
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*/
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/* $NetBSD: clock.c,v 1.20 1998/01/31 10:32:47 ross Exp $ */
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/kernel.h>
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@ -52,13 +51,11 @@
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/timetc.h>
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#include <sys/pcpu.h>
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#include <machine/pal.h>
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#include <machine/sal.h>
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#include <machine/clock.h>
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#include <machine/clockvar.h>
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#include <isa/isareg.h>
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#include <ia64/ia64/timerreg.h>
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#include <machine/cpu.h>
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#define SECMIN ((unsigned)60) /* seconds per minute */
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#define SECHOUR ((unsigned)(60*SECMIN)) /* seconds per hour */
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@ -68,198 +65,107 @@
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/*
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* 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
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* can use a simple formula for leap years.
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* XXX time_t is 64-bits on ia64.
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*/
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#define LEAPYEAR(y) (((y) % 4) == 0)
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kobj_t clockdev;
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int clockinitted;
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int tickfix;
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int tickfixinterval;
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static int sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS);
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int disable_rtc_set; /* disable resettodr() if != 0 */
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SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
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CTLFLAG_RW, &disable_rtc_set, 0, "");
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int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
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SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
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CTLFLAG_RW, &wall_cmos_clock, 0, "");
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int adjkerntz; /* local offset from GMT in seconds */
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int disable_rtc_set; /* disable resettodr() if != 0 */
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int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
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u_int64_t itm_reload; /* reload ticks for clock */
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static int beeping = 0;
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SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
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&adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
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kobj_t clockdev;
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int todr_initialized;
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uint64_t ia64_clock_reload;
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#ifndef SMP
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static timecounter_get_t ia64_get_timecount;
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static timecounter_get_t ia64_get_timecount;
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static struct timecounter ia64_timecounter = {
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ia64_get_timecount, /* get_timecount */
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0, /* no poll_pps */
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~0u, /* counter_mask */
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~0u, /* counter_mask */
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0, /* frequency */
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"ITC" /* name */
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};
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static unsigned
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ia64_get_timecount(struct timecounter* tc)
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{
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return ia64_get_itc();
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}
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#endif
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/* Values for timerX_state: */
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#define RELEASED 0
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#define RELEASE_PENDING 1
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#define ACQUIRED 2
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#define ACQUIRE_PENDING 3
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static int
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sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
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{
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int error;
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/* static u_char timer0_state; */
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static u_char timer2_state;
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/*
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* Algorithm for missed clock ticks from Linux/alpha.
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*/
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/*
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* Shift amount by which scaled_ticks_per_cycle is scaled. Shifting
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* by 48 gives us 16 bits for HZ while keeping the accuracy good even
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* for large CPU clock rates.
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*/
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#define FIX_SHIFT 48
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static u_int64_t scaled_ticks_per_cycle;
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static u_int32_t max_cycles_per_tick;
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static u_int32_t last_time;
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#if 0 /* not used yet */
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static u_int32_t calibrate_clocks(u_int32_t firmware_freq);
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#endif
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error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2, req);
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if (!error && req->newptr)
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resettodr();
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return (error);
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}
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void
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clockattach(kobj_t dev)
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{
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/*
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* Just bookkeeping.
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*/
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if (clockdev)
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panic("clockattach: multiple clocks");
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clockdev = dev;
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#ifdef EVCNT_COUNTERS
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evcnt_attach(dev, "intr", &clock_intr_evcnt);
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#endif
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/*
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* Get the clock started.
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*/
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/* Get the clock started. */
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CLOCK_INIT(clockdev);
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}
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/*
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* Machine-dependent clock routines.
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*
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* Startrtclock restarts the real-time clock, which provides
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* hardclock interrupts to kern_clock.c.
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*
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* Inittodr initializes the time of day hardware which provides
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* date functions. Its primary function is to use some file
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* system information in case the hardare clock lost state.
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*
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* Resettodr restores the time of day hardware after a time change.
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*/
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void
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pcpu_initclock(void)
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{
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PCPU_SET(clockadj, 0);
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PCPU_SET(clock, ia64_get_itc());
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ia64_set_itm(PCPU_GET(clock) + ia64_clock_reload);
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ia64_set_itv(CLOCK_VECTOR); /* highest priority class */
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}
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/*
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* Start the real-time and statistics clocks. Leave stathz 0 since there
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* are no other timers available.
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* Start the real-time and statistics clocks. We use cr.itc and cr.itm
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* to implement a 1000hz clock.
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*/
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void
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cpu_initclocks()
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{
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u_int32_t freq;
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/*
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* We use cr.itc and cr.itm to implement a 1024hz clock.
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*/
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hz = 1024;
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tick = 1000000 / hz; /* number of microseconds between interrupts */
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tickfix = 1000000 - (hz * tick);
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if (tickfix) {
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int ftp;
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ftp = min(ffs(tickfix), ffs(hz));
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tickfix >>= (ftp - 1);
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tickfixinterval = hz >> (ftp - 1);
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}
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if (!itc_frequency)
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if (itc_frequency == 0)
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panic("Unknown clock frequency");
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freq = itc_frequency;
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last_time = ia64_get_itc();
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scaled_ticks_per_cycle = ((u_int64_t)hz << FIX_SHIFT) / freq;
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max_cycles_per_tick = 2*freq / hz;
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stathz = hz;
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ia64_clock_reload = (itc_frequency + hz/2) / hz;
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#ifndef SMP
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ia64_timecounter.tc_frequency = freq;
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ia64_timecounter.tc_frequency = itc_frequency;
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tc_init(&ia64_timecounter);
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#endif
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itm_reload = (itc_frequency + hz/2) / hz;
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ia64_set_itm(ia64_get_itc() + itm_reload);
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ia64_set_itv(CLOCK_VECTOR); /* highest priority class */
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stathz = 128;
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pcpu_initclock();
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}
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#if 0 /* not used yet */
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static u_int32_t
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calibrate_clocks(u_int32_t firmware_freq)
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{
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u_int32_t start_pcc, stop_pcc;
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int sec, start_sec;
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if (bootverbose)
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printf("Calibrating clock(s) ... ");
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/* Read the mc146818A seconds counter. */
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if (CLOCK_GETSECS(clockdev, &sec))
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goto fail;
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/* Wait for the mC146818A seconds counter to change. */
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start_sec = sec;
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for (;;) {
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if (CLOCK_GETSECS(clockdev, &sec))
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goto fail;
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if (sec != start_sec)
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break;
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}
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/* Start keeping track of the PCC. */
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start_pcc = ia64_get_itc();
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/*
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* Wait for the mc146818A seconds counter to change.
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*/
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start_sec = sec;
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for (;;) {
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if (CLOCK_GETSECS(clockdev, &sec))
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goto fail;
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if (sec != start_sec)
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break;
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}
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/*
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* Read the PCC again to work out frequency.
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*/
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stop_pcc = ia64_get_itc();
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if (bootverbose) {
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printf("PCC clock: %u Hz (firmware %u Hz)\n",
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stop_pcc - start_pcc, firmware_freq);
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}
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return (stop_pcc - start_pcc);
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fail:
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if (bootverbose)
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printf("failed, using firmware default of %u Hz\n",
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firmware_freq);
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return (firmware_freq);
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}
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#endif
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/*
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* We assume newhz is either stathz or profhz, and that neither will
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* change after being set up above. Could recalculate intervals here
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* but that would be a drag.
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*/
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void
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cpu_startprofclock(void)
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{
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@ -283,20 +189,17 @@ static short dayyr[12] = {
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};
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/*
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* Initialze the time of day register, based on the time base which is, e.g.
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* from a filesystem. Base provides the time to within six months,
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* Initialize the time of day register, based on the time base which is,
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* e.g. from a filesystem. Base provides the time to within six months,
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* and the time of year clock (if any) provides the rest.
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*/
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void
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inittodr(base)
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time_t base;
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inittodr(time_t base)
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{
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register int days, yr;
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struct clocktime ct;
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time_t deltat;
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int badbase;
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int s;
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struct timespec ts;
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time_t deltat;
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int badbase, days, s, yr;
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if (base < 5*SECYR) {
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printf("WARNING: preposterous time in filesystem");
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@ -307,7 +210,7 @@ inittodr(base)
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badbase = 0;
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CLOCK_GET(clockdev, base, &ct);
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clockinitted = 1;
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todr_initialized = 1;
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/* simple sanity checks */
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if (ct.year < 70 || ct.mon < 1 || ct.mon > 12 || ct.day < 1 ||
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@ -333,12 +236,13 @@ inittodr(base)
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days += dayyr[ct.mon - 1] + ct.day - 1;
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if (LEAPYEAR(yr) && ct.mon > 2)
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days++;
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/* now have days since Jan 1, 1970; the rest is easy... */
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s = splclock();
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ts.tv_sec =
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ts.tv_sec =
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days * SECDAY + ct.hour * SECHOUR + ct.min * SECMIN + ct.sec;
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if (wall_cmos_clock)
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ts.tv_sec += adjkerntz;
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ts.tv_sec += adjkerntz;
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ts.tv_nsec = 0;
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tc_setclock(&ts);
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splx(s);
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@ -361,29 +265,26 @@ inittodr(base)
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}
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/*
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* Reset the TODR based on the time value; used when the TODR
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* has a preposterous value and also when the time is reset
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* by the stime system call. Also called when the TODR goes past
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* Reset the TODR based on the time value; used when the TODR has a
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* preposterous value and also when the time is reset by the stime
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* system call. Also called when the TODR goes past
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* TODRZERO + 100*(SECYEAR+2*SECDAY) (e.g. on Jan 2 just after midnight)
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* to wrap the TODR around.
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*/
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void
|
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resettodr()
|
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{
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register int t, t2, s;
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struct clocktime ct;
|
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unsigned long tm;
|
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unsigned long tm;
|
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int s, t, t2;
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|
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if (disable_rtc_set)
|
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if (!todr_initialized || disable_rtc_set)
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return;
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|
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s = splclock();
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tm = time_second;
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splx(s);
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if (!clockinitted)
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return;
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|
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/* Calculate local time to put in RTC */
|
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tm -= (wall_cmos_clock ? adjkerntz : 0);
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@ -419,86 +320,3 @@ resettodr()
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CLOCK_SET(clockdev, &ct);
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}
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#ifndef SMP
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static unsigned
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ia64_get_timecount(struct timecounter* tc)
|
||||
{
|
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return ia64_get_itc();
|
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}
|
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#endif
|
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|
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int
|
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acquire_timer2(int mode)
|
||||
{
|
||||
|
||||
if (timer2_state != RELEASED)
|
||||
return (-1);
|
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timer2_state = ACQUIRED;
|
||||
|
||||
/*
|
||||
* This access to the timer registers is as atomic as possible
|
||||
* because it is a single instruction. We could do better if we
|
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* knew the rate. Use of splclock() limits glitches to 10-100us,
|
||||
* and this is probably good enough for timer2, so we aren't as
|
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* careful with it as with timer0.
|
||||
*/
|
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outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
|
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|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
release_timer2()
|
||||
{
|
||||
|
||||
if (timer2_state != ACQUIRED)
|
||||
return (-1);
|
||||
timer2_state = RELEASED;
|
||||
outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
sysbeepstop(void *chan)
|
||||
{
|
||||
outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
|
||||
release_timer2();
|
||||
beeping = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Frequency of all three count-down timers; (TIMER_FREQ/freq) is the
|
||||
* appropriate count to generate a frequency of freq hz.
|
||||
*/
|
||||
#ifndef TIMER_FREQ
|
||||
#define TIMER_FREQ 1193182
|
||||
#endif
|
||||
#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x))
|
||||
|
||||
int
|
||||
sysbeep(int pitch, int period)
|
||||
{
|
||||
int x = splhigh();
|
||||
|
||||
if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
|
||||
if (!beeping) {
|
||||
/* Something else owns it. */
|
||||
splx(x);
|
||||
return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
|
||||
}
|
||||
|
||||
if (pitch) pitch = TIMER_DIV(pitch);
|
||||
|
||||
outb(TIMER_CNTR2, pitch);
|
||||
outb(TIMER_CNTR2, (pitch>>8));
|
||||
if (!beeping) {
|
||||
/* enable counter2 output to speaker */
|
||||
if (pitch) outb(IO_PPI, inb(IO_PPI) | 3);
|
||||
beeping = period;
|
||||
timeout(sysbeepstop, (void *)NULL, period);
|
||||
}
|
||||
splx(x);
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
@ -85,21 +85,51 @@ dummy_perf(unsigned long vector, struct trapframe *framep)
|
||||
void (*perf_irq)(unsigned long, struct trapframe *) = dummy_perf;
|
||||
|
||||
static unsigned int ints[MAXCPU];
|
||||
static unsigned int clks[MAXCPU];
|
||||
static unsigned int asts[MAXCPU];
|
||||
static unsigned int rdvs[MAXCPU];
|
||||
SYSCTL_OPAQUE(_debug, OID_AUTO, ints, CTLFLAG_RW, &ints, sizeof(ints), "IU","");
|
||||
SYSCTL_OPAQUE(_debug, OID_AUTO, clks, CTLFLAG_RW, &clks, sizeof(clks), "IU","");
|
||||
SYSCTL_OPAQUE(_debug, OID_AUTO, asts, CTLFLAG_RW, &asts, sizeof(asts), "IU","");
|
||||
SYSCTL_OPAQUE(_debug, OID_AUTO, rdvs, CTLFLAG_RW, &rdvs, sizeof(rdvs), "IU","");
|
||||
SYSCTL_OPAQUE(_debug, OID_AUTO, ints, CTLFLAG_RW, &ints, sizeof(ints), "IU",
|
||||
"");
|
||||
|
||||
static u_int schedclk2;
|
||||
static unsigned int clks[MAXCPU];
|
||||
#ifdef SMP
|
||||
SYSCTL_OPAQUE(_debug, OID_AUTO, clks, CTLFLAG_RW, &clks, sizeof(clks), "IU",
|
||||
"");
|
||||
#else
|
||||
SYSCTL_INT(_debug, OID_AUTO, clks, CTLFLAG_RW, clks, 0, "");
|
||||
#endif
|
||||
|
||||
#ifdef SMP
|
||||
static unsigned int asts[MAXCPU];
|
||||
SYSCTL_OPAQUE(_debug, OID_AUTO, asts, CTLFLAG_RW, &asts, sizeof(asts), "IU",
|
||||
"");
|
||||
|
||||
static unsigned int rdvs[MAXCPU];
|
||||
SYSCTL_OPAQUE(_debug, OID_AUTO, rdvs, CTLFLAG_RW, &rdvs, sizeof(rdvs), "IU",
|
||||
"");
|
||||
#endif
|
||||
|
||||
static int adjust_edges = 0;
|
||||
SYSCTL_INT(_debug, OID_AUTO, clock_adjust_edges, CTLFLAG_RW,
|
||||
&adjust_edges, 0, "Number of times ITC got more than 12.5% behind");
|
||||
|
||||
static int adjust_excess = 0;
|
||||
SYSCTL_INT(_debug, OID_AUTO, clock_adjust_excess, CTLFLAG_RW,
|
||||
&adjust_excess, 0, "Total number of ignored ITC interrupts");
|
||||
|
||||
static int adjust_lost = 0;
|
||||
SYSCTL_INT(_debug, OID_AUTO, clock_adjust_lost, CTLFLAG_RW,
|
||||
&adjust_lost, 0, "Total number of lost ITC interrupts");
|
||||
|
||||
static int adjust_ticks = 0;
|
||||
SYSCTL_INT(_debug, OID_AUTO, clock_adjust_ticks, CTLFLAG_RW,
|
||||
&adjust_ticks, 0, "Total number of ITC interrupts with adjustment");
|
||||
|
||||
void
|
||||
interrupt(u_int64_t vector, struct trapframe *framep)
|
||||
{
|
||||
struct thread *td;
|
||||
volatile struct ia64_interrupt_block *ib = IA64_INTERRUPT_BLOCK;
|
||||
uint64_t adj, clk, itc;
|
||||
int64_t delta;
|
||||
int count;
|
||||
|
||||
td = curthread;
|
||||
atomic_add_int(&td->td_intr_nesting_level, 1);
|
||||
@ -115,39 +145,55 @@ interrupt(u_int64_t vector, struct trapframe *framep)
|
||||
|
||||
if (vector == CLOCK_VECTOR) {/* clock interrupt */
|
||||
/* CTR0(KTR_INTR, "clock interrupt"); */
|
||||
|
||||
|
||||
cnt.v_intr++;
|
||||
#ifdef EVCNT_COUNTERS
|
||||
clock_intr_evcnt.ev_count++;
|
||||
#else
|
||||
intrcnt[INTRCNT_CLOCK]++;
|
||||
#endif
|
||||
critical_enter();
|
||||
/* Rearm so we get the next clock interrupt */
|
||||
ia64_set_itm(ia64_get_itc() + itm_reload);
|
||||
#ifdef SMP
|
||||
clks[PCPU_GET(cpuid)]++;
|
||||
/* Only the BSP runs the real clock */
|
||||
if (PCPU_GET(cpuid) == 0) {
|
||||
#endif
|
||||
hardclock((struct clockframe *)framep);
|
||||
/* divide hz (1024) by 8 to get stathz (128) */
|
||||
if ((++schedclk2 & 0x7) == 0) {
|
||||
if (profprocs != 0)
|
||||
profclock((struct clockframe *)framep);
|
||||
statclock((struct clockframe *)framep);
|
||||
}
|
||||
#ifdef SMP
|
||||
} else {
|
||||
hardclock_process((struct clockframe *)framep);
|
||||
if ((schedclk2 & 0x7) == 0) {
|
||||
if (profprocs != 0)
|
||||
profclock((struct clockframe *)framep);
|
||||
statclock((struct clockframe *)framep);
|
||||
}
|
||||
|
||||
critical_enter();
|
||||
|
||||
adj = PCPU_GET(clockadj);
|
||||
itc = ia64_get_itc();
|
||||
ia64_set_itm(itc + ia64_clock_reload - adj);
|
||||
clk = PCPU_GET(clock);
|
||||
delta = itc - clk;
|
||||
count = 0;
|
||||
while (delta >= ia64_clock_reload) {
|
||||
/* Only the BSP runs the real clock */
|
||||
if (PCPU_GET(cpuid) == 0)
|
||||
hardclock((struct clockframe *)framep);
|
||||
else
|
||||
hardclock_process((struct clockframe *)framep);
|
||||
if (profprocs != 0)
|
||||
profclock((struct clockframe *)framep);
|
||||
statclock((struct clockframe *)framep);
|
||||
delta -= ia64_clock_reload;
|
||||
clk += ia64_clock_reload;
|
||||
if (adj != 0)
|
||||
adjust_ticks++;
|
||||
count++;
|
||||
}
|
||||
#endif
|
||||
if (count > 0) {
|
||||
adjust_lost += count - 1;
|
||||
if (delta > (ia64_clock_reload >> 3)) {
|
||||
if (adj == 0)
|
||||
adjust_edges++;
|
||||
adj = ia64_clock_reload >> 4;
|
||||
} else if (delta < (ia64_clock_reload >> 3))
|
||||
adj = 0;
|
||||
} else {
|
||||
adj = 0;
|
||||
adjust_excess++;
|
||||
}
|
||||
PCPU_SET(clock, clk);
|
||||
PCPU_SET(clockadj, adj);
|
||||
|
||||
critical_exit();
|
||||
|
||||
#ifdef SMP
|
||||
} else if (vector == ipi_vector[IPI_AST]) {
|
||||
asts[PCPU_GET(cpuid)]++;
|
||||
@ -186,23 +232,6 @@ interrupt(u_int64_t vector, struct trapframe *framep)
|
||||
atomic_subtract_int(&td->td_intr_nesting_level, 1);
|
||||
}
|
||||
|
||||
int
|
||||
badaddr(addr, size)
|
||||
void *addr;
|
||||
size_t size;
|
||||
{
|
||||
return(badaddr_read(addr, size, NULL));
|
||||
}
|
||||
|
||||
int
|
||||
badaddr_read(addr, size, rptr)
|
||||
void *addr;
|
||||
size_t size;
|
||||
void *rptr;
|
||||
{
|
||||
return (1); /* XXX implement */
|
||||
}
|
||||
|
||||
/*
|
||||
* Hardware irqs have vectors starting at this offset.
|
||||
*/
|
||||
|
||||
@ -1357,26 +1357,6 @@ Debugger(const char *msg)
|
||||
}
|
||||
#endif /* no DDB */
|
||||
|
||||
static int
|
||||
sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
|
||||
{
|
||||
int error;
|
||||
error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
|
||||
req);
|
||||
if (!error && req->newptr)
|
||||
resettodr();
|
||||
return (error);
|
||||
}
|
||||
|
||||
SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
|
||||
&adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
|
||||
|
||||
SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
|
||||
CTLFLAG_RW, &disable_rtc_set, 0, "");
|
||||
|
||||
SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
|
||||
CTLFLAG_RW, &wall_cmos_clock, 0, "");
|
||||
|
||||
/*
|
||||
* Utility functions for manipulating instruction bundles.
|
||||
*/
|
||||
@ -1400,3 +1380,9 @@ ia64_pack_bundle(u_int64_t *lowp, u_int64_t *highp,
|
||||
*lowp = low;
|
||||
*highp = high;
|
||||
}
|
||||
|
||||
int
|
||||
sysbeep(int pitch, int period)
|
||||
{
|
||||
return (ENODEV);
|
||||
}
|
||||
|
||||
@ -123,10 +123,11 @@ ia64_ap_startup(void)
|
||||
|
||||
mtx_lock_spin(&sched_lock);
|
||||
|
||||
/* kick off the clock on this AP */
|
||||
ia64_set_itm(ia64_get_itc() + itm_reload);
|
||||
ia64_set_itv(CLOCK_VECTOR);
|
||||
ia64_set_tpr(0);
|
||||
|
||||
/* kick off the clock on this AP */
|
||||
pcpu_initclock();
|
||||
|
||||
cpu_throw(NULL, choosethread());
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
@ -1,110 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 1993 The Regents of the University of California.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
|
||||
* 4. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
*
|
||||
* Register definitions for the Intel 8253 Programmable Interval Timer.
|
||||
*
|
||||
* This chip has three independent 16-bit down counters that can be
|
||||
* read on the fly. There are three mode registers and three countdown
|
||||
* registers. The countdown registers are addressed directly, via the
|
||||
* first three I/O ports. The three mode registers are accessed via
|
||||
* the fourth I/O port, with two bits in the mode byte indicating the
|
||||
* register. (Why are hardware interfaces always so braindead?).
|
||||
*
|
||||
* To write a value into the countdown register, the mode register
|
||||
* is first programmed with a command indicating the which byte of
|
||||
* the two byte register is to be modified. The three possibilities
|
||||
* are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
|
||||
* msb (TMR_MR_BOTH).
|
||||
*
|
||||
* To read the current value ("on the fly") from the countdown register,
|
||||
* you write a "latch" command into the mode register, then read the stable
|
||||
* value from the corresponding I/O port. For example, you write
|
||||
* TMR_MR_LATCH into the corresponding mode register. Presumably,
|
||||
* after doing this, a write operation to the I/O port would result
|
||||
* in undefined behavior (but hopefully not fry the chip).
|
||||
* Reading in this manner has no side effects.
|
||||
*
|
||||
* [IBM-PC]
|
||||
* The outputs of the three timers are connected as follows:
|
||||
*
|
||||
* timer 0 -> irq 0
|
||||
* timer 1 -> dma chan 0 (for dram refresh)
|
||||
* timer 2 -> speaker (via keyboard controller)
|
||||
*
|
||||
* Timer 0 is used to call hardclock.
|
||||
* Timer 2 is used to generate console beeps.
|
||||
*
|
||||
* [PC-9801]
|
||||
* The outputs of the three timers are connected as follows:
|
||||
*
|
||||
* timer 0 -> irq 0
|
||||
* timer 1 -> speaker (via keyboard controller)
|
||||
* timer 2 -> RS232C
|
||||
*
|
||||
* Timer 0 is used to call hardclock.
|
||||
* Timer 1 is used to generate console beeps.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Macros for specifying values to be written into a mode register.
|
||||
*/
|
||||
#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */
|
||||
#ifdef PC98
|
||||
#define TIMER_CNTR1 0x3fdb /* timer 1 counter port */
|
||||
#define TIMER_CNTR2 (IO_TIMER1 + 4) /* timer 2 counter port */
|
||||
#define TIMER_MODE (IO_TIMER1 + 6) /* timer mode port */
|
||||
#else
|
||||
#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */
|
||||
#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */
|
||||
#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */
|
||||
#endif
|
||||
#define TIMER_SEL0 0x00 /* select counter 0 */
|
||||
#define TIMER_SEL1 0x40 /* select counter 1 */
|
||||
#define TIMER_SEL2 0x80 /* select counter 2 */
|
||||
#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */
|
||||
#define TIMER_ONESHOT 0x02 /* mode 1, one shot */
|
||||
#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */
|
||||
#define TIMER_SQWAVE 0x06 /* mode 3, square wave */
|
||||
#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */
|
||||
#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */
|
||||
#define TIMER_LATCH 0x00 /* latch counter for reading */
|
||||
#define TIMER_LSB 0x10 /* r/w counter LSB */
|
||||
#define TIMER_MSB 0x20 /* r/w counter MSB */
|
||||
#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */
|
||||
#define TIMER_BCD 0x01 /* count in BCD */
|
||||
|
||||
@ -13,16 +13,14 @@
|
||||
|
||||
#define CLOCK_VECTOR 254
|
||||
|
||||
extern int disable_rtc_set;
|
||||
extern int wall_cmos_clock;
|
||||
extern int adjkerntz;
|
||||
extern int adjkerntz;
|
||||
extern int disable_rtc_set;
|
||||
extern int wall_cmos_clock;
|
||||
|
||||
extern u_int64_t itc_frequency;
|
||||
extern u_int64_t itm_reload;
|
||||
extern uint64_t ia64_clock_reload;
|
||||
extern uint64_t itc_frequency;
|
||||
|
||||
int sysbeep(int pitch, int period);
|
||||
int acquire_timer2(int mode);
|
||||
int release_timer2(void);
|
||||
int sysbeep(int pitch, int period);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@ -75,18 +75,14 @@ struct clockframe {
|
||||
* CTL_MACHDEP definitions.
|
||||
*/
|
||||
#define CPU_CONSDEV 1 /* dev_t: console terminal device */
|
||||
#define CPU_ROOT_DEVICE 2 /* string: root device name */
|
||||
#define CPU_BOOTED_KERNEL 3 /* string: booted kernel name */
|
||||
#define CPU_ADJKERNTZ 4 /* int: timezone offset (seconds) */
|
||||
#define CPU_DISRTCSET 5 /* int: disable resettodr() call */
|
||||
#define CPU_WALLCLOCK 6 /* int: indicates wall CMOS clock */
|
||||
#define CPU_MAXID 7 /* valid machdep IDs */
|
||||
#define CPU_ADJKERNTZ 2 /* int: timezone offset (seconds) */
|
||||
#define CPU_DISRTCSET 3 /* int: disable resettodr() call */
|
||||
#define CPU_WALLCLOCK 4 /* int: indicates wall CMOS clock */
|
||||
#define CPU_MAXID 5 /* valid machdep IDs */
|
||||
|
||||
#define CTL_MACHDEP_NAMES { \
|
||||
{ 0, 0 }, \
|
||||
{ "console_device", CTLTYPE_STRUCT }, \
|
||||
{ "root_device", CTLTYPE_STRING }, \
|
||||
{ "booted_kernel", CTLTYPE_STRING }, \
|
||||
{ "adjkerntz", CTLTYPE_INT }, \
|
||||
{ "disable_rtc_set", CTLTYPE_INT }, \
|
||||
{ "wall_cmos_clock", CTLTYPE_INT }, \
|
||||
@ -100,11 +96,6 @@ struct reg;
|
||||
struct rpb;
|
||||
struct trapframe;
|
||||
|
||||
extern struct rpb *hwrpb;
|
||||
extern volatile int mc_expected, mc_received;
|
||||
|
||||
int badaddr(void *, size_t);
|
||||
int badaddr_read(void *, size_t, void *);
|
||||
u_int64_t console_restart(u_int64_t, u_int64_t, u_int64_t);
|
||||
int do_ast(struct trapframe *);
|
||||
void dumpconf(void);
|
||||
@ -118,8 +109,6 @@ void init_prom_interface(struct rpb*);
|
||||
void interrupt(u_int64_t, struct trapframe *);
|
||||
void machine_check(unsigned long, struct trapframe *, unsigned long,
|
||||
unsigned long);
|
||||
u_int64_t hwrpb_checksum(void);
|
||||
void hwrpb_restart_setup(void);
|
||||
void regdump(struct trapframe *);
|
||||
void regtoframe(struct reg *, struct trapframe *);
|
||||
void set_iointr(void (*)(void *, unsigned long));
|
||||
|
||||
@ -35,8 +35,10 @@
|
||||
#define PCPU_MD_FIELDS \
|
||||
struct pcb *pc_pcb; /* Used by IPI_STOP */ \
|
||||
struct pmap *pc_current_pmap; /* active pmap */ \
|
||||
u_int64_t pc_lid; /* local CPU ID */ \
|
||||
u_int32_t pc_awake:1; /* CPU is awake? */
|
||||
uint64_t pc_lid; /* local CPU ID */ \
|
||||
uint32_t pc_awake:1; /* CPU is awake? */ \
|
||||
uint64_t pc_clock; /* Clock counter. */ \
|
||||
uint64_t pc_clockadj; /* Clock adjust. */
|
||||
|
||||
struct pcpu;
|
||||
|
||||
@ -46,6 +48,8 @@ register struct pcpu *pcpup __asm__("r13");
|
||||
#define PCPU_PTR(member) (&pcpup->pc_ ## member)
|
||||
#define PCPU_SET(member,value) (pcpup->pc_ ## member = (value))
|
||||
|
||||
void pcpu_initclock(void);
|
||||
|
||||
#endif /* _KERNEL */
|
||||
|
||||
#endif /* !_MACHINE_PCPU_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user