Driver for Apple Keywest I2C controllers found in MacIO ASICs. Used for
power and thermal control, as well as GPIOs on Xserves and controlling sound codecs for Apple built-in audio. Submitted by: Marco Trillo Obtained from: NetBSD
This commit is contained in:
parent
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commit
a9cade51ed
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=187262
@ -113,6 +113,7 @@ powerpc/powermac/ata_dbdma.c optional powermac ata
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powerpc/powermac/dbdma.c optional powermac pci
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powerpc/powermac/grackle.c optional powermac pci
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powerpc/powermac/hrowpic.c optional powermac pci
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powerpc/powermac/kiic.c optional powermac kiic
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powerpc/powermac/macio.c optional powermac pci
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powerpc/powermac/openpic_macio.c optional powermac pci
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powerpc/powermac/pswitch.c optional powermac pswitch
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@ -25,6 +25,7 @@ options SC_OFWFB # OFW frame buffer
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device pci
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device bm # Apple BMAC (Big Mac Ethernet)
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device kiic # Apple Keywest I2C Controller
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device ofwd # Open Firmware disks
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device adb # Apple Desktop Bus
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device cuda # VIA-CUDA ADB interface
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391
sys/powerpc/powermac/kiic.c
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391
sys/powerpc/powermac/kiic.c
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@ -0,0 +1,391 @@
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/*-
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* Copyright (c) 2001 Tsubai Masanari. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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* NetBSD: ki2c.c,v 1.11 2007/12/06 17:00:33 ad Exp
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* Id: ki2c.c,v 1.7 2002/10/05 09:56:05 tsubai Exp
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*/
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/*
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* Support routines for the Keywest I2C controller.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/ofw/ofw_bus.h>
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#include "iicbus_if.h"
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/* Keywest I2C Register offsets */
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#define MODE 0
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#define CONTROL 1
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#define STATUS 2
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#define ISR 3
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#define IER 4
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#define ADDR 5
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#define SUBADDR 6
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#define DATA 7
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/* MODE */
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#define I2C_SPEED 0x03 /* Speed mask */
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#define I2C_100kHz 0x00
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#define I2C_50kHz 0x01
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#define I2C_25kHz 0x02
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#define I2C_MODE 0x0c /* Mode mask */
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#define I2C_DUMBMODE 0x00 /* Dumb mode */
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#define I2C_STDMODE 0x04 /* Standard mode */
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#define I2C_STDSUBMODE 0x08 /* Standard mode + sub address */
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#define I2C_COMBMODE 0x0c /* Combined mode */
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#define I2C_PORT 0xf0 /* Port mask */
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/* CONTROL */
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#define I2C_CT_AAK 0x01 /* Send AAK */
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#define I2C_CT_ADDR 0x02 /* Send address(es) */
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#define I2C_CT_STOP 0x04 /* Send STOP */
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#define I2C_CT_START 0x08 /* Send START */
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/* STATUS */
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#define I2C_ST_BUSY 0x01 /* Busy */
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#define I2C_ST_LASTAAK 0x02 /* Last AAK */
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#define I2C_ST_LASTRW 0x04 /* Last R/W */
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#define I2C_ST_SDA 0x08 /* SDA */
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#define I2C_ST_SCL 0x10 /* SCL */
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/* ISR/IER */
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#define I2C_INT_DATA 0x01 /* Data byte sent/received */
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#define I2C_INT_ADDR 0x02 /* Address sent */
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#define I2C_INT_STOP 0x04 /* STOP condition sent */
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#define I2C_INT_START 0x08 /* START condition sent */
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/* I2C flags */
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#define I2C_BUSY 0x01
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#define I2C_READING 0x02
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#define I2C_ERROR 0x04
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#define I2C_SELECTED 0x08
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struct kiic_softc {
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device_t sc_dev;
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phandle_t sc_node;
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struct mtx sc_mutex;
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struct resource *sc_reg;
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int sc_irqrid;
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struct resource *sc_irq;
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void *sc_ih;
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u_int sc_regstep;
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u_int sc_flags;
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u_char *sc_data;
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int sc_resid;
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device_t sc_iicbus;
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};
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static int kiic_probe(device_t dev);
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static int kiic_attach(device_t dev);
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static void kiic_writereg(struct kiic_softc *sc, u_int, u_int);
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static u_int kiic_readreg(struct kiic_softc *, u_int);
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static void kiic_setmode(struct kiic_softc *, u_int);
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static void kiic_setspeed(struct kiic_softc *, u_int);
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static void kiic_intr(void *xsc);
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static int kiic_transfer(device_t dev, struct iic_msg *msgs,
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uint32_t nmsgs);
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static phandle_t kiic_get_node(device_t bus, device_t dev);
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static device_method_t kiic_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, kiic_probe),
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DEVMETHOD(device_attach, kiic_attach),
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/* iicbus interface */
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DEVMETHOD(iicbus_callback, iicbus_null_callback),
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DEVMETHOD(iicbus_transfer, kiic_transfer),
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/* ofw_bus interface */
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DEVMETHOD(ofw_bus_get_node, kiic_get_node),
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{ 0, 0 }
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};
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static driver_t kiic_driver = {
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"iichb",
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kiic_methods,
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sizeof(struct kiic_softc)
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};
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static devclass_t kiic_devclass;
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DRIVER_MODULE(kiic, macio, kiic_driver, kiic_devclass, 0, 0);
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static int
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kiic_probe(device_t self)
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{
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const char *name;
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name = ofw_bus_get_name(self);
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if (name && strcmp(name, "i2c") == 0) {
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device_set_desc(self, "Keywest I2C controller");
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return (0);
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}
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return (ENXIO);
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}
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static int
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kiic_attach(device_t self)
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{
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struct kiic_softc *sc = device_get_softc(self);
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int rid, rate;
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phandle_t node;
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char name[64];
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bzero(sc, sizeof(*sc));
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sc->sc_dev = self;
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node = ofw_bus_get_node(self);
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if (node == 0 || node == -1) {
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return (EINVAL);
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}
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rid = 0;
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sc->sc_reg = bus_alloc_resource_any(self, SYS_RES_MEMORY,
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&rid, RF_ACTIVE);
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if (sc->sc_reg == NULL) {
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return (ENOMEM);
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}
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if (OF_getprop(node, "AAPL,i2c-rate", &rate, 4) != 4) {
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device_printf(self, "cannot get i2c-rate\n");
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return (ENXIO);
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}
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if (OF_getprop(node, "AAPL,address-step", &sc->sc_regstep, 4) != 4) {
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device_printf(self, "unable to find i2c address step\n");
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return (ENXIO);
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}
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/*
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* Some Keywest I2C devices have their children attached directly
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* underneath them. Some have a single 'iicbus' child with the
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* devices underneath that. Sort this out, and make sure that the
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* OFW I2C layer has the correct node.
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*/
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sc->sc_node = OF_child(node);
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if (OF_getprop(sc->sc_node,"name",name,sizeof(name)) > 0) {
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if (strcmp(name,"i2c-bus") != 0)
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sc->sc_node = node;
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}
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mtx_init(&sc->sc_mutex, "kiic", NULL, MTX_DEF);
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sc->sc_irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &sc->sc_irqrid,
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RF_ACTIVE);
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bus_setup_intr(self, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE, NULL,
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kiic_intr, sc, &sc->sc_ih);
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kiic_writereg(sc, STATUS, 0);
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kiic_writereg(sc, ISR, 0);
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kiic_writereg(sc, IER, 0);
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kiic_setmode(sc, I2C_STDMODE);
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kiic_setspeed(sc, I2C_100kHz); /* XXX rate */
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kiic_writereg(sc, IER, I2C_INT_DATA | I2C_INT_ADDR | I2C_INT_STOP);
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/* Add the IIC bus layer */
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sc->sc_iicbus = device_add_child(self, "iicbus", -1);
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return (bus_generic_attach(self));
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}
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static void
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kiic_writereg(struct kiic_softc *sc, u_int reg, u_int val)
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{
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bus_write_1(sc->sc_reg, sc->sc_regstep * reg, val);
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DELAY(10); /* XXX why? */
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}
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static u_int
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kiic_readreg(struct kiic_softc *sc, u_int reg)
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{
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return bus_read_1(sc->sc_reg, sc->sc_regstep * reg);
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}
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static void
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kiic_setmode(struct kiic_softc *sc, u_int mode)
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{
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u_int x;
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KASSERT((mode & ~I2C_MODE) == 0, ("bad mode"));
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x = kiic_readreg(sc, MODE);
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x &= ~I2C_MODE;
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x |= mode;
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kiic_writereg(sc, MODE, x);
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}
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static void
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kiic_setspeed(struct kiic_softc *sc, u_int speed)
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{
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u_int x;
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KASSERT((speed & ~I2C_SPEED) == 0, ("bad speed"));
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x = kiic_readreg(sc, MODE);
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x &= ~I2C_SPEED;
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x |= speed;
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kiic_writereg(sc, MODE, x);
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}
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static void
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kiic_intr(void *xsc)
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{
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struct kiic_softc *sc = xsc;
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u_int isr;
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uint32_t x;
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mtx_lock(&sc->sc_mutex);
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isr = kiic_readreg(sc, ISR);
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if (isr & I2C_INT_ADDR) {
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sc->sc_flags |= I2C_SELECTED;
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if (sc->sc_flags & I2C_READING) {
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if (sc->sc_resid > 1) {
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x = kiic_readreg(sc, CONTROL);
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x |= I2C_CT_AAK;
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kiic_writereg(sc, CONTROL, x);
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}
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} else {
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kiic_writereg(sc, DATA, *sc->sc_data++);
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sc->sc_resid--;
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}
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}
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if (isr & I2C_INT_DATA) {
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if (sc->sc_resid > 0) {
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if (sc->sc_flags & I2C_READING) {
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*sc->sc_data++ = kiic_readreg(sc, DATA);
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sc->sc_resid--;
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} else {
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kiic_writereg(sc, DATA, *sc->sc_data++);
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sc->sc_resid--;
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}
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}
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if (sc->sc_resid == 0)
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wakeup(sc->sc_dev);
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}
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if (isr & I2C_INT_STOP) {
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kiic_writereg(sc, CONTROL, 0);
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sc->sc_flags &= ~I2C_SELECTED;
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wakeup(sc->sc_dev);
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}
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kiic_writereg(sc, ISR, isr);
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mtx_unlock(&sc->sc_mutex);
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}
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static int
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kiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
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{
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struct kiic_softc *sc;
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int i, x, timo;
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uint8_t addr;
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sc = device_get_softc(dev);
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timo = 100;
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mtx_lock(&sc->sc_mutex);
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if (sc->sc_flags & I2C_BUSY)
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mtx_sleep(dev, &sc->sc_mutex, 0, "kiic", timo);
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if (sc->sc_flags & I2C_BUSY) {
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mtx_unlock(&sc->sc_mutex);
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return (ETIMEDOUT);
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}
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sc->sc_flags = I2C_BUSY;
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for (i = 0; i < nmsgs; i++) {
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sc->sc_data = msgs[i].buf;
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sc->sc_resid = msgs[i].len;
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sc->sc_flags = I2C_BUSY;
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addr = msgs[i].slave;
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timo = 1000 + sc->sc_resid * 200;
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if (msgs[i].flags & IIC_M_RD) {
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sc->sc_flags |= I2C_READING;
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addr |= 1;
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}
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kiic_writereg(sc, ADDR, addr);
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kiic_writereg(sc, SUBADDR, 0x04);
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x = kiic_readreg(sc, CONTROL) | I2C_CT_ADDR;
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kiic_writereg(sc, CONTROL, x);
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mtx_sleep(dev, &sc->sc_mutex, 0, "kiic", timo);
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if (!(sc->sc_flags & I2C_READING)) {
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x = kiic_readreg(sc, CONTROL) | I2C_CT_STOP;
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kiic_writereg(sc, CONTROL, x);
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}
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mtx_sleep(dev, &sc->sc_mutex, 0, "kiic", timo);
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msgs[i].len -= sc->sc_resid;
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if (sc->sc_flags & I2C_ERROR) {
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device_printf(sc->sc_dev, "I2C_ERROR\n");
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mtx_unlock(&sc->sc_mutex);
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return (-1);
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}
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}
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sc->sc_flags = 0;
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mtx_unlock(&sc->sc_mutex);
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return (0);
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}
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static phandle_t
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kiic_get_node(device_t bus, device_t dev)
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{
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struct kiic_softc *sc;
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sc = device_get_softc(bus);
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/* We only have one child, the I2C bus, which needs our own node. */
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return sc->sc_node;
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}
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